2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
57 #include <linux/if_vlan.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
102 * detected as not set during a prior frame transmission, then the
103 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
104 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
105 * frames not being transmitted until there is a 0-to-1 transition on
108 #define FEC_QUIRK_ERR006358 (1 << 7)
110 static struct platform_device_id fec_devtype[] = {
112 /* keep it for coldfire */
117 .driver_data = FEC_QUIRK_USE_GASKET,
123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
126 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
127 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
128 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
130 .name = "mvf600-fec",
131 .driver_data = FEC_QUIRK_ENET_MAC,
136 MODULE_DEVICE_TABLE(platform, fec_devtype);
139 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
140 IMX27_FEC, /* runs on i.mx27/35/51 */
146 static const struct of_device_id fec_dt_ids[] = {
147 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
148 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
149 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
150 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
151 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
154 MODULE_DEVICE_TABLE(of, fec_dt_ids);
156 static unsigned char macaddr[ETH_ALEN];
157 module_param_array(macaddr, byte, NULL, 0);
158 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
160 #if defined(CONFIG_M5272)
162 * Some hardware gets it MAC address out of local flash memory.
163 * if this is non-zero then assume it is the address to get MAC from.
165 #if defined(CONFIG_NETtel)
166 #define FEC_FLASHMAC 0xf0006006
167 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
168 #define FEC_FLASHMAC 0xf0006000
169 #elif defined(CONFIG_CANCam)
170 #define FEC_FLASHMAC 0xf0020000
171 #elif defined (CONFIG_M5272C3)
172 #define FEC_FLASHMAC (0xffe04000 + 4)
173 #elif defined(CONFIG_MOD5272)
174 #define FEC_FLASHMAC 0xffc0406b
176 #define FEC_FLASHMAC 0
178 #endif /* CONFIG_M5272 */
180 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
181 #error "FEC: descriptor ring size constants too large"
184 /* Interrupt events/masks. */
185 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
186 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
187 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
188 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
189 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
190 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
191 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
192 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
193 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
194 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
196 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
197 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
199 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
201 #define PKT_MAXBUF_SIZE 1522
202 #define PKT_MINBUF_SIZE 64
203 #define PKT_MAXBLR_SIZE 1536
205 /* FEC receive acceleration */
206 #define FEC_RACC_IPDIS (1 << 1)
207 #define FEC_RACC_PRODIS (1 << 2)
208 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
211 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
212 * size bits. Other FEC hardware does not, so we need to take that into
213 * account when setting it.
215 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
216 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
217 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
219 #define OPT_FRAME_SIZE 0
222 /* FEC MII MMFR bits definition */
223 #define FEC_MMFR_ST (1 << 30)
224 #define FEC_MMFR_OP_READ (2 << 28)
225 #define FEC_MMFR_OP_WRITE (1 << 28)
226 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
227 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
228 #define FEC_MMFR_TA (2 << 16)
229 #define FEC_MMFR_DATA(v) (v & 0xffff)
231 #define FEC_MII_TIMEOUT 30000 /* us */
233 /* Transmitter timeout */
234 #define TX_TIMEOUT (2 * HZ)
236 #define FEC_PAUSE_FLAG_AUTONEG 0x1
237 #define FEC_PAUSE_FLAG_ENABLE 0x2
242 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
244 struct bufdesc *new_bd = bdp + 1;
245 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
246 struct bufdesc_ex *ex_base;
247 struct bufdesc *base;
250 if (bdp >= fep->tx_bd_base) {
251 base = fep->tx_bd_base;
252 ring_size = fep->tx_ring_size;
253 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
255 base = fep->rx_bd_base;
256 ring_size = fep->rx_ring_size;
257 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
261 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
262 ex_base : ex_new_bd);
264 return (new_bd >= (base + ring_size)) ?
269 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
271 struct bufdesc *new_bd = bdp - 1;
272 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
273 struct bufdesc_ex *ex_base;
274 struct bufdesc *base;
277 if (bdp >= fep->tx_bd_base) {
278 base = fep->tx_bd_base;
279 ring_size = fep->tx_ring_size;
280 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
282 base = fep->rx_bd_base;
283 ring_size = fep->rx_ring_size;
284 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
288 return (struct bufdesc *)((ex_new_bd < ex_base) ?
289 (ex_new_bd + ring_size) : ex_new_bd);
291 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
294 static void *swap_buffer(void *bufaddr, int len)
297 unsigned int *buf = bufaddr;
299 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
300 *buf = cpu_to_be32(*buf);
306 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
308 /* Only run for packets requiring a checksum. */
309 if (skb->ip_summed != CHECKSUM_PARTIAL)
312 if (unlikely(skb_cow_head(skb, 0)))
315 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
321 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
323 struct fec_enet_private *fep = netdev_priv(ndev);
324 const struct platform_device_id *id_entry =
325 platform_get_device_id(fep->pdev);
326 struct bufdesc *bdp, *bdp_pre;
328 unsigned short status;
331 /* Fill in a Tx ring entry */
334 status = bdp->cbd_sc;
336 if (status & BD_ENET_TX_READY) {
337 /* Ooops. All transmit buffers are full. Bail out.
338 * This should not happen, since ndev->tbusy should be set.
340 netdev_err(ndev, "tx queue full!\n");
341 return NETDEV_TX_BUSY;
344 /* Protocol checksum off-load for TCP and UDP. */
345 if (fec_enet_clear_csum(skb, ndev)) {
350 /* Clear all of the status flags */
351 status &= ~BD_ENET_TX_STATS;
353 /* Set buffer length and buffer pointer */
355 bdp->cbd_datlen = skb->len;
358 * On some FEC implementations data must be aligned on
359 * 4-byte boundaries. Use bounce buffers to copy data
360 * and get it aligned. Ugh.
363 index = (struct bufdesc_ex *)bdp -
364 (struct bufdesc_ex *)fep->tx_bd_base;
366 index = bdp - fep->tx_bd_base;
368 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
369 memcpy(fep->tx_bounce[index], skb->data, skb->len);
370 bufaddr = fep->tx_bounce[index];
374 * Some design made an incorrect assumption on endian mode of
375 * the system that it's running on. As the result, driver has to
376 * swap every frame going to and coming from the controller.
378 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
379 swap_buffer(bufaddr, skb->len);
381 /* Save skb pointer */
382 fep->tx_skbuff[index] = skb;
384 /* Push the data cache so the CPM does not get stale memory
387 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
388 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
389 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr))
390 return NETDEV_TX_BUSY;
392 /* Send it on its way. Tell FEC it's ready, interrupt when done,
393 * it's the last BD of the frame, and to put the CRC on the end.
395 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
396 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
397 bdp->cbd_sc = status;
399 if (fep->bufdesc_ex) {
401 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
403 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
405 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
406 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
408 ebdp->cbd_esc = BD_ENET_TX_INT;
410 /* Enable protocol checksum flags
411 * We do not bother with the IP Checksum bits as they
412 * are done by the kernel
414 if (skb->ip_summed == CHECKSUM_PARTIAL)
415 ebdp->cbd_esc |= BD_ENET_TX_PINS;
419 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
420 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
421 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
422 fep->delay_work.trig_tx = true;
423 schedule_delayed_work(&(fep->delay_work.delay_work),
424 msecs_to_jiffies(1));
427 /* If this was the last BD in the ring, start at the beginning again. */
428 bdp = fec_enet_get_nextdesc(bdp, fep);
432 if (fep->cur_tx == fep->dirty_tx)
433 netif_stop_queue(ndev);
435 /* Trigger transmission start */
436 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
438 skb_tx_timestamp(skb);
443 /* Init RX & TX buffer descriptors
445 static void fec_enet_bd_init(struct net_device *dev)
447 struct fec_enet_private *fep = netdev_priv(dev);
451 /* Initialize the receive buffer descriptors. */
452 bdp = fep->rx_bd_base;
453 for (i = 0; i < fep->rx_ring_size; i++) {
455 /* Initialize the BD for every fragment in the page. */
456 if (bdp->cbd_bufaddr)
457 bdp->cbd_sc = BD_ENET_RX_EMPTY;
460 bdp = fec_enet_get_nextdesc(bdp, fep);
463 /* Set the last buffer to wrap */
464 bdp = fec_enet_get_prevdesc(bdp, fep);
465 bdp->cbd_sc |= BD_SC_WRAP;
467 fep->cur_rx = fep->rx_bd_base;
469 /* ...and the same for transmit */
470 bdp = fep->tx_bd_base;
472 for (i = 0; i < fep->tx_ring_size; i++) {
474 /* Initialize the BD for every fragment in the page. */
476 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
477 dev_kfree_skb_any(fep->tx_skbuff[i]);
478 fep->tx_skbuff[i] = NULL;
480 bdp->cbd_bufaddr = 0;
481 bdp = fec_enet_get_nextdesc(bdp, fep);
484 /* Set the last buffer to wrap */
485 bdp = fec_enet_get_prevdesc(bdp, fep);
486 bdp->cbd_sc |= BD_SC_WRAP;
490 /* This function is called to start or restart the FEC during a link
491 * change. This only happens when switching between half and full
495 fec_restart(struct net_device *ndev, int duplex)
497 struct fec_enet_private *fep = netdev_priv(ndev);
498 const struct platform_device_id *id_entry =
499 platform_get_device_id(fep->pdev);
503 u32 rcntl = OPT_FRAME_SIZE | 0x04;
504 u32 ecntl = 0x2; /* ETHEREN */
506 if (netif_running(ndev)) {
507 netif_device_detach(ndev);
508 napi_disable(&fep->napi);
509 netif_stop_queue(ndev);
510 netif_tx_lock_bh(ndev);
513 /* Whack a reset. We should wait for this. */
514 writel(1, fep->hwp + FEC_ECNTRL);
518 * enet-mac reset will reset mac address registers too,
519 * so need to reconfigure it.
521 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
522 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
523 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
524 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
527 /* Clear any outstanding interrupt. */
528 writel(0xffc00000, fep->hwp + FEC_IEVENT);
530 /* Setup multicast filter. */
531 set_multicast_list(ndev);
533 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
534 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
537 /* Set maximum receive buffer size. */
538 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
540 fec_enet_bd_init(ndev);
542 /* Set receive and transmit descriptor base. */
543 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
545 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
546 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
548 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
549 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
552 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
553 if (fep->tx_skbuff[i]) {
554 dev_kfree_skb_any(fep->tx_skbuff[i]);
555 fep->tx_skbuff[i] = NULL;
559 /* Enable MII mode */
562 writel(0x04, fep->hwp + FEC_X_CNTRL);
566 writel(0x0, fep->hwp + FEC_X_CNTRL);
569 fep->full_duplex = duplex;
572 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
574 #if !defined(CONFIG_M5272)
575 /* set RX checksum */
576 val = readl(fep->hwp + FEC_RACC);
577 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
578 val |= FEC_RACC_OPTIONS;
580 val &= ~FEC_RACC_OPTIONS;
581 writel(val, fep->hwp + FEC_RACC);
585 * The phy interface and speed need to get configured
586 * differently on enet-mac.
588 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
589 /* Enable flow control and length check */
590 rcntl |= 0x40000000 | 0x00000020;
592 /* RGMII, RMII or MII */
593 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
595 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
600 /* 1G, 100M or 10M */
602 if (fep->phy_dev->speed == SPEED_1000)
604 else if (fep->phy_dev->speed == SPEED_100)
610 #ifdef FEC_MIIGSK_ENR
611 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
613 /* disable the gasket and wait */
614 writel(0, fep->hwp + FEC_MIIGSK_ENR);
615 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
619 * configure the gasket:
620 * RMII, 50 MHz, no loopback, no echo
621 * MII, 25 MHz, no loopback, no echo
623 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
624 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
625 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
626 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
627 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
629 /* re-enable the gasket */
630 writel(2, fep->hwp + FEC_MIIGSK_ENR);
635 #if !defined(CONFIG_M5272)
636 /* enable pause frame*/
637 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
638 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
639 fep->phy_dev && fep->phy_dev->pause)) {
640 rcntl |= FEC_ENET_FCE;
642 /* set FIFO threshold parameter to reduce overrun */
643 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
644 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
645 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
646 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
649 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
651 rcntl &= ~FEC_ENET_FCE;
653 #endif /* !defined(CONFIG_M5272) */
655 writel(rcntl, fep->hwp + FEC_R_CNTRL);
657 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
658 /* enable ENET endian swap */
660 /* enable ENET store and forward mode */
661 writel(1 << 8, fep->hwp + FEC_X_WMRK);
668 /* Enable the MIB statistic event counters */
669 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
672 /* And last, enable the transmit and receive processing */
673 writel(ecntl, fep->hwp + FEC_ECNTRL);
674 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
677 fec_ptp_start_cyclecounter(ndev);
679 /* Enable interrupts we wish to service */
680 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
682 if (netif_running(ndev)) {
683 netif_tx_unlock_bh(ndev);
684 netif_wake_queue(ndev);
685 napi_enable(&fep->napi);
686 netif_device_attach(ndev);
691 fec_stop(struct net_device *ndev)
693 struct fec_enet_private *fep = netdev_priv(ndev);
694 const struct platform_device_id *id_entry =
695 platform_get_device_id(fep->pdev);
696 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
698 /* We cannot expect a graceful transmit stop without link !!! */
700 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
702 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
703 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
706 /* Whack a reset. We should wait for this. */
707 writel(1, fep->hwp + FEC_ECNTRL);
709 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
710 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
712 /* We have to keep ENET enabled to have MII interrupt stay working */
713 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
714 writel(2, fep->hwp + FEC_ECNTRL);
715 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
721 fec_timeout(struct net_device *ndev)
723 struct fec_enet_private *fep = netdev_priv(ndev);
725 ndev->stats.tx_errors++;
727 fep->delay_work.timeout = true;
728 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
731 static void fec_enet_work(struct work_struct *work)
733 struct fec_enet_private *fep =
735 struct fec_enet_private,
736 delay_work.delay_work.work);
738 if (fep->delay_work.timeout) {
739 fep->delay_work.timeout = false;
740 fec_restart(fep->netdev, fep->full_duplex);
741 netif_wake_queue(fep->netdev);
744 if (fep->delay_work.trig_tx) {
745 fep->delay_work.trig_tx = false;
746 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
751 fec_enet_tx(struct net_device *ndev)
753 struct fec_enet_private *fep;
755 unsigned short status;
759 fep = netdev_priv(ndev);
762 /* get next bdp of dirty_tx */
763 bdp = fec_enet_get_nextdesc(bdp, fep);
765 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
767 /* current queue is empty */
768 if (bdp == fep->cur_tx)
772 index = (struct bufdesc_ex *)bdp -
773 (struct bufdesc_ex *)fep->tx_bd_base;
775 index = bdp - fep->tx_bd_base;
777 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
778 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
779 bdp->cbd_bufaddr = 0;
781 skb = fep->tx_skbuff[index];
783 /* Check for errors. */
784 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
785 BD_ENET_TX_RL | BD_ENET_TX_UN |
787 ndev->stats.tx_errors++;
788 if (status & BD_ENET_TX_HB) /* No heartbeat */
789 ndev->stats.tx_heartbeat_errors++;
790 if (status & BD_ENET_TX_LC) /* Late collision */
791 ndev->stats.tx_window_errors++;
792 if (status & BD_ENET_TX_RL) /* Retrans limit */
793 ndev->stats.tx_aborted_errors++;
794 if (status & BD_ENET_TX_UN) /* Underrun */
795 ndev->stats.tx_fifo_errors++;
796 if (status & BD_ENET_TX_CSL) /* Carrier lost */
797 ndev->stats.tx_carrier_errors++;
799 ndev->stats.tx_packets++;
800 ndev->stats.tx_bytes += bdp->cbd_datlen;
803 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
805 struct skb_shared_hwtstamps shhwtstamps;
807 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
809 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
810 spin_lock_irqsave(&fep->tmreg_lock, flags);
811 shhwtstamps.hwtstamp = ns_to_ktime(
812 timecounter_cyc2time(&fep->tc, ebdp->ts));
813 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
814 skb_tstamp_tx(skb, &shhwtstamps);
817 if (status & BD_ENET_TX_READY)
818 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
820 /* Deferred means some collisions occurred during transmit,
821 * but we eventually sent the packet OK.
823 if (status & BD_ENET_TX_DEF)
824 ndev->stats.collisions++;
826 /* Free the sk buffer associated with this last transmit */
827 dev_kfree_skb_any(skb);
828 fep->tx_skbuff[index] = NULL;
832 /* Update pointer to next buffer descriptor to be transmitted */
833 bdp = fec_enet_get_nextdesc(bdp, fep);
835 /* Since we have freed up a buffer, the ring is no longer full
837 if (fep->dirty_tx != fep->cur_tx) {
838 if (netif_queue_stopped(ndev))
839 netif_wake_queue(ndev);
846 /* During a receive, the cur_rx points to the current incoming buffer.
847 * When we update through the ring, if the next incoming buffer has
848 * not been given to the system, we just set the empty indicator,
849 * effectively tossing the packet.
852 fec_enet_rx(struct net_device *ndev, int budget)
854 struct fec_enet_private *fep = netdev_priv(ndev);
855 const struct platform_device_id *id_entry =
856 platform_get_device_id(fep->pdev);
858 unsigned short status;
862 int pkt_received = 0;
863 struct bufdesc_ex *ebdp = NULL;
864 bool vlan_packet_rcvd = false;
871 /* First, grab all of the stats for the incoming packet.
872 * These get messed up if we get called due to a busy condition.
876 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
878 if (pkt_received >= budget)
882 /* Since we have allocated space to hold a complete frame,
883 * the last indicator should be set.
885 if ((status & BD_ENET_RX_LAST) == 0)
886 netdev_err(ndev, "rcv is not +last\n");
889 goto rx_processing_done;
891 /* Check for errors. */
892 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
893 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
894 ndev->stats.rx_errors++;
895 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
896 /* Frame too long or too short. */
897 ndev->stats.rx_length_errors++;
899 if (status & BD_ENET_RX_NO) /* Frame alignment */
900 ndev->stats.rx_frame_errors++;
901 if (status & BD_ENET_RX_CR) /* CRC Error */
902 ndev->stats.rx_crc_errors++;
903 if (status & BD_ENET_RX_OV) /* FIFO overrun */
904 ndev->stats.rx_fifo_errors++;
907 /* Report late collisions as a frame error.
908 * On this error, the BD is closed, but we don't know what we
909 * have in the buffer. So, just drop this frame on the floor.
911 if (status & BD_ENET_RX_CL) {
912 ndev->stats.rx_errors++;
913 ndev->stats.rx_frame_errors++;
914 goto rx_processing_done;
917 /* Process the incoming frame. */
918 ndev->stats.rx_packets++;
919 pkt_len = bdp->cbd_datlen;
920 ndev->stats.rx_bytes += pkt_len;
921 data = (__u8*)__va(bdp->cbd_bufaddr);
923 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
924 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
926 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
927 swap_buffer(data, pkt_len);
929 /* Extract the enhanced buffer descriptor */
932 ebdp = (struct bufdesc_ex *)bdp;
934 /* If this is a VLAN packet remove the VLAN Tag */
935 vlan_packet_rcvd = false;
936 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
937 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
938 /* Push and remove the vlan tag */
939 struct vlan_hdr *vlan_header =
940 (struct vlan_hdr *) (data + ETH_HLEN);
941 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
942 pkt_len -= VLAN_HLEN;
944 vlan_packet_rcvd = true;
947 /* This does 16 byte alignment, exactly what we need.
948 * The packet length includes FCS, but we don't want to
949 * include that when passing upstream as it messes up
950 * bridging applications.
952 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
954 if (unlikely(!skb)) {
955 ndev->stats.rx_dropped++;
957 int payload_offset = (2 * ETH_ALEN);
958 skb_reserve(skb, NET_IP_ALIGN);
959 skb_put(skb, pkt_len - 4); /* Make room */
961 /* Extract the frame data without the VLAN header. */
962 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
963 if (vlan_packet_rcvd)
964 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
965 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
966 data + payload_offset,
967 pkt_len - 4 - (2 * ETH_ALEN));
969 skb->protocol = eth_type_trans(skb, ndev);
971 /* Get receive timestamp from the skb */
972 if (fep->hwts_rx_en && fep->bufdesc_ex) {
973 struct skb_shared_hwtstamps *shhwtstamps =
977 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
979 spin_lock_irqsave(&fep->tmreg_lock, flags);
980 shhwtstamps->hwtstamp = ns_to_ktime(
981 timecounter_cyc2time(&fep->tc, ebdp->ts));
982 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
985 if (fep->bufdesc_ex &&
986 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
987 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
989 skb->ip_summed = CHECKSUM_UNNECESSARY;
991 skb_checksum_none_assert(skb);
995 /* Handle received VLAN packets */
996 if (vlan_packet_rcvd)
997 __vlan_hwaccel_put_tag(skb,
1001 napi_gro_receive(&fep->napi, skb);
1004 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
1005 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
1006 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr))
1007 dev_warn(&fep->pdev->dev,
1008 "Failed to map RX buffer %p for DMA\n", data);
1010 /* Clear the status flags for this buffer */
1011 status &= ~BD_ENET_RX_STATS;
1013 /* Mark the buffer empty */
1014 status |= BD_ENET_RX_EMPTY;
1015 bdp->cbd_sc = status;
1017 if (fep->bufdesc_ex) {
1018 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1020 ebdp->cbd_esc = BD_ENET_RX_INT;
1025 /* Update BD pointer to next entry */
1026 bdp = fec_enet_get_nextdesc(bdp, fep);
1028 /* Doing this here will keep the FEC running while we process
1029 * incoming frames. On a heavily loaded network, we should be
1030 * able to keep up at the expense of system resources.
1032 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1036 return pkt_received;
1040 fec_enet_interrupt(int irq, void *dev_id)
1042 struct net_device *ndev = dev_id;
1043 struct fec_enet_private *fep = netdev_priv(ndev);
1045 irqreturn_t ret = IRQ_NONE;
1048 int_events = readl(fep->hwp + FEC_IEVENT);
1049 writel(int_events, fep->hwp + FEC_IEVENT);
1051 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1054 /* Disable the RX interrupt */
1055 if (napi_schedule_prep(&fep->napi)) {
1056 writel(FEC_RX_DISABLED_IMASK,
1057 fep->hwp + FEC_IMASK);
1058 __napi_schedule(&fep->napi);
1062 if (int_events & FEC_ENET_MII) {
1064 complete(&fep->mdio_done);
1066 } while (int_events);
1071 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1073 struct net_device *ndev = napi->dev;
1074 int pkts = fec_enet_rx(ndev, budget);
1075 struct fec_enet_private *fep = netdev_priv(ndev);
1079 if (pkts < budget) {
1080 napi_complete(napi);
1081 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1086 /* ------------------------------------------------------------------------- */
1087 static void fec_get_mac(struct net_device *ndev)
1089 struct fec_enet_private *fep = netdev_priv(ndev);
1090 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1091 unsigned char *iap, tmpaddr[ETH_ALEN];
1094 * try to get mac address in following order:
1096 * 1) module parameter via kernel command line in form
1097 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1102 * 2) from device tree data
1104 if (!is_valid_ether_addr(iap)) {
1105 struct device_node *np = fep->pdev->dev.of_node;
1107 const char *mac = of_get_mac_address(np);
1109 iap = (unsigned char *) mac;
1114 * 3) from flash or fuse (via platform data)
1116 if (!is_valid_ether_addr(iap)) {
1119 iap = (unsigned char *)FEC_FLASHMAC;
1122 iap = (unsigned char *)&pdata->mac;
1127 * 4) FEC mac registers set by bootloader
1129 if (!is_valid_ether_addr(iap)) {
1130 *((__be32 *) &tmpaddr[0]) =
1131 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1132 *((__be16 *) &tmpaddr[4]) =
1133 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1138 * 5) random mac address
1140 if (!is_valid_ether_addr(iap)) {
1141 /* Report it and use a random ethernet address instead */
1142 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1143 eth_hw_addr_random(ndev);
1144 netdev_info(ndev, "Using random MAC address: %pM\n",
1149 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1151 /* Adjust MAC if using macaddr */
1153 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1156 /* ------------------------------------------------------------------------- */
1161 static void fec_enet_adjust_link(struct net_device *ndev)
1163 struct fec_enet_private *fep = netdev_priv(ndev);
1164 struct phy_device *phy_dev = fep->phy_dev;
1165 int status_change = 0;
1167 /* Prevent a state halted on mii error */
1168 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1169 phy_dev->state = PHY_RESUMING;
1173 if (phy_dev->link) {
1175 fep->link = phy_dev->link;
1179 if (fep->full_duplex != phy_dev->duplex)
1182 if (phy_dev->speed != fep->speed) {
1183 fep->speed = phy_dev->speed;
1187 /* if any of the above changed restart the FEC */
1189 fec_restart(ndev, phy_dev->duplex);
1193 fep->link = phy_dev->link;
1199 phy_print_status(phy_dev);
1202 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1204 struct fec_enet_private *fep = bus->priv;
1205 unsigned long time_left;
1207 fep->mii_timeout = 0;
1208 init_completion(&fep->mdio_done);
1210 /* start a read op */
1211 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1212 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1213 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1215 /* wait for end of transfer */
1216 time_left = wait_for_completion_timeout(&fep->mdio_done,
1217 usecs_to_jiffies(FEC_MII_TIMEOUT));
1218 if (time_left == 0) {
1219 fep->mii_timeout = 1;
1220 netdev_err(fep->netdev, "MDIO read timeout\n");
1225 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1228 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1231 struct fec_enet_private *fep = bus->priv;
1232 unsigned long time_left;
1234 fep->mii_timeout = 0;
1235 init_completion(&fep->mdio_done);
1237 /* start a write op */
1238 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1239 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1240 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1241 fep->hwp + FEC_MII_DATA);
1243 /* wait for end of transfer */
1244 time_left = wait_for_completion_timeout(&fep->mdio_done,
1245 usecs_to_jiffies(FEC_MII_TIMEOUT));
1246 if (time_left == 0) {
1247 fep->mii_timeout = 1;
1248 netdev_err(fep->netdev, "MDIO write timeout\n");
1255 static int fec_enet_mdio_reset(struct mii_bus *bus)
1260 static int fec_enet_mii_probe(struct net_device *ndev)
1262 struct fec_enet_private *fep = netdev_priv(ndev);
1263 const struct platform_device_id *id_entry =
1264 platform_get_device_id(fep->pdev);
1265 struct phy_device *phy_dev = NULL;
1266 char mdio_bus_id[MII_BUS_ID_SIZE];
1267 char phy_name[MII_BUS_ID_SIZE + 3];
1269 int dev_id = fep->dev_id;
1271 fep->phy_dev = NULL;
1273 /* check for attached phy */
1274 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1275 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1277 if (fep->mii_bus->phy_map[phy_id] == NULL)
1279 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1283 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1287 if (phy_id >= PHY_MAX_ADDR) {
1288 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1289 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1293 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1294 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1295 fep->phy_interface);
1296 if (IS_ERR(phy_dev)) {
1297 netdev_err(ndev, "could not attach to PHY\n");
1298 return PTR_ERR(phy_dev);
1301 /* mask with MAC supported features */
1302 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1303 phy_dev->supported &= PHY_GBIT_FEATURES;
1304 #if !defined(CONFIG_M5272)
1305 phy_dev->supported |= SUPPORTED_Pause;
1309 phy_dev->supported &= PHY_BASIC_FEATURES;
1311 phy_dev->advertising = phy_dev->supported;
1313 fep->phy_dev = phy_dev;
1315 fep->full_duplex = 0;
1317 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1318 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1324 static int fec_enet_mii_init(struct platform_device *pdev)
1326 static struct mii_bus *fec0_mii_bus;
1327 struct net_device *ndev = platform_get_drvdata(pdev);
1328 struct fec_enet_private *fep = netdev_priv(ndev);
1329 const struct platform_device_id *id_entry =
1330 platform_get_device_id(fep->pdev);
1331 int err = -ENXIO, i;
1334 * The dual fec interfaces are not equivalent with enet-mac.
1335 * Here are the differences:
1337 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1338 * - fec0 acts as the 1588 time master while fec1 is slave
1339 * - external phys can only be configured by fec0
1341 * That is to say fec1 can not work independently. It only works
1342 * when fec0 is working. The reason behind this design is that the
1343 * second interface is added primarily for Switch mode.
1345 * Because of the last point above, both phys are attached on fec0
1346 * mdio interface in board design, and need to be configured by
1349 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1350 /* fec1 uses fec0 mii_bus */
1351 if (mii_cnt && fec0_mii_bus) {
1352 fep->mii_bus = fec0_mii_bus;
1359 fep->mii_timeout = 0;
1362 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1364 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1365 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1366 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1369 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1370 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1372 fep->phy_speed <<= 1;
1373 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1375 fep->mii_bus = mdiobus_alloc();
1376 if (fep->mii_bus == NULL) {
1381 fep->mii_bus->name = "fec_enet_mii_bus";
1382 fep->mii_bus->read = fec_enet_mdio_read;
1383 fep->mii_bus->write = fec_enet_mdio_write;
1384 fep->mii_bus->reset = fec_enet_mdio_reset;
1385 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1386 pdev->name, fep->dev_id + 1);
1387 fep->mii_bus->priv = fep;
1388 fep->mii_bus->parent = &pdev->dev;
1390 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1391 if (!fep->mii_bus->irq) {
1393 goto err_out_free_mdiobus;
1396 for (i = 0; i < PHY_MAX_ADDR; i++)
1397 fep->mii_bus->irq[i] = PHY_POLL;
1399 if (mdiobus_register(fep->mii_bus))
1400 goto err_out_free_mdio_irq;
1404 /* save fec0 mii_bus */
1405 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1406 fec0_mii_bus = fep->mii_bus;
1410 err_out_free_mdio_irq:
1411 kfree(fep->mii_bus->irq);
1412 err_out_free_mdiobus:
1413 mdiobus_free(fep->mii_bus);
1418 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1420 if (--mii_cnt == 0) {
1421 mdiobus_unregister(fep->mii_bus);
1422 kfree(fep->mii_bus->irq);
1423 mdiobus_free(fep->mii_bus);
1427 static int fec_enet_get_settings(struct net_device *ndev,
1428 struct ethtool_cmd *cmd)
1430 struct fec_enet_private *fep = netdev_priv(ndev);
1431 struct phy_device *phydev = fep->phy_dev;
1436 return phy_ethtool_gset(phydev, cmd);
1439 static int fec_enet_set_settings(struct net_device *ndev,
1440 struct ethtool_cmd *cmd)
1442 struct fec_enet_private *fep = netdev_priv(ndev);
1443 struct phy_device *phydev = fep->phy_dev;
1448 return phy_ethtool_sset(phydev, cmd);
1451 static void fec_enet_get_drvinfo(struct net_device *ndev,
1452 struct ethtool_drvinfo *info)
1454 struct fec_enet_private *fep = netdev_priv(ndev);
1456 strlcpy(info->driver, fep->pdev->dev.driver->name,
1457 sizeof(info->driver));
1458 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1459 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1462 static int fec_enet_get_ts_info(struct net_device *ndev,
1463 struct ethtool_ts_info *info)
1465 struct fec_enet_private *fep = netdev_priv(ndev);
1467 if (fep->bufdesc_ex) {
1469 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1470 SOF_TIMESTAMPING_RX_SOFTWARE |
1471 SOF_TIMESTAMPING_SOFTWARE |
1472 SOF_TIMESTAMPING_TX_HARDWARE |
1473 SOF_TIMESTAMPING_RX_HARDWARE |
1474 SOF_TIMESTAMPING_RAW_HARDWARE;
1476 info->phc_index = ptp_clock_index(fep->ptp_clock);
1478 info->phc_index = -1;
1480 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1481 (1 << HWTSTAMP_TX_ON);
1483 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1484 (1 << HWTSTAMP_FILTER_ALL);
1487 return ethtool_op_get_ts_info(ndev, info);
1491 #if !defined(CONFIG_M5272)
1493 static void fec_enet_get_pauseparam(struct net_device *ndev,
1494 struct ethtool_pauseparam *pause)
1496 struct fec_enet_private *fep = netdev_priv(ndev);
1498 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1499 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1500 pause->rx_pause = pause->tx_pause;
1503 static int fec_enet_set_pauseparam(struct net_device *ndev,
1504 struct ethtool_pauseparam *pause)
1506 struct fec_enet_private *fep = netdev_priv(ndev);
1508 if (pause->tx_pause != pause->rx_pause) {
1510 "hardware only support enable/disable both tx and rx");
1514 fep->pause_flag = 0;
1516 /* tx pause must be same as rx pause */
1517 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1518 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1520 if (pause->rx_pause || pause->autoneg) {
1521 fep->phy_dev->supported |= ADVERTISED_Pause;
1522 fep->phy_dev->advertising |= ADVERTISED_Pause;
1524 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1525 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1528 if (pause->autoneg) {
1529 if (netif_running(ndev))
1531 phy_start_aneg(fep->phy_dev);
1533 if (netif_running(ndev))
1534 fec_restart(ndev, 0);
1539 static const struct fec_stat {
1540 char name[ETH_GSTRING_LEN];
1544 { "tx_dropped", RMON_T_DROP },
1545 { "tx_packets", RMON_T_PACKETS },
1546 { "tx_broadcast", RMON_T_BC_PKT },
1547 { "tx_multicast", RMON_T_MC_PKT },
1548 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1549 { "tx_undersize", RMON_T_UNDERSIZE },
1550 { "tx_oversize", RMON_T_OVERSIZE },
1551 { "tx_fragment", RMON_T_FRAG },
1552 { "tx_jabber", RMON_T_JAB },
1553 { "tx_collision", RMON_T_COL },
1554 { "tx_64byte", RMON_T_P64 },
1555 { "tx_65to127byte", RMON_T_P65TO127 },
1556 { "tx_128to255byte", RMON_T_P128TO255 },
1557 { "tx_256to511byte", RMON_T_P256TO511 },
1558 { "tx_512to1023byte", RMON_T_P512TO1023 },
1559 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1560 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1561 { "tx_octets", RMON_T_OCTETS },
1564 { "IEEE_tx_drop", IEEE_T_DROP },
1565 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1566 { "IEEE_tx_1col", IEEE_T_1COL },
1567 { "IEEE_tx_mcol", IEEE_T_MCOL },
1568 { "IEEE_tx_def", IEEE_T_DEF },
1569 { "IEEE_tx_lcol", IEEE_T_LCOL },
1570 { "IEEE_tx_excol", IEEE_T_EXCOL },
1571 { "IEEE_tx_macerr", IEEE_T_MACERR },
1572 { "IEEE_tx_cserr", IEEE_T_CSERR },
1573 { "IEEE_tx_sqe", IEEE_T_SQE },
1574 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1575 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1578 { "rx_packets", RMON_R_PACKETS },
1579 { "rx_broadcast", RMON_R_BC_PKT },
1580 { "rx_multicast", RMON_R_MC_PKT },
1581 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1582 { "rx_undersize", RMON_R_UNDERSIZE },
1583 { "rx_oversize", RMON_R_OVERSIZE },
1584 { "rx_fragment", RMON_R_FRAG },
1585 { "rx_jabber", RMON_R_JAB },
1586 { "rx_64byte", RMON_R_P64 },
1587 { "rx_65to127byte", RMON_R_P65TO127 },
1588 { "rx_128to255byte", RMON_R_P128TO255 },
1589 { "rx_256to511byte", RMON_R_P256TO511 },
1590 { "rx_512to1023byte", RMON_R_P512TO1023 },
1591 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1592 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1593 { "rx_octets", RMON_R_OCTETS },
1596 { "IEEE_rx_drop", IEEE_R_DROP },
1597 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1598 { "IEEE_rx_crc", IEEE_R_CRC },
1599 { "IEEE_rx_align", IEEE_R_ALIGN },
1600 { "IEEE_rx_macerr", IEEE_R_MACERR },
1601 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1602 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1605 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1606 struct ethtool_stats *stats, u64 *data)
1608 struct fec_enet_private *fep = netdev_priv(dev);
1611 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1612 data[i] = readl(fep->hwp + fec_stats[i].offset);
1615 static void fec_enet_get_strings(struct net_device *netdev,
1616 u32 stringset, u8 *data)
1619 switch (stringset) {
1621 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1622 memcpy(data + i * ETH_GSTRING_LEN,
1623 fec_stats[i].name, ETH_GSTRING_LEN);
1628 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1632 return ARRAY_SIZE(fec_stats);
1637 #endif /* !defined(CONFIG_M5272) */
1639 static int fec_enet_nway_reset(struct net_device *dev)
1641 struct fec_enet_private *fep = netdev_priv(dev);
1642 struct phy_device *phydev = fep->phy_dev;
1647 return genphy_restart_aneg(phydev);
1650 static const struct ethtool_ops fec_enet_ethtool_ops = {
1651 #if !defined(CONFIG_M5272)
1652 .get_pauseparam = fec_enet_get_pauseparam,
1653 .set_pauseparam = fec_enet_set_pauseparam,
1655 .get_settings = fec_enet_get_settings,
1656 .set_settings = fec_enet_set_settings,
1657 .get_drvinfo = fec_enet_get_drvinfo,
1658 .get_link = ethtool_op_get_link,
1659 .get_ts_info = fec_enet_get_ts_info,
1660 .nway_reset = fec_enet_nway_reset,
1661 #ifndef CONFIG_M5272
1662 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1663 .get_strings = fec_enet_get_strings,
1664 .get_sset_count = fec_enet_get_sset_count,
1668 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1670 struct fec_enet_private *fep = netdev_priv(ndev);
1671 struct phy_device *phydev = fep->phy_dev;
1673 if (!netif_running(ndev))
1679 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1680 return fec_ptp_ioctl(ndev, rq, cmd);
1682 return phy_mii_ioctl(phydev, rq, cmd);
1685 static void fec_enet_free_buffers(struct net_device *ndev)
1687 struct fec_enet_private *fep = netdev_priv(ndev);
1689 struct sk_buff *skb;
1690 struct bufdesc *bdp;
1692 bdp = fep->rx_bd_base;
1693 for (i = 0; i < fep->rx_ring_size; i++) {
1694 skb = fep->rx_skbuff[i];
1696 if (bdp->cbd_bufaddr)
1697 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1698 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1701 bdp = fec_enet_get_nextdesc(bdp, fep);
1704 bdp = fep->tx_bd_base;
1705 for (i = 0; i < fep->tx_ring_size; i++)
1706 kfree(fep->tx_bounce[i]);
1709 static int fec_enet_alloc_buffers(struct net_device *ndev)
1711 struct fec_enet_private *fep = netdev_priv(ndev);
1713 struct sk_buff *skb;
1714 struct bufdesc *bdp;
1716 bdp = fep->rx_bd_base;
1717 for (i = 0; i < fep->rx_ring_size; i++) {
1718 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1720 fec_enet_free_buffers(ndev);
1723 fep->rx_skbuff[i] = skb;
1725 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1726 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1727 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr))
1729 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1731 if (fep->bufdesc_ex) {
1732 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1733 ebdp->cbd_esc = BD_ENET_RX_INT;
1736 bdp = fec_enet_get_nextdesc(bdp, fep);
1739 /* Set the last buffer to wrap. */
1740 bdp = fec_enet_get_prevdesc(bdp, fep);
1741 bdp->cbd_sc |= BD_SC_WRAP;
1743 bdp = fep->tx_bd_base;
1744 for (i = 0; i < fep->tx_ring_size; i++) {
1745 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1748 bdp->cbd_bufaddr = 0;
1750 if (fep->bufdesc_ex) {
1751 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1752 ebdp->cbd_esc = BD_ENET_TX_INT;
1755 bdp = fec_enet_get_nextdesc(bdp, fep);
1758 /* Set the last buffer to wrap. */
1759 bdp = fec_enet_get_prevdesc(bdp, fep);
1760 bdp->cbd_sc |= BD_SC_WRAP;
1766 bdp = fec_enet_get_prevdesc(bdp, fep);
1767 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1768 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1775 fec_enet_open(struct net_device *ndev)
1777 struct fec_enet_private *fep = netdev_priv(ndev);
1780 napi_enable(&fep->napi);
1782 /* I should reset the ring buffers here, but I don't yet know
1783 * a simple way to do that.
1786 ret = fec_enet_alloc_buffers(ndev);
1790 /* Probe and connect to PHY when open the interface */
1791 ret = fec_enet_mii_probe(ndev);
1793 fec_enet_free_buffers(ndev);
1796 phy_start(fep->phy_dev);
1797 netif_start_queue(ndev);
1803 fec_enet_close(struct net_device *ndev)
1805 struct fec_enet_private *fep = netdev_priv(ndev);
1807 /* Don't know what to do yet. */
1808 napi_disable(&fep->napi);
1810 netif_stop_queue(ndev);
1814 phy_stop(fep->phy_dev);
1815 phy_disconnect(fep->phy_dev);
1818 fec_enet_free_buffers(ndev);
1823 /* Set or clear the multicast filter for this adaptor.
1824 * Skeleton taken from sunlance driver.
1825 * The CPM Ethernet implementation allows Multicast as well as individual
1826 * MAC address filtering. Some of the drivers check to make sure it is
1827 * a group multicast address, and discard those that are not. I guess I
1828 * will do the same for now, but just remove the test if you want
1829 * individual filtering as well (do the upper net layers want or support
1830 * this kind of feature?).
1833 #define HASH_BITS 6 /* #bits in hash */
1834 #define CRC32_POLY 0xEDB88320
1836 static void set_multicast_list(struct net_device *ndev)
1838 struct fec_enet_private *fep = netdev_priv(ndev);
1839 struct netdev_hw_addr *ha;
1840 unsigned int i, bit, data, crc, tmp;
1843 if (ndev->flags & IFF_PROMISC) {
1844 tmp = readl(fep->hwp + FEC_R_CNTRL);
1846 writel(tmp, fep->hwp + FEC_R_CNTRL);
1850 tmp = readl(fep->hwp + FEC_R_CNTRL);
1852 writel(tmp, fep->hwp + FEC_R_CNTRL);
1854 if (ndev->flags & IFF_ALLMULTI) {
1855 /* Catch all multicast addresses, so set the
1858 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1859 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1864 /* Clear filter and add the addresses in hash register
1866 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1867 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1869 netdev_for_each_mc_addr(ha, ndev) {
1870 /* calculate crc32 value of mac address */
1873 for (i = 0; i < ndev->addr_len; i++) {
1875 for (bit = 0; bit < 8; bit++, data >>= 1) {
1877 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1881 /* only upper 6 bits (HASH_BITS) are used
1882 * which point to specific bit in he hash registers
1884 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1887 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1888 tmp |= 1 << (hash - 32);
1889 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1891 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1893 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1898 /* Set a MAC change in hardware. */
1900 fec_set_mac_address(struct net_device *ndev, void *p)
1902 struct fec_enet_private *fep = netdev_priv(ndev);
1903 struct sockaddr *addr = p;
1905 if (!is_valid_ether_addr(addr->sa_data))
1906 return -EADDRNOTAVAIL;
1908 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1910 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1911 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1912 fep->hwp + FEC_ADDR_LOW);
1913 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1914 fep->hwp + FEC_ADDR_HIGH);
1918 #ifdef CONFIG_NET_POLL_CONTROLLER
1920 * fec_poll_controller - FEC Poll controller function
1921 * @dev: The FEC network adapter
1923 * Polled functionality used by netconsole and others in non interrupt mode
1926 static void fec_poll_controller(struct net_device *dev)
1929 struct fec_enet_private *fep = netdev_priv(dev);
1931 for (i = 0; i < FEC_IRQ_NUM; i++) {
1932 if (fep->irq[i] > 0) {
1933 disable_irq(fep->irq[i]);
1934 fec_enet_interrupt(fep->irq[i], dev);
1935 enable_irq(fep->irq[i]);
1941 static int fec_set_features(struct net_device *netdev,
1942 netdev_features_t features)
1944 struct fec_enet_private *fep = netdev_priv(netdev);
1945 netdev_features_t changed = features ^ netdev->features;
1947 netdev->features = features;
1949 /* Receive checksum has been changed */
1950 if (changed & NETIF_F_RXCSUM) {
1951 if (features & NETIF_F_RXCSUM)
1952 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1954 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1956 if (netif_running(netdev)) {
1958 fec_restart(netdev, fep->phy_dev->duplex);
1959 netif_wake_queue(netdev);
1961 fec_restart(netdev, fep->phy_dev->duplex);
1968 static const struct net_device_ops fec_netdev_ops = {
1969 .ndo_open = fec_enet_open,
1970 .ndo_stop = fec_enet_close,
1971 .ndo_start_xmit = fec_enet_start_xmit,
1972 .ndo_set_rx_mode = set_multicast_list,
1973 .ndo_change_mtu = eth_change_mtu,
1974 .ndo_validate_addr = eth_validate_addr,
1975 .ndo_tx_timeout = fec_timeout,
1976 .ndo_set_mac_address = fec_set_mac_address,
1977 .ndo_do_ioctl = fec_enet_ioctl,
1978 #ifdef CONFIG_NET_POLL_CONTROLLER
1979 .ndo_poll_controller = fec_poll_controller,
1981 .ndo_set_features = fec_set_features,
1985 * XXX: We need to clean up on failure exits here.
1988 static int fec_enet_init(struct net_device *ndev)
1990 struct fec_enet_private *fep = netdev_priv(ndev);
1991 const struct platform_device_id *id_entry =
1992 platform_get_device_id(fep->pdev);
1993 struct bufdesc *cbd_base;
1995 /* Allocate memory for buffer descriptors. */
1996 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
2001 memset(cbd_base, 0, PAGE_SIZE);
2005 /* Get the Ethernet address */
2008 /* init the tx & rx ring size */
2009 fep->tx_ring_size = TX_RING_SIZE;
2010 fep->rx_ring_size = RX_RING_SIZE;
2012 /* Set receive and transmit descriptor base. */
2013 fep->rx_bd_base = cbd_base;
2014 if (fep->bufdesc_ex)
2015 fep->tx_bd_base = (struct bufdesc *)
2016 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2018 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2020 /* The FEC Ethernet specific entries in the device structure */
2021 ndev->watchdog_timeo = TX_TIMEOUT;
2022 ndev->netdev_ops = &fec_netdev_ops;
2023 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2025 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2026 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2028 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
2029 /* enable hw VLAN support */
2030 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2031 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2034 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2035 /* enable hw accelerator */
2036 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2038 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2040 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2043 fec_restart(ndev, 0);
2049 static void fec_reset_phy(struct platform_device *pdev)
2053 struct device_node *np = pdev->dev.of_node;
2058 of_property_read_u32(np, "phy-reset-duration", &msec);
2059 /* A sane reset duration should not be longer than 1s */
2063 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2064 if (!gpio_is_valid(phy_reset))
2067 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2068 GPIOF_OUT_INIT_LOW, "phy-reset");
2070 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2074 gpio_set_value(phy_reset, 1);
2076 #else /* CONFIG_OF */
2077 static void fec_reset_phy(struct platform_device *pdev)
2080 * In case of platform probe, the reset has been done
2084 #endif /* CONFIG_OF */
2087 fec_probe(struct platform_device *pdev)
2089 struct fec_enet_private *fep;
2090 struct fec_platform_data *pdata;
2091 struct net_device *ndev;
2092 int i, irq, ret = 0;
2094 const struct of_device_id *of_id;
2097 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2099 pdev->id_entry = of_id->data;
2101 /* Init network device */
2102 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2106 SET_NETDEV_DEV(ndev, &pdev->dev);
2108 /* setup board info structure */
2109 fep = netdev_priv(ndev);
2111 #if !defined(CONFIG_M5272)
2112 /* default enable pause frame auto negotiation */
2113 if (pdev->id_entry &&
2114 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2115 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2118 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2119 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2120 if (IS_ERR(fep->hwp)) {
2121 ret = PTR_ERR(fep->hwp);
2122 goto failed_ioremap;
2126 fep->dev_id = dev_id++;
2128 fep->bufdesc_ex = 0;
2130 platform_set_drvdata(pdev, ndev);
2132 ret = of_get_phy_mode(pdev->dev.of_node);
2134 pdata = dev_get_platdata(&pdev->dev);
2136 fep->phy_interface = pdata->phy;
2138 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2140 fep->phy_interface = ret;
2143 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2144 if (IS_ERR(fep->clk_ipg)) {
2145 ret = PTR_ERR(fep->clk_ipg);
2149 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2150 if (IS_ERR(fep->clk_ahb)) {
2151 ret = PTR_ERR(fep->clk_ahb);
2155 /* enet_out is optional, depends on board */
2156 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2157 if (IS_ERR(fep->clk_enet_out))
2158 fep->clk_enet_out = NULL;
2160 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2162 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2163 if (IS_ERR(fep->clk_ptp)) {
2164 fep->clk_ptp = NULL;
2165 fep->bufdesc_ex = 0;
2168 ret = clk_prepare_enable(fep->clk_ahb);
2172 ret = clk_prepare_enable(fep->clk_ipg);
2174 goto failed_clk_ipg;
2176 if (fep->clk_enet_out) {
2177 ret = clk_prepare_enable(fep->clk_enet_out);
2179 goto failed_clk_enet_out;
2183 ret = clk_prepare_enable(fep->clk_ptp);
2185 goto failed_clk_ptp;
2188 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2189 if (!IS_ERR(fep->reg_phy)) {
2190 ret = regulator_enable(fep->reg_phy);
2193 "Failed to enable phy regulator: %d\n", ret);
2194 goto failed_regulator;
2197 fep->reg_phy = NULL;
2200 fec_reset_phy(pdev);
2202 if (fep->bufdesc_ex)
2205 ret = fec_enet_init(ndev);
2209 for (i = 0; i < FEC_IRQ_NUM; i++) {
2210 irq = platform_get_irq(pdev, i);
2217 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2218 0, pdev->name, ndev);
2223 ret = fec_enet_mii_init(pdev);
2225 goto failed_mii_init;
2227 /* Carrier starts down, phylib will bring it up */
2228 netif_carrier_off(ndev);
2230 ret = register_netdev(ndev);
2232 goto failed_register;
2234 if (fep->bufdesc_ex && fep->ptp_clock)
2235 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2237 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2241 fec_enet_mii_remove(fep);
2246 regulator_disable(fep->reg_phy);
2249 clk_disable_unprepare(fep->clk_ptp);
2251 if (fep->clk_enet_out)
2252 clk_disable_unprepare(fep->clk_enet_out);
2253 failed_clk_enet_out:
2254 clk_disable_unprepare(fep->clk_ipg);
2256 clk_disable_unprepare(fep->clk_ahb);
2265 fec_drv_remove(struct platform_device *pdev)
2267 struct net_device *ndev = platform_get_drvdata(pdev);
2268 struct fec_enet_private *fep = netdev_priv(ndev);
2270 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2271 unregister_netdev(ndev);
2272 fec_enet_mii_remove(fep);
2273 del_timer_sync(&fep->time_keep);
2275 regulator_disable(fep->reg_phy);
2277 clk_disable_unprepare(fep->clk_ptp);
2279 ptp_clock_unregister(fep->ptp_clock);
2280 if (fep->clk_enet_out)
2281 clk_disable_unprepare(fep->clk_enet_out);
2282 clk_disable_unprepare(fep->clk_ipg);
2283 clk_disable_unprepare(fep->clk_ahb);
2289 #ifdef CONFIG_PM_SLEEP
2291 fec_suspend(struct device *dev)
2293 struct net_device *ndev = dev_get_drvdata(dev);
2294 struct fec_enet_private *fep = netdev_priv(ndev);
2296 if (netif_running(ndev)) {
2298 netif_device_detach(ndev);
2301 clk_disable_unprepare(fep->clk_ptp);
2302 if (fep->clk_enet_out)
2303 clk_disable_unprepare(fep->clk_enet_out);
2304 clk_disable_unprepare(fep->clk_ipg);
2305 clk_disable_unprepare(fep->clk_ahb);
2308 regulator_disable(fep->reg_phy);
2314 fec_resume(struct device *dev)
2316 struct net_device *ndev = dev_get_drvdata(dev);
2317 struct fec_enet_private *fep = netdev_priv(ndev);
2321 ret = regulator_enable(fep->reg_phy);
2326 ret = clk_prepare_enable(fep->clk_ahb);
2328 goto failed_clk_ahb;
2330 ret = clk_prepare_enable(fep->clk_ipg);
2332 goto failed_clk_ipg;
2334 if (fep->clk_enet_out) {
2335 ret = clk_prepare_enable(fep->clk_enet_out);
2337 goto failed_clk_enet_out;
2341 ret = clk_prepare_enable(fep->clk_ptp);
2343 goto failed_clk_ptp;
2346 if (netif_running(ndev)) {
2347 fec_restart(ndev, fep->full_duplex);
2348 netif_device_attach(ndev);
2354 if (fep->clk_enet_out)
2355 clk_disable_unprepare(fep->clk_enet_out);
2356 failed_clk_enet_out:
2357 clk_disable_unprepare(fep->clk_ipg);
2359 clk_disable_unprepare(fep->clk_ahb);
2362 regulator_disable(fep->reg_phy);
2365 #endif /* CONFIG_PM_SLEEP */
2367 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2369 static struct platform_driver fec_driver = {
2371 .name = DRIVER_NAME,
2372 .owner = THIS_MODULE,
2374 .of_match_table = fec_dt_ids,
2376 .id_table = fec_devtype,
2378 .remove = fec_drv_remove,
2381 module_platform_driver(fec_driver);
2383 MODULE_ALIAS("platform:"DRIVER_NAME);
2384 MODULE_LICENSE("GPL");