1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include "stmmac_ptp.h"
50 #include <linux/reset.h>
51 #include <linux/of_mdio.h>
52 #include "dwmac1000.h"
54 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
55 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
57 /* Module parameters */
59 static int watchdog = TX_TIMEO;
60 module_param(watchdog, int, S_IRUGO | S_IWUSR);
61 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
63 static int debug = -1;
64 module_param(debug, int, S_IRUGO | S_IWUSR);
65 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
67 static int phyaddr = -1;
68 module_param(phyaddr, int, S_IRUGO);
69 MODULE_PARM_DESC(phyaddr, "Physical device address");
71 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
72 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
74 static int flow_ctrl = FLOW_OFF;
75 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
76 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
78 static int pause = PAUSE_TIME;
79 module_param(pause, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
83 static int tc = TC_DEFAULT;
84 module_param(tc, int, S_IRUGO | S_IWUSR);
85 MODULE_PARM_DESC(tc, "DMA threshold control value");
87 #define DEFAULT_BUFSIZE 1536
88 static int buf_sz = DEFAULT_BUFSIZE;
89 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
92 #define STMMAC_RX_COPYBREAK 256
94 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
95 NETIF_MSG_LINK | NETIF_MSG_IFUP |
96 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
98 #define STMMAC_DEFAULT_LPI_TIMER 1000
99 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
100 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
101 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
104 /* By default the driver will use the ring mode to manage tx and rx descriptors,
105 * but allow user to force to use the chain instead of the ring
107 static unsigned int chain_mode;
108 module_param(chain_mode, int, S_IRUGO);
109 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
111 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
113 #ifdef CONFIG_DEBUG_FS
114 static int stmmac_init_fs(struct net_device *dev);
115 static void stmmac_exit_fs(struct net_device *dev);
118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
121 * stmmac_verify_args - verify the driver parameters.
122 * Description: it checks the driver parameters and set a default in case of
125 static void stmmac_verify_args(void)
127 if (unlikely(watchdog < 0))
129 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
130 buf_sz = DEFAULT_BUFSIZE;
131 if (unlikely(flow_ctrl > 1))
132 flow_ctrl = FLOW_AUTO;
133 else if (likely(flow_ctrl < 0))
134 flow_ctrl = FLOW_OFF;
135 if (unlikely((pause < 0) || (pause > 0xffff)))
138 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
142 * stmmac_disable_all_queues - Disable all queues
143 * @priv: driver private structure
145 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
147 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
150 for (queue = 0; queue < rx_queues_cnt; queue++) {
151 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
153 napi_disable(&rx_q->napi);
158 * stmmac_enable_all_queues - Enable all queues
159 * @priv: driver private structure
161 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
163 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
166 for (queue = 0; queue < rx_queues_cnt; queue++) {
167 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
169 napi_enable(&rx_q->napi);
174 * stmmac_stop_all_queues - Stop all queues
175 * @priv: driver private structure
177 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
179 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
182 for (queue = 0; queue < tx_queues_cnt; queue++)
183 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
187 * stmmac_start_all_queues - Start all queues
188 * @priv: driver private structure
190 static void stmmac_start_all_queues(struct stmmac_priv *priv)
192 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
195 for (queue = 0; queue < tx_queues_cnt; queue++)
196 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
200 * stmmac_clk_csr_set - dynamically set the MDC clock
201 * @priv: driver private structure
202 * Description: this is to dynamically set the MDC clock according to the csr
205 * If a specific clk_csr value is passed from the platform
206 * this means that the CSR Clock Range selection cannot be
207 * changed at run-time and it is fixed (as reported in the driver
208 * documentation). Viceversa the driver will try to set the MDC
209 * clock dynamically according to the actual clock input.
211 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
215 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
217 /* Platform provided default clk_csr would be assumed valid
218 * for all other cases except for the below mentioned ones.
219 * For values higher than the IEEE 802.3 specified frequency
220 * we can not estimate the proper divider as it is not known
221 * the frequency of clk_csr_i. So we do not change the default
224 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
225 if (clk_rate < CSR_F_35M)
226 priv->clk_csr = STMMAC_CSR_20_35M;
227 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
228 priv->clk_csr = STMMAC_CSR_35_60M;
229 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
230 priv->clk_csr = STMMAC_CSR_60_100M;
231 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
232 priv->clk_csr = STMMAC_CSR_100_150M;
233 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
234 priv->clk_csr = STMMAC_CSR_150_250M;
235 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
236 priv->clk_csr = STMMAC_CSR_250_300M;
240 static void print_pkt(unsigned char *buf, int len)
242 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
243 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
246 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
248 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
251 if (tx_q->dirty_tx > tx_q->cur_tx)
252 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
254 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
260 * stmmac_rx_dirty - Get RX queue dirty
261 * @priv: driver private structure
262 * @queue: RX queue index
264 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
266 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
269 if (rx_q->dirty_rx <= rx_q->cur_rx)
270 dirty = rx_q->cur_rx - rx_q->dirty_rx;
272 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
278 * stmmac_hw_fix_mac_speed - callback for speed selection
279 * @priv: driver private structure
280 * Description: on some platforms (e.g. ST), some HW system configuration
281 * registers have to be set according to the link speed negotiated.
283 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
285 struct net_device *ndev = priv->dev;
286 struct phy_device *phydev = ndev->phydev;
288 if (likely(priv->plat->fix_mac_speed))
289 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
293 * stmmac_enable_eee_mode - check and enter in LPI mode
294 * @priv: driver private structure
295 * Description: this function is to verify and enter in LPI mode in case of
298 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
300 u32 tx_cnt = priv->plat->tx_queues_to_use;
303 /* check if all TX queues have the work finished */
304 for (queue = 0; queue < tx_cnt; queue++) {
305 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
307 if (tx_q->dirty_tx != tx_q->cur_tx)
308 return; /* still unfinished work */
311 /* Check and enter in LPI mode */
312 if (!priv->tx_path_in_lpi_mode)
313 priv->hw->mac->set_eee_mode(priv->hw,
314 priv->plat->en_tx_lpi_clockgating);
318 * stmmac_disable_eee_mode - disable and exit from LPI mode
319 * @priv: driver private structure
320 * Description: this function is to exit and disable EEE in case of
321 * LPI state is true. This is called by the xmit.
323 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
325 priv->hw->mac->reset_eee_mode(priv->hw);
326 del_timer_sync(&priv->eee_ctrl_timer);
327 priv->tx_path_in_lpi_mode = false;
331 * stmmac_eee_ctrl_timer - EEE TX SW timer.
334 * if there is no data transfer and if we are not in LPI state,
335 * then MAC Transmitter can be moved to LPI state.
337 static void stmmac_eee_ctrl_timer(unsigned long arg)
339 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
341 stmmac_enable_eee_mode(priv);
342 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
346 * stmmac_eee_init - init EEE
347 * @priv: driver private structure
349 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
350 * can also manage EEE, this function enable the LPI state and start related
353 bool stmmac_eee_init(struct stmmac_priv *priv)
355 struct net_device *ndev = priv->dev;
359 /* Using PCS we cannot dial with the phy registers at this stage
360 * so we do not support extra feature like EEE.
362 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
363 (priv->hw->pcs == STMMAC_PCS_TBI) ||
364 (priv->hw->pcs == STMMAC_PCS_RTBI))
367 /* MAC core supports the EEE feature. */
368 if (priv->dma_cap.eee) {
369 int tx_lpi_timer = priv->tx_lpi_timer;
371 /* Check if the PHY supports EEE */
372 if (phy_init_eee(ndev->phydev, 1)) {
373 /* To manage at run-time if the EEE cannot be supported
374 * anymore (for example because the lp caps have been
376 * In that case the driver disable own timers.
378 spin_lock_irqsave(&priv->lock, flags);
379 if (priv->eee_active) {
380 netdev_dbg(priv->dev, "disable EEE\n");
381 del_timer_sync(&priv->eee_ctrl_timer);
382 priv->hw->mac->set_eee_timer(priv->hw, 0,
385 priv->eee_active = 0;
386 spin_unlock_irqrestore(&priv->lock, flags);
389 /* Activate the EEE and start timers */
390 spin_lock_irqsave(&priv->lock, flags);
391 if (!priv->eee_active) {
392 priv->eee_active = 1;
393 setup_timer(&priv->eee_ctrl_timer,
394 stmmac_eee_ctrl_timer,
395 (unsigned long)priv);
396 mod_timer(&priv->eee_ctrl_timer,
397 STMMAC_LPI_T(eee_timer));
399 priv->hw->mac->set_eee_timer(priv->hw,
400 STMMAC_DEFAULT_LIT_LS,
403 /* Set HW EEE according to the speed */
404 priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link);
407 spin_unlock_irqrestore(&priv->lock, flags);
409 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
415 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
416 * @priv: driver private structure
417 * @p : descriptor pointer
418 * @skb : the socket buffer
420 * This function will read timestamp from the descriptor & pass it to stack.
421 * and also perform some sanity checks.
423 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
424 struct dma_desc *p, struct sk_buff *skb)
426 struct skb_shared_hwtstamps shhwtstamp;
429 if (!priv->hwts_tx_en)
432 /* exit if skb doesn't support hw tstamp */
433 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
436 /* check tx tstamp status */
437 if (priv->hw->desc->get_tx_timestamp_status(p)) {
438 /* get the valid tstamp */
439 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
441 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
442 shhwtstamp.hwtstamp = ns_to_ktime(ns);
444 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
445 /* pass tstamp to stack */
446 skb_tstamp_tx(skb, &shhwtstamp);
452 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
453 * @priv: driver private structure
454 * @p : descriptor pointer
455 * @np : next descriptor pointer
456 * @skb : the socket buffer
458 * This function will read received packet's timestamp from the descriptor
459 * and pass it to stack. It also perform some sanity checks.
461 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
462 struct dma_desc *np, struct sk_buff *skb)
464 struct skb_shared_hwtstamps *shhwtstamp = NULL;
467 if (!priv->hwts_rx_en)
470 /* Check if timestamp is available */
471 if (priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
472 /* For GMAC4, the valid timestamp is from CTX next desc. */
473 if (priv->plat->has_gmac4)
474 ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
476 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
478 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
479 shhwtstamp = skb_hwtstamps(skb);
480 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
481 shhwtstamp->hwtstamp = ns_to_ktime(ns);
483 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
488 * stmmac_hwtstamp_ioctl - control hardware timestamping.
489 * @dev: device pointer.
490 * @ifr: An IOCTL specific structure, that can contain a pointer to
491 * a proprietary structure used to pass information to the driver.
493 * This function configures the MAC to enable/disable both outgoing(TX)
494 * and incoming(RX) packets time stamping based on user input.
496 * 0 on success and an appropriate -ve integer on failure.
498 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
500 struct stmmac_priv *priv = netdev_priv(dev);
501 struct hwtstamp_config config;
502 struct timespec64 now;
506 u32 ptp_over_ipv4_udp = 0;
507 u32 ptp_over_ipv6_udp = 0;
508 u32 ptp_over_ethernet = 0;
509 u32 snap_type_sel = 0;
510 u32 ts_master_en = 0;
515 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
516 netdev_alert(priv->dev, "No support for HW time stamping\n");
517 priv->hwts_tx_en = 0;
518 priv->hwts_rx_en = 0;
523 if (copy_from_user(&config, ifr->ifr_data,
524 sizeof(struct hwtstamp_config)))
527 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
528 __func__, config.flags, config.tx_type, config.rx_filter);
530 /* reserved for future extensions */
534 if (config.tx_type != HWTSTAMP_TX_OFF &&
535 config.tx_type != HWTSTAMP_TX_ON)
539 switch (config.rx_filter) {
540 case HWTSTAMP_FILTER_NONE:
541 /* time stamp no incoming packet at all */
542 config.rx_filter = HWTSTAMP_FILTER_NONE;
545 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
546 /* PTP v1, UDP, any kind of event packet */
547 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
548 /* take time stamp for all event messages */
549 if (priv->plat->has_gmac4)
550 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
552 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
554 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
555 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
558 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
559 /* PTP v1, UDP, Sync packet */
560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
561 /* take time stamp for SYNC messages only */
562 ts_event_en = PTP_TCR_TSEVNTENA;
564 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
565 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
568 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
569 /* PTP v1, UDP, Delay_req packet */
570 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
571 /* take time stamp for Delay_Req messages only */
572 ts_master_en = PTP_TCR_TSMSTRENA;
573 ts_event_en = PTP_TCR_TSEVNTENA;
575 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
576 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
579 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
580 /* PTP v2, UDP, any kind of event packet */
581 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
582 ptp_v2 = PTP_TCR_TSVER2ENA;
583 /* take time stamp for all event messages */
584 if (priv->plat->has_gmac4)
585 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
587 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
593 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
594 /* PTP v2, UDP, Sync packet */
595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
596 ptp_v2 = PTP_TCR_TSVER2ENA;
597 /* take time stamp for SYNC messages only */
598 ts_event_en = PTP_TCR_TSEVNTENA;
600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
604 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
605 /* PTP v2, UDP, Delay_req packet */
606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
607 ptp_v2 = PTP_TCR_TSVER2ENA;
608 /* take time stamp for Delay_Req messages only */
609 ts_master_en = PTP_TCR_TSMSTRENA;
610 ts_event_en = PTP_TCR_TSEVNTENA;
612 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
613 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
616 case HWTSTAMP_FILTER_PTP_V2_EVENT:
617 /* PTP v2/802.AS1 any layer, any kind of event packet */
618 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
619 ptp_v2 = PTP_TCR_TSVER2ENA;
620 /* take time stamp for all event messages */
621 if (priv->plat->has_gmac4)
622 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
624 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
626 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
627 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
628 ptp_over_ethernet = PTP_TCR_TSIPENA;
631 case HWTSTAMP_FILTER_PTP_V2_SYNC:
632 /* PTP v2/802.AS1, any layer, Sync packet */
633 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
634 ptp_v2 = PTP_TCR_TSVER2ENA;
635 /* take time stamp for SYNC messages only */
636 ts_event_en = PTP_TCR_TSEVNTENA;
638 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
639 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
640 ptp_over_ethernet = PTP_TCR_TSIPENA;
643 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
644 /* PTP v2/802.AS1, any layer, Delay_req packet */
645 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
646 ptp_v2 = PTP_TCR_TSVER2ENA;
647 /* take time stamp for Delay_Req messages only */
648 ts_master_en = PTP_TCR_TSMSTRENA;
649 ts_event_en = PTP_TCR_TSEVNTENA;
651 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
652 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
653 ptp_over_ethernet = PTP_TCR_TSIPENA;
656 case HWTSTAMP_FILTER_ALL:
657 /* time stamp any incoming packet */
658 config.rx_filter = HWTSTAMP_FILTER_ALL;
659 tstamp_all = PTP_TCR_TSENALL;
666 switch (config.rx_filter) {
667 case HWTSTAMP_FILTER_NONE:
668 config.rx_filter = HWTSTAMP_FILTER_NONE;
671 /* PTP v1, UDP, any kind of event packet */
672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
676 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
677 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
679 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
680 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
682 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
683 tstamp_all | ptp_v2 | ptp_over_ethernet |
684 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
685 ts_master_en | snap_type_sel);
686 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
688 /* program Sub Second Increment reg */
689 sec_inc = priv->hw->ptp->config_sub_second_increment(
690 priv->ptpaddr, priv->plat->clk_ptp_rate,
691 priv->plat->has_gmac4);
692 temp = div_u64(1000000000ULL, sec_inc);
694 /* calculate default added value:
696 * addend = (2^32)/freq_div_ratio;
697 * where, freq_div_ratio = 1e9ns/sec_inc
699 temp = (u64)(temp << 32);
700 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
701 priv->hw->ptp->config_addend(priv->ptpaddr,
702 priv->default_addend);
704 /* initialize system time */
705 ktime_get_real_ts64(&now);
707 /* lower 32 bits of tv_sec are safe until y2106 */
708 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
712 return copy_to_user(ifr->ifr_data, &config,
713 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
717 * stmmac_init_ptp - init PTP
718 * @priv: driver private structure
719 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
720 * This is done by looking at the HW cap. register.
721 * This function also registers the ptp driver.
723 static int stmmac_init_ptp(struct stmmac_priv *priv)
725 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
729 /* Check if adv_ts can be enabled for dwmac 4.x core */
730 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
732 /* Dwmac 3.x core with extend_desc can support adv_ts */
733 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
736 if (priv->dma_cap.time_stamp)
737 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
740 netdev_info(priv->dev,
741 "IEEE 1588-2008 Advanced Timestamp supported\n");
743 priv->hw->ptp = &stmmac_ptp;
744 priv->hwts_tx_en = 0;
745 priv->hwts_rx_en = 0;
747 stmmac_ptp_register(priv);
752 static void stmmac_release_ptp(struct stmmac_priv *priv)
754 if (priv->plat->clk_ptp_ref)
755 clk_disable_unprepare(priv->plat->clk_ptp_ref);
756 stmmac_ptp_unregister(priv);
760 * stmmac_mac_flow_ctrl - Configure flow control in all queues
761 * @priv: driver private structure
762 * Description: It is used for configuring the flow control in all queues
764 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
766 u32 tx_cnt = priv->plat->tx_queues_to_use;
768 priv->hw->mac->flow_ctrl(priv->hw, duplex, priv->flow_ctrl,
769 priv->pause, tx_cnt);
773 * stmmac_adjust_link - adjusts the link parameters
774 * @dev: net device structure
775 * Description: this is the helper called by the physical abstraction layer
776 * drivers to communicate the phy link status. According the speed and duplex
777 * this driver can invoke registered glue-logic as well.
778 * It also invoke the eee initialization because it could happen when switch
779 * on different networks (that are eee capable).
781 static void stmmac_adjust_link(struct net_device *dev)
783 struct stmmac_priv *priv = netdev_priv(dev);
784 struct phy_device *phydev = dev->phydev;
791 spin_lock_irqsave(&priv->lock, flags);
794 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
796 /* Now we make sure that we can be in full duplex mode.
797 * If not, we operate in half-duplex mode. */
798 if (phydev->duplex != priv->oldduplex) {
800 if (!(phydev->duplex))
801 ctrl &= ~priv->hw->link.duplex;
803 ctrl |= priv->hw->link.duplex;
804 priv->oldduplex = phydev->duplex;
806 /* Flow Control operation */
808 stmmac_mac_flow_ctrl(priv, phydev->duplex);
810 if (phydev->speed != priv->speed) {
812 switch (phydev->speed) {
814 if (priv->plat->has_gmac ||
815 priv->plat->has_gmac4)
816 ctrl &= ~priv->hw->link.port;
819 if (priv->plat->has_gmac ||
820 priv->plat->has_gmac4) {
821 ctrl |= priv->hw->link.port;
822 ctrl |= priv->hw->link.speed;
824 ctrl &= ~priv->hw->link.port;
828 if (priv->plat->has_gmac ||
829 priv->plat->has_gmac4) {
830 ctrl |= priv->hw->link.port;
831 ctrl &= ~(priv->hw->link.speed);
833 ctrl &= ~priv->hw->link.port;
837 netif_warn(priv, link, priv->dev,
838 "broken speed: %d\n", phydev->speed);
839 phydev->speed = SPEED_UNKNOWN;
842 if (phydev->speed != SPEED_UNKNOWN)
843 stmmac_hw_fix_mac_speed(priv);
844 priv->speed = phydev->speed;
847 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
849 if (!priv->oldlink) {
853 } else if (priv->oldlink) {
856 priv->speed = SPEED_UNKNOWN;
857 priv->oldduplex = DUPLEX_UNKNOWN;
860 if (new_state && netif_msg_link(priv))
861 phy_print_status(phydev);
863 spin_unlock_irqrestore(&priv->lock, flags);
865 if (phydev->is_pseudo_fixed_link)
866 /* Stop PHY layer to call the hook to adjust the link in case
867 * of a switch is attached to the stmmac driver.
869 phydev->irq = PHY_IGNORE_INTERRUPT;
871 /* At this stage, init the EEE if supported.
872 * Never called in case of fixed_link.
874 priv->eee_enabled = stmmac_eee_init(priv);
878 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
879 * @priv: driver private structure
880 * Description: this is to verify if the HW supports the PCS.
881 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
882 * configured for the TBI, RTBI, or SGMII PHY interface.
884 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
886 int interface = priv->plat->interface;
888 if (priv->dma_cap.pcs) {
889 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
890 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
891 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
892 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
893 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
894 priv->hw->pcs = STMMAC_PCS_RGMII;
895 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
896 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
897 priv->hw->pcs = STMMAC_PCS_SGMII;
903 * stmmac_init_phy - PHY initialization
904 * @dev: net device structure
905 * Description: it initializes the driver's PHY state, and attaches the PHY
910 static int stmmac_init_phy(struct net_device *dev)
912 struct stmmac_priv *priv = netdev_priv(dev);
913 struct phy_device *phydev;
914 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
915 char bus_id[MII_BUS_ID_SIZE];
916 int interface = priv->plat->interface;
917 int max_speed = priv->plat->max_speed;
919 priv->speed = SPEED_UNKNOWN;
920 priv->oldduplex = DUPLEX_UNKNOWN;
922 if (priv->plat->phy_node) {
923 phydev = of_phy_connect(dev, priv->plat->phy_node,
924 &stmmac_adjust_link, 0, interface);
926 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
929 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
930 priv->plat->phy_addr);
931 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
934 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
938 if (IS_ERR_OR_NULL(phydev)) {
939 netdev_err(priv->dev, "Could not attach to PHY\n");
943 return PTR_ERR(phydev);
946 /* Stop Advertising 1000BASE Capability if interface is not GMII */
947 if ((interface == PHY_INTERFACE_MODE_MII) ||
948 (interface == PHY_INTERFACE_MODE_RMII) ||
949 (max_speed < 1000 && max_speed > 0))
950 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
951 SUPPORTED_1000baseT_Full);
954 * Broken HW is sometimes missing the pull-up resistor on the
955 * MDIO line, which results in reads to non-existent devices returning
956 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
958 * Note: phydev->phy_id is the result of reading the UID PHY registers.
960 if (!priv->plat->phy_node && phydev->phy_id == 0) {
961 phy_disconnect(phydev);
965 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
966 * subsequent PHY polling, make sure we force a link transition if
967 * we have a UP/DOWN/UP transition
969 if (phydev->is_pseudo_fixed_link)
970 phydev->irq = PHY_POLL;
972 phy_attached_info(phydev);
976 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
978 u32 rx_cnt = priv->plat->rx_queues_to_use;
982 /* Display RX rings */
983 for (queue = 0; queue < rx_cnt; queue++) {
984 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
986 pr_info("\tRX Queue %u rings\n", queue);
988 if (priv->extend_desc)
989 head_rx = (void *)rx_q->dma_erx;
991 head_rx = (void *)rx_q->dma_rx;
993 /* Display RX ring */
994 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
998 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1000 u32 tx_cnt = priv->plat->tx_queues_to_use;
1004 /* Display TX rings */
1005 for (queue = 0; queue < tx_cnt; queue++) {
1006 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1008 pr_info("\tTX Queue %d rings\n", queue);
1010 if (priv->extend_desc)
1011 head_tx = (void *)tx_q->dma_etx;
1013 head_tx = (void *)tx_q->dma_tx;
1015 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
1019 static void stmmac_display_rings(struct stmmac_priv *priv)
1021 /* Display RX ring */
1022 stmmac_display_rx_rings(priv);
1024 /* Display TX ring */
1025 stmmac_display_tx_rings(priv);
1028 static int stmmac_set_bfsize(int mtu, int bufsize)
1032 if (mtu >= BUF_SIZE_4KiB)
1033 ret = BUF_SIZE_8KiB;
1034 else if (mtu >= BUF_SIZE_2KiB)
1035 ret = BUF_SIZE_4KiB;
1036 else if (mtu > DEFAULT_BUFSIZE)
1037 ret = BUF_SIZE_2KiB;
1039 ret = DEFAULT_BUFSIZE;
1045 * stmmac_clear_rx_descriptors - clear RX descriptors
1046 * @priv: driver private structure
1047 * @queue: RX queue index
1048 * Description: this function is called to clear the RX descriptors
1049 * in case of both basic and extended descriptors are used.
1051 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1053 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1056 /* Clear the RX descriptors */
1057 for (i = 0; i < DMA_RX_SIZE; i++)
1058 if (priv->extend_desc)
1059 priv->hw->desc->init_rx_desc(&rx_q->dma_erx[i].basic,
1060 priv->use_riwt, priv->mode,
1061 (i == DMA_RX_SIZE - 1));
1063 priv->hw->desc->init_rx_desc(&rx_q->dma_rx[i],
1064 priv->use_riwt, priv->mode,
1065 (i == DMA_RX_SIZE - 1));
1069 * stmmac_clear_tx_descriptors - clear tx descriptors
1070 * @priv: driver private structure
1071 * @queue: TX queue index.
1072 * Description: this function is called to clear the TX descriptors
1073 * in case of both basic and extended descriptors are used.
1075 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1077 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1080 /* Clear the TX descriptors */
1081 for (i = 0; i < DMA_TX_SIZE; i++)
1082 if (priv->extend_desc)
1083 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,
1085 (i == DMA_TX_SIZE - 1));
1087 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],
1089 (i == DMA_TX_SIZE - 1));
1093 * stmmac_clear_descriptors - clear descriptors
1094 * @priv: driver private structure
1095 * Description: this function is called to clear the TX and RX descriptors
1096 * in case of both basic and extended descriptors are used.
1098 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1100 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1101 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1104 /* Clear the RX descriptors */
1105 for (queue = 0; queue < rx_queue_cnt; queue++)
1106 stmmac_clear_rx_descriptors(priv, queue);
1108 /* Clear the TX descriptors */
1109 for (queue = 0; queue < tx_queue_cnt; queue++)
1110 stmmac_clear_tx_descriptors(priv, queue);
1114 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1115 * @priv: driver private structure
1116 * @p: descriptor pointer
1117 * @i: descriptor index
1119 * @queue: RX queue index
1120 * Description: this function is called to allocate a receive buffer, perform
1121 * the DMA mapping and init the descriptor.
1123 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1124 int i, gfp_t flags, u32 queue)
1126 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1127 struct sk_buff *skb;
1129 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1131 netdev_err(priv->dev,
1132 "%s: Rx init fails; skb is NULL\n", __func__);
1135 rx_q->rx_skbuff[i] = skb;
1136 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1139 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1140 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1141 dev_kfree_skb_any(skb);
1145 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1146 p->des0 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);
1148 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[i]);
1150 if ((priv->hw->mode->init_desc3) &&
1151 (priv->dma_buf_sz == BUF_SIZE_16KiB))
1152 priv->hw->mode->init_desc3(p);
1158 * stmmac_free_rx_buffer - free RX dma buffers
1159 * @priv: private structure
1160 * @queue: RX queue index
1163 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1165 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1167 if (rx_q->rx_skbuff[i]) {
1168 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1169 priv->dma_buf_sz, DMA_FROM_DEVICE);
1170 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1172 rx_q->rx_skbuff[i] = NULL;
1176 * stmmac_free_tx_buffer - free RX dma buffers
1177 * @priv: private structure
1178 * @queue: RX queue index
1181 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1183 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1185 if (tx_q->tx_skbuff_dma[i].buf) {
1186 if (tx_q->tx_skbuff_dma[i].map_as_page)
1187 dma_unmap_page(priv->device,
1188 tx_q->tx_skbuff_dma[i].buf,
1189 tx_q->tx_skbuff_dma[i].len,
1192 dma_unmap_single(priv->device,
1193 tx_q->tx_skbuff_dma[i].buf,
1194 tx_q->tx_skbuff_dma[i].len,
1198 if (tx_q->tx_skbuff[i]) {
1199 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1200 tx_q->tx_skbuff[i] = NULL;
1201 tx_q->tx_skbuff_dma[i].buf = 0;
1202 tx_q->tx_skbuff_dma[i].map_as_page = false;
1207 * init_dma_rx_desc_rings - init the RX descriptor rings
1208 * @dev: net device structure
1210 * Description: this function initializes the DMA RX descriptors
1211 * and allocates the socket buffers. It supports the chained and ring
1214 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1216 struct stmmac_priv *priv = netdev_priv(dev);
1217 u32 rx_count = priv->plat->rx_queues_to_use;
1218 unsigned int bfsize = 0;
1223 if (priv->hw->mode->set_16kib_bfsize)
1224 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1226 if (bfsize < BUF_SIZE_16KiB)
1227 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1229 priv->dma_buf_sz = bfsize;
1231 /* RX INITIALIZATION */
1232 netif_dbg(priv, probe, priv->dev,
1233 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1235 for (queue = 0; queue < rx_count; queue++) {
1236 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1238 netif_dbg(priv, probe, priv->dev,
1239 "(%s) dma_rx_phy=0x%08x\n", __func__,
1240 (u32)rx_q->dma_rx_phy);
1242 for (i = 0; i < DMA_RX_SIZE; i++) {
1245 if (priv->extend_desc)
1246 p = &((rx_q->dma_erx + i)->basic);
1248 p = rx_q->dma_rx + i;
1250 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1253 goto err_init_rx_buffers;
1255 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1256 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1257 (unsigned int)rx_q->rx_skbuff_dma[i]);
1261 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1263 stmmac_clear_rx_descriptors(priv, queue);
1265 /* Setup the chained descriptor addresses */
1266 if (priv->mode == STMMAC_CHAIN_MODE) {
1267 if (priv->extend_desc)
1268 priv->hw->mode->init(rx_q->dma_erx,
1272 priv->hw->mode->init(rx_q->dma_rx,
1282 err_init_rx_buffers:
1283 while (queue >= 0) {
1285 stmmac_free_rx_buffer(priv, queue, i);
1298 * init_dma_tx_desc_rings - init the TX descriptor rings
1299 * @dev: net device structure.
1300 * Description: this function initializes the DMA TX descriptors
1301 * and allocates the socket buffers. It supports the chained and ring
1304 static int init_dma_tx_desc_rings(struct net_device *dev)
1306 struct stmmac_priv *priv = netdev_priv(dev);
1307 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1311 for (queue = 0; queue < tx_queue_cnt; queue++) {
1312 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1314 netif_dbg(priv, probe, priv->dev,
1315 "(%s) dma_tx_phy=0x%08x\n", __func__,
1316 (u32)tx_q->dma_tx_phy);
1318 /* Setup the chained descriptor addresses */
1319 if (priv->mode == STMMAC_CHAIN_MODE) {
1320 if (priv->extend_desc)
1321 priv->hw->mode->init(tx_q->dma_etx,
1325 priv->hw->mode->init(tx_q->dma_tx,
1330 for (i = 0; i < DMA_TX_SIZE; i++) {
1332 if (priv->extend_desc)
1333 p = &((tx_q->dma_etx + i)->basic);
1335 p = tx_q->dma_tx + i;
1337 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1346 tx_q->tx_skbuff_dma[i].buf = 0;
1347 tx_q->tx_skbuff_dma[i].map_as_page = false;
1348 tx_q->tx_skbuff_dma[i].len = 0;
1349 tx_q->tx_skbuff_dma[i].last_segment = false;
1350 tx_q->tx_skbuff[i] = NULL;
1356 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1363 * init_dma_desc_rings - init the RX/TX descriptor rings
1364 * @dev: net device structure
1366 * Description: this function initializes the DMA RX/TX descriptors
1367 * and allocates the socket buffers. It supports the chained and ring
1370 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1372 struct stmmac_priv *priv = netdev_priv(dev);
1375 ret = init_dma_rx_desc_rings(dev, flags);
1379 ret = init_dma_tx_desc_rings(dev);
1381 stmmac_clear_descriptors(priv);
1383 if (netif_msg_hw(priv))
1384 stmmac_display_rings(priv);
1390 * dma_free_rx_skbufs - free RX dma buffers
1391 * @priv: private structure
1392 * @queue: RX queue index
1394 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1398 for (i = 0; i < DMA_RX_SIZE; i++)
1399 stmmac_free_rx_buffer(priv, queue, i);
1403 * dma_free_tx_skbufs - free TX dma buffers
1404 * @priv: private structure
1405 * @queue: TX queue index
1407 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1411 for (i = 0; i < DMA_TX_SIZE; i++)
1412 stmmac_free_tx_buffer(priv, queue, i);
1416 * free_dma_rx_desc_resources - free RX dma desc resources
1417 * @priv: private structure
1419 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1421 u32 rx_count = priv->plat->rx_queues_to_use;
1424 /* Free RX queue resources */
1425 for (queue = 0; queue < rx_count; queue++) {
1426 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1428 /* Release the DMA RX socket buffers */
1429 dma_free_rx_skbufs(priv, queue);
1431 /* Free DMA regions of consistent memory previously allocated */
1432 if (!priv->extend_desc)
1433 dma_free_coherent(priv->device,
1434 DMA_RX_SIZE * sizeof(struct dma_desc),
1435 rx_q->dma_rx, rx_q->dma_rx_phy);
1437 dma_free_coherent(priv->device, DMA_RX_SIZE *
1438 sizeof(struct dma_extended_desc),
1439 rx_q->dma_erx, rx_q->dma_rx_phy);
1441 kfree(rx_q->rx_skbuff_dma);
1442 kfree(rx_q->rx_skbuff);
1447 * free_dma_tx_desc_resources - free TX dma desc resources
1448 * @priv: private structure
1450 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1452 u32 tx_count = priv->plat->tx_queues_to_use;
1455 /* Free TX queue resources */
1456 for (queue = 0; queue < tx_count; queue++) {
1457 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1459 /* Release the DMA TX socket buffers */
1460 dma_free_tx_skbufs(priv, queue);
1462 /* Free DMA regions of consistent memory previously allocated */
1463 if (!priv->extend_desc)
1464 dma_free_coherent(priv->device,
1465 DMA_TX_SIZE * sizeof(struct dma_desc),
1466 tx_q->dma_tx, tx_q->dma_tx_phy);
1468 dma_free_coherent(priv->device, DMA_TX_SIZE *
1469 sizeof(struct dma_extended_desc),
1470 tx_q->dma_etx, tx_q->dma_tx_phy);
1472 kfree(tx_q->tx_skbuff_dma);
1473 kfree(tx_q->tx_skbuff);
1478 * alloc_dma_rx_desc_resources - alloc RX resources.
1479 * @priv: private structure
1480 * Description: according to which descriptor can be used (extend or basic)
1481 * this function allocates the resources for TX and RX paths. In case of
1482 * reception, for example, it pre-allocated the RX socket buffer in order to
1483 * allow zero-copy mechanism.
1485 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1487 u32 rx_count = priv->plat->rx_queues_to_use;
1491 /* RX queues buffers and DMA */
1492 for (queue = 0; queue < rx_count; queue++) {
1493 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1495 rx_q->queue_index = queue;
1496 rx_q->priv_data = priv;
1498 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1501 if (!rx_q->rx_skbuff_dma)
1504 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1505 sizeof(struct sk_buff *),
1507 if (!rx_q->rx_skbuff)
1510 if (priv->extend_desc) {
1511 rx_q->dma_erx = dma_zalloc_coherent(priv->device,
1521 rx_q->dma_rx = dma_zalloc_coherent(priv->device,
1535 free_dma_rx_desc_resources(priv);
1541 * alloc_dma_tx_desc_resources - alloc TX resources.
1542 * @priv: private structure
1543 * Description: according to which descriptor can be used (extend or basic)
1544 * this function allocates the resources for TX and RX paths. In case of
1545 * reception, for example, it pre-allocated the RX socket buffer in order to
1546 * allow zero-copy mechanism.
1548 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1550 u32 tx_count = priv->plat->tx_queues_to_use;
1554 /* TX queues buffers and DMA */
1555 for (queue = 0; queue < tx_count; queue++) {
1556 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1558 tx_q->queue_index = queue;
1559 tx_q->priv_data = priv;
1561 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1562 sizeof(*tx_q->tx_skbuff_dma),
1564 if (!tx_q->tx_skbuff_dma)
1567 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1568 sizeof(struct sk_buff *),
1570 if (!tx_q->tx_skbuff)
1571 goto err_dma_buffers;
1573 if (priv->extend_desc) {
1574 tx_q->dma_etx = dma_zalloc_coherent(priv->device,
1581 goto err_dma_buffers;
1583 tx_q->dma_tx = dma_zalloc_coherent(priv->device,
1590 goto err_dma_buffers;
1597 free_dma_tx_desc_resources(priv);
1603 * alloc_dma_desc_resources - alloc TX/RX resources.
1604 * @priv: private structure
1605 * Description: according to which descriptor can be used (extend or basic)
1606 * this function allocates the resources for TX and RX paths. In case of
1607 * reception, for example, it pre-allocated the RX socket buffer in order to
1608 * allow zero-copy mechanism.
1610 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1613 int ret = alloc_dma_rx_desc_resources(priv);
1618 ret = alloc_dma_tx_desc_resources(priv);
1624 * free_dma_desc_resources - free dma desc resources
1625 * @priv: private structure
1627 static void free_dma_desc_resources(struct stmmac_priv *priv)
1629 /* Release the DMA RX socket buffers */
1630 free_dma_rx_desc_resources(priv);
1632 /* Release the DMA TX socket buffers */
1633 free_dma_tx_desc_resources(priv);
1637 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1638 * @priv: driver private structure
1639 * Description: It is used for enabling the rx queues in the MAC
1641 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1643 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1647 for (queue = 0; queue < rx_queues_count; queue++) {
1648 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1649 priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);
1654 * stmmac_start_rx_dma - start RX DMA channel
1655 * @priv: driver private structure
1656 * @chan: RX channel index
1658 * This starts a RX DMA channel
1660 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1662 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1663 priv->hw->dma->start_rx(priv->ioaddr, chan);
1667 * stmmac_start_tx_dma - start TX DMA channel
1668 * @priv: driver private structure
1669 * @chan: TX channel index
1671 * This starts a TX DMA channel
1673 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1675 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1676 priv->hw->dma->start_tx(priv->ioaddr, chan);
1680 * stmmac_stop_rx_dma - stop RX DMA channel
1681 * @priv: driver private structure
1682 * @chan: RX channel index
1684 * This stops a RX DMA channel
1686 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1688 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1689 priv->hw->dma->stop_rx(priv->ioaddr, chan);
1693 * stmmac_stop_tx_dma - stop TX DMA channel
1694 * @priv: driver private structure
1695 * @chan: TX channel index
1697 * This stops a TX DMA channel
1699 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1701 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1702 priv->hw->dma->stop_tx(priv->ioaddr, chan);
1706 * stmmac_start_all_dma - start all RX and TX DMA channels
1707 * @priv: driver private structure
1709 * This starts all the RX and TX DMA channels
1711 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1713 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1714 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1717 for (chan = 0; chan < rx_channels_count; chan++)
1718 stmmac_start_rx_dma(priv, chan);
1720 for (chan = 0; chan < tx_channels_count; chan++)
1721 stmmac_start_tx_dma(priv, chan);
1725 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1726 * @priv: driver private structure
1728 * This stops the RX and TX DMA channels
1730 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1732 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1733 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1736 for (chan = 0; chan < rx_channels_count; chan++)
1737 stmmac_stop_rx_dma(priv, chan);
1739 for (chan = 0; chan < tx_channels_count; chan++)
1740 stmmac_stop_tx_dma(priv, chan);
1744 * stmmac_dma_operation_mode - HW DMA operation mode
1745 * @priv: driver private structure
1746 * Description: it is used for configuring the DMA operation mode register in
1747 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1749 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1751 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1752 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1753 int rxfifosz = priv->plat->rx_fifo_size;
1759 rxfifosz = priv->dma_cap.rx_fifo_size;
1761 if (priv->plat->force_thresh_dma_mode) {
1764 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1766 * In case of GMAC, SF mode can be enabled
1767 * to perform the TX COE in HW. This depends on:
1768 * 1) TX COE if actually supported
1769 * 2) There is no bugged Jumbo frame support
1770 * that needs to not insert csum in the TDES.
1772 txmode = SF_DMA_MODE;
1773 rxmode = SF_DMA_MODE;
1774 priv->xstats.threshold = SF_DMA_MODE;
1777 rxmode = SF_DMA_MODE;
1780 /* configure all channels */
1781 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1782 for (chan = 0; chan < rx_channels_count; chan++)
1783 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
1786 for (chan = 0; chan < tx_channels_count; chan++)
1787 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan);
1789 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
1795 * stmmac_tx_clean - to manage the transmission completion
1796 * @priv: driver private structure
1797 * @queue: TX queue index
1798 * Description: it reclaims the transmit resources after transmission completes.
1800 static void stmmac_tx_clean(struct stmmac_priv *priv, u32 queue)
1802 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1803 unsigned int bytes_compl = 0, pkts_compl = 0;
1804 unsigned int entry = tx_q->dirty_tx;
1806 netif_tx_lock(priv->dev);
1808 priv->xstats.tx_clean++;
1810 while (entry != tx_q->cur_tx) {
1811 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1815 if (priv->extend_desc)
1816 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1818 p = tx_q->dma_tx + entry;
1820 status = priv->hw->desc->tx_status(&priv->dev->stats,
1823 /* Check if the descriptor is owned by the DMA */
1824 if (unlikely(status & tx_dma_own))
1827 /* Just consider the last segment and ...*/
1828 if (likely(!(status & tx_not_ls))) {
1829 /* ... verify the status error condition */
1830 if (unlikely(status & tx_err)) {
1831 priv->dev->stats.tx_errors++;
1833 priv->dev->stats.tx_packets++;
1834 priv->xstats.tx_pkt_n++;
1836 stmmac_get_tx_hwtstamp(priv, p, skb);
1839 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1840 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1841 dma_unmap_page(priv->device,
1842 tx_q->tx_skbuff_dma[entry].buf,
1843 tx_q->tx_skbuff_dma[entry].len,
1846 dma_unmap_single(priv->device,
1847 tx_q->tx_skbuff_dma[entry].buf,
1848 tx_q->tx_skbuff_dma[entry].len,
1850 tx_q->tx_skbuff_dma[entry].buf = 0;
1851 tx_q->tx_skbuff_dma[entry].len = 0;
1852 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1855 if (priv->hw->mode->clean_desc3)
1856 priv->hw->mode->clean_desc3(tx_q, p);
1858 tx_q->tx_skbuff_dma[entry].last_segment = false;
1859 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1861 if (likely(skb != NULL)) {
1863 bytes_compl += skb->len;
1864 dev_consume_skb_any(skb);
1865 tx_q->tx_skbuff[entry] = NULL;
1868 priv->hw->desc->release_tx_desc(p, priv->mode);
1870 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1872 tx_q->dirty_tx = entry;
1874 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1875 pkts_compl, bytes_compl);
1877 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1879 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1881 netif_dbg(priv, tx_done, priv->dev,
1882 "%s: restart transmit\n", __func__);
1883 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1886 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1887 stmmac_enable_eee_mode(priv);
1888 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1890 netif_tx_unlock(priv->dev);
1893 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv, u32 chan)
1895 priv->hw->dma->enable_dma_irq(priv->ioaddr, chan);
1898 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv, u32 chan)
1900 priv->hw->dma->disable_dma_irq(priv->ioaddr, chan);
1904 * stmmac_tx_err - to manage the tx error
1905 * @priv: driver private structure
1906 * @chan: channel index
1907 * Description: it cleans the descriptors and restarts the transmission
1908 * in case of transmission errors.
1910 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1912 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1915 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1917 stmmac_stop_tx_dma(priv, chan);
1918 dma_free_tx_skbufs(priv, chan);
1919 for (i = 0; i < DMA_TX_SIZE; i++)
1920 if (priv->extend_desc)
1921 priv->hw->desc->init_tx_desc(&tx_q->dma_etx[i].basic,
1923 (i == DMA_TX_SIZE - 1));
1925 priv->hw->desc->init_tx_desc(&tx_q->dma_tx[i],
1927 (i == DMA_TX_SIZE - 1));
1930 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1931 stmmac_start_tx_dma(priv, chan);
1933 priv->dev->stats.tx_errors++;
1934 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1938 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1939 * @priv: driver private structure
1940 * @txmode: TX operating mode
1941 * @rxmode: RX operating mode
1942 * @chan: channel index
1943 * Description: it is used for configuring of the DMA operation mode in
1944 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1947 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1948 u32 rxmode, u32 chan)
1950 int rxfifosz = priv->plat->rx_fifo_size;
1953 rxfifosz = priv->dma_cap.rx_fifo_size;
1955 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1956 priv->hw->dma->dma_rx_mode(priv->ioaddr, rxmode, chan,
1958 priv->hw->dma->dma_tx_mode(priv->ioaddr, txmode, chan);
1960 priv->hw->dma->dma_mode(priv->ioaddr, txmode, rxmode,
1966 * stmmac_dma_interrupt - DMA ISR
1967 * @priv: driver private structure
1968 * Description: this is the DMA ISR. It is called by the main ISR.
1969 * It calls the dwmac dma routine and schedule poll method in case of some
1972 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1974 u32 tx_channel_count = priv->plat->tx_queues_to_use;
1978 for (chan = 0; chan < tx_channel_count; chan++) {
1979 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
1981 status = priv->hw->dma->dma_interrupt(priv->ioaddr,
1982 &priv->xstats, chan);
1983 if (likely((status & handle_rx)) || (status & handle_tx)) {
1984 if (likely(napi_schedule_prep(&rx_q->napi))) {
1985 stmmac_disable_dma_irq(priv, chan);
1986 __napi_schedule(&rx_q->napi);
1990 if (unlikely(status & tx_hard_error_bump_tc)) {
1991 /* Try to bump up the dma threshold on this failure */
1992 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1995 if (priv->plat->force_thresh_dma_mode)
1996 stmmac_set_dma_operation_mode(priv,
2001 stmmac_set_dma_operation_mode(priv,
2005 priv->xstats.threshold = tc;
2007 } else if (unlikely(status == tx_hard_error)) {
2008 stmmac_tx_err(priv, chan);
2014 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2015 * @priv: driver private structure
2016 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2018 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2020 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2021 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2023 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2024 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
2025 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
2027 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
2028 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
2031 dwmac_mmc_intr_all_mask(priv->mmcaddr);
2033 if (priv->dma_cap.rmon) {
2034 dwmac_mmc_ctrl(priv->mmcaddr, mode);
2035 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2037 netdev_info(priv->dev, "No MAC Management Counters available\n");
2041 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
2042 * @priv: driver private structure
2043 * Description: select the Enhanced/Alternate or Normal descriptors.
2044 * In case of Enhanced/Alternate, it checks if the extended descriptors are
2045 * supported by the HW capability register.
2047 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
2049 if (priv->plat->enh_desc) {
2050 dev_info(priv->device, "Enhanced/Alternate descriptors\n");
2052 /* GMAC older than 3.50 has no extended descriptors */
2053 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
2054 dev_info(priv->device, "Enabled extended descriptors\n");
2055 priv->extend_desc = 1;
2057 dev_warn(priv->device, "Extended descriptors not supported\n");
2059 priv->hw->desc = &enh_desc_ops;
2061 dev_info(priv->device, "Normal descriptors\n");
2062 priv->hw->desc = &ndesc_ops;
2067 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2068 * @priv: driver private structure
2070 * new GMAC chip generations have a new register to indicate the
2071 * presence of the optional feature/functions.
2072 * This can be also used to override the value passed through the
2073 * platform and necessary for old MAC10/100 and GMAC chips.
2075 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2079 if (priv->hw->dma->get_hw_feature) {
2080 priv->hw->dma->get_hw_feature(priv->ioaddr,
2089 * stmmac_check_ether_addr - check if the MAC addr is valid
2090 * @priv: driver private structure
2092 * it is to verify if the MAC address is valid, in case of failures it
2093 * generates a random MAC address
2095 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2097 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2098 priv->hw->mac->get_umac_addr(priv->hw,
2099 priv->dev->dev_addr, 0);
2100 if (!is_valid_ether_addr(priv->dev->dev_addr))
2101 eth_hw_addr_random(priv->dev);
2102 netdev_info(priv->dev, "device MAC address %pM\n",
2103 priv->dev->dev_addr);
2108 * stmmac_init_dma_engine - DMA init.
2109 * @priv: driver private structure
2111 * It inits the DMA invoking the specific MAC/GMAC callback.
2112 * Some DMA parameters can be passed from the platform;
2113 * in case of these are not passed a default is kept for the MAC or GMAC.
2115 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2117 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2118 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2119 struct stmmac_rx_queue *rx_q;
2120 struct stmmac_tx_queue *tx_q;
2121 u32 dummy_dma_rx_phy = 0;
2122 u32 dummy_dma_tx_phy = 0;
2127 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2128 dev_err(priv->device, "Invalid DMA configuration\n");
2132 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2135 ret = priv->hw->dma->reset(priv->ioaddr);
2137 dev_err(priv->device, "Failed to reset the dma\n");
2141 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2142 /* DMA Configuration */
2143 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
2144 dummy_dma_tx_phy, dummy_dma_rx_phy, atds);
2146 /* DMA RX Channel Configuration */
2147 for (chan = 0; chan < rx_channels_count; chan++) {
2148 rx_q = &priv->rx_queue[chan];
2150 priv->hw->dma->init_rx_chan(priv->ioaddr,
2151 priv->plat->dma_cfg,
2152 rx_q->dma_rx_phy, chan);
2154 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2155 (DMA_RX_SIZE * sizeof(struct dma_desc));
2156 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2161 /* DMA TX Channel Configuration */
2162 for (chan = 0; chan < tx_channels_count; chan++) {
2163 tx_q = &priv->tx_queue[chan];
2165 priv->hw->dma->init_chan(priv->ioaddr,
2166 priv->plat->dma_cfg,
2169 priv->hw->dma->init_tx_chan(priv->ioaddr,
2170 priv->plat->dma_cfg,
2171 tx_q->dma_tx_phy, chan);
2173 tx_q->tx_tail_addr = tx_q->dma_tx_phy +
2174 (DMA_TX_SIZE * sizeof(struct dma_desc));
2175 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr,
2180 rx_q = &priv->rx_queue[chan];
2181 tx_q = &priv->tx_queue[chan];
2182 priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
2183 tx_q->dma_tx_phy, rx_q->dma_rx_phy, atds);
2186 if (priv->plat->axi && priv->hw->dma->axi)
2187 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
2193 * stmmac_tx_timer - mitigation sw timer for tx.
2194 * @data: data pointer
2196 * This is the timer handler to directly invoke the stmmac_tx_clean.
2198 static void stmmac_tx_timer(unsigned long data)
2200 struct stmmac_priv *priv = (struct stmmac_priv *)data;
2201 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2204 /* let's scan all the tx queues */
2205 for (queue = 0; queue < tx_queues_count; queue++)
2206 stmmac_tx_clean(priv, queue);
2210 * stmmac_init_tx_coalesce - init tx mitigation options.
2211 * @priv: driver private structure
2213 * This inits the transmit coalesce parameters: i.e. timer rate,
2214 * timer handler and default threshold used for enabling the
2215 * interrupt on completion bit.
2217 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2219 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2220 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2221 init_timer(&priv->txtimer);
2222 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
2223 priv->txtimer.data = (unsigned long)priv;
2224 priv->txtimer.function = stmmac_tx_timer;
2225 add_timer(&priv->txtimer);
2228 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2230 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2231 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2234 /* set TX ring length */
2235 if (priv->hw->dma->set_tx_ring_len) {
2236 for (chan = 0; chan < tx_channels_count; chan++)
2237 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
2238 (DMA_TX_SIZE - 1), chan);
2241 /* set RX ring length */
2242 if (priv->hw->dma->set_rx_ring_len) {
2243 for (chan = 0; chan < rx_channels_count; chan++)
2244 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
2245 (DMA_RX_SIZE - 1), chan);
2250 * stmmac_set_tx_queue_weight - Set TX queue weight
2251 * @priv: driver private structure
2252 * Description: It is used for setting TX queues weight
2254 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2256 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2260 for (queue = 0; queue < tx_queues_count; queue++) {
2261 weight = priv->plat->tx_queues_cfg[queue].weight;
2262 priv->hw->mac->set_mtl_tx_queue_weight(priv->hw, weight, queue);
2267 * stmmac_configure_cbs - Configure CBS in TX queue
2268 * @priv: driver private structure
2269 * Description: It is used for configuring CBS in AVB TX queues
2271 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2273 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2277 /* queue 0 is reserved for legacy traffic */
2278 for (queue = 1; queue < tx_queues_count; queue++) {
2279 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2280 if (mode_to_use == MTL_QUEUE_DCB)
2283 priv->hw->mac->config_cbs(priv->hw,
2284 priv->plat->tx_queues_cfg[queue].send_slope,
2285 priv->plat->tx_queues_cfg[queue].idle_slope,
2286 priv->plat->tx_queues_cfg[queue].high_credit,
2287 priv->plat->tx_queues_cfg[queue].low_credit,
2293 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2294 * @priv: driver private structure
2295 * Description: It is used for mapping RX queues to RX dma channels
2297 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2299 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2303 for (queue = 0; queue < rx_queues_count; queue++) {
2304 chan = priv->plat->rx_queues_cfg[queue].chan;
2305 priv->hw->mac->map_mtl_to_dma(priv->hw, queue, chan);
2310 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2311 * @priv: driver private structure
2312 * Description: It is used for configuring the RX Queue Priority
2314 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2316 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2320 for (queue = 0; queue < rx_queues_count; queue++) {
2321 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2324 prio = priv->plat->rx_queues_cfg[queue].prio;
2325 priv->hw->mac->rx_queue_prio(priv->hw, prio, queue);
2330 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2331 * @priv: driver private structure
2332 * Description: It is used for configuring the TX Queue Priority
2334 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2336 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2340 for (queue = 0; queue < tx_queues_count; queue++) {
2341 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2344 prio = priv->plat->tx_queues_cfg[queue].prio;
2345 priv->hw->mac->tx_queue_prio(priv->hw, prio, queue);
2350 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2351 * @priv: driver private structure
2352 * Description: It is used for configuring the RX queue routing
2354 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2356 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2360 for (queue = 0; queue < rx_queues_count; queue++) {
2361 /* no specific packet type routing specified for the queue */
2362 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2365 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2366 priv->hw->mac->rx_queue_prio(priv->hw, packet, queue);
2371 * stmmac_mtl_configuration - Configure MTL
2372 * @priv: driver private structure
2373 * Description: It is used for configurring MTL
2375 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2377 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2378 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2380 if (tx_queues_count > 1 && priv->hw->mac->set_mtl_tx_queue_weight)
2381 stmmac_set_tx_queue_weight(priv);
2383 /* Configure MTL RX algorithms */
2384 if (rx_queues_count > 1 && priv->hw->mac->prog_mtl_rx_algorithms)
2385 priv->hw->mac->prog_mtl_rx_algorithms(priv->hw,
2386 priv->plat->rx_sched_algorithm);
2388 /* Configure MTL TX algorithms */
2389 if (tx_queues_count > 1 && priv->hw->mac->prog_mtl_tx_algorithms)
2390 priv->hw->mac->prog_mtl_tx_algorithms(priv->hw,
2391 priv->plat->tx_sched_algorithm);
2393 /* Configure CBS in AVB TX queues */
2394 if (tx_queues_count > 1 && priv->hw->mac->config_cbs)
2395 stmmac_configure_cbs(priv);
2397 /* Map RX MTL to DMA channels */
2398 if (priv->hw->mac->map_mtl_to_dma)
2399 stmmac_rx_queue_dma_chan_map(priv);
2401 /* Enable MAC RX Queues */
2402 if (priv->hw->mac->rx_queue_enable)
2403 stmmac_mac_enable_rx_queues(priv);
2405 /* Set RX priorities */
2406 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_prio)
2407 stmmac_mac_config_rx_queues_prio(priv);
2409 /* Set TX priorities */
2410 if (tx_queues_count > 1 && priv->hw->mac->tx_queue_prio)
2411 stmmac_mac_config_tx_queues_prio(priv);
2413 /* Set RX routing */
2414 if (rx_queues_count > 1 && priv->hw->mac->rx_queue_routing)
2415 stmmac_mac_config_rx_queues_routing(priv);
2419 * stmmac_hw_setup - setup mac in a usable state.
2420 * @dev : pointer to the device structure.
2422 * this is the main function to setup the HW in a usable state because the
2423 * dma engine is reset, the core registers are configured (e.g. AXI,
2424 * Checksum features, timers). The DMA is ready to start receiving and
2427 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2430 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2432 struct stmmac_priv *priv = netdev_priv(dev);
2433 u32 rx_cnt = priv->plat->rx_queues_to_use;
2434 u32 tx_cnt = priv->plat->tx_queues_to_use;
2438 /* DMA initialization and SW reset */
2439 ret = stmmac_init_dma_engine(priv);
2441 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2446 /* Copy the MAC addr into the HW */
2447 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
2449 /* PS and related bits will be programmed according to the speed */
2450 if (priv->hw->pcs) {
2451 int speed = priv->plat->mac_port_sel_speed;
2453 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2454 (speed == SPEED_1000)) {
2455 priv->hw->ps = speed;
2457 dev_warn(priv->device, "invalid port speed\n");
2462 /* Initialize the MAC Core */
2463 priv->hw->mac->core_init(priv->hw, dev->mtu);
2466 if (priv->synopsys_id >= DWMAC_CORE_4_00)
2467 stmmac_mtl_configuration(priv);
2469 ret = priv->hw->mac->rx_ipc(priv->hw);
2471 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2472 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2473 priv->hw->rx_csum = 0;
2476 /* Enable the MAC Rx/Tx */
2477 priv->hw->mac->set_mac(priv->ioaddr, true);
2479 /* Set the HW DMA mode and the COE */
2480 stmmac_dma_operation_mode(priv);
2482 stmmac_mmc_setup(priv);
2485 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2487 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2489 ret = stmmac_init_ptp(priv);
2490 if (ret == -EOPNOTSUPP)
2491 netdev_warn(priv->dev, "PTP not supported by HW\n");
2493 netdev_warn(priv->dev, "PTP init failed\n");
2496 #ifdef CONFIG_DEBUG_FS
2497 ret = stmmac_init_fs(dev);
2499 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
2502 /* Start the ball rolling... */
2503 stmmac_start_all_dma(priv);
2505 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2507 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
2508 priv->rx_riwt = MAX_DMA_RIWT;
2509 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2512 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
2513 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
2515 /* set TX and RX rings length */
2516 stmmac_set_rings_length(priv);
2520 for (chan = 0; chan < tx_cnt; chan++)
2521 priv->hw->dma->enable_tso(priv->ioaddr, 1, chan);
2527 static void stmmac_hw_teardown(struct net_device *dev)
2529 struct stmmac_priv *priv = netdev_priv(dev);
2531 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2535 * stmmac_open - open entry point of the driver
2536 * @dev : pointer to the device structure.
2538 * This function is the open entry point of the driver.
2540 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2543 static int stmmac_open(struct net_device *dev)
2545 struct stmmac_priv *priv = netdev_priv(dev);
2548 stmmac_check_ether_addr(priv);
2550 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2551 priv->hw->pcs != STMMAC_PCS_TBI &&
2552 priv->hw->pcs != STMMAC_PCS_RTBI) {
2553 ret = stmmac_init_phy(dev);
2555 netdev_err(priv->dev,
2556 "%s: Cannot attach to PHY (error: %d)\n",
2562 /* Extra statistics */
2563 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2564 priv->xstats.threshold = tc;
2566 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2567 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2569 ret = alloc_dma_desc_resources(priv);
2571 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2573 goto dma_desc_error;
2576 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2578 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2583 ret = stmmac_hw_setup(dev, true);
2585 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2589 stmmac_init_tx_coalesce(priv);
2592 phy_start(dev->phydev);
2594 /* Request the IRQ lines */
2595 ret = request_irq(dev->irq, stmmac_interrupt,
2596 IRQF_SHARED, dev->name, dev);
2597 if (unlikely(ret < 0)) {
2598 netdev_err(priv->dev,
2599 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2600 __func__, dev->irq, ret);
2604 /* Request the Wake IRQ in case of another line is used for WoL */
2605 if (priv->wol_irq != dev->irq) {
2606 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2607 IRQF_SHARED, dev->name, dev);
2608 if (unlikely(ret < 0)) {
2609 netdev_err(priv->dev,
2610 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2611 __func__, priv->wol_irq, ret);
2616 /* Request the IRQ lines */
2617 if (priv->lpi_irq > 0) {
2618 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2620 if (unlikely(ret < 0)) {
2621 netdev_err(priv->dev,
2622 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2623 __func__, priv->lpi_irq, ret);
2628 stmmac_enable_all_queues(priv);
2629 stmmac_start_all_queues(priv);
2634 if (priv->wol_irq != dev->irq)
2635 free_irq(priv->wol_irq, dev);
2637 free_irq(dev->irq, dev);
2640 phy_stop(dev->phydev);
2642 del_timer_sync(&priv->txtimer);
2643 stmmac_hw_teardown(dev);
2645 free_dma_desc_resources(priv);
2648 phy_disconnect(dev->phydev);
2654 * stmmac_release - close entry point of the driver
2655 * @dev : device pointer.
2657 * This is the stop entry point of the driver.
2659 static int stmmac_release(struct net_device *dev)
2661 struct stmmac_priv *priv = netdev_priv(dev);
2663 if (priv->eee_enabled)
2664 del_timer_sync(&priv->eee_ctrl_timer);
2666 /* Stop and disconnect the PHY */
2668 phy_stop(dev->phydev);
2669 phy_disconnect(dev->phydev);
2672 stmmac_stop_all_queues(priv);
2674 stmmac_disable_all_queues(priv);
2676 del_timer_sync(&priv->txtimer);
2678 /* Free the IRQ lines */
2679 free_irq(dev->irq, dev);
2680 if (priv->wol_irq != dev->irq)
2681 free_irq(priv->wol_irq, dev);
2682 if (priv->lpi_irq > 0)
2683 free_irq(priv->lpi_irq, dev);
2685 /* Stop TX/RX DMA and clear the descriptors */
2686 stmmac_stop_all_dma(priv);
2688 /* Release and free the Rx/Tx resources */
2689 free_dma_desc_resources(priv);
2691 /* Disable the MAC Rx/Tx */
2692 priv->hw->mac->set_mac(priv->ioaddr, false);
2694 netif_carrier_off(dev);
2696 #ifdef CONFIG_DEBUG_FS
2697 stmmac_exit_fs(dev);
2700 stmmac_release_ptp(priv);
2706 * stmmac_tso_allocator - close entry point of the driver
2707 * @priv: driver private structure
2708 * @des: buffer start address
2709 * @total_len: total length to fill in descriptors
2710 * @last_segmant: condition for the last descriptor
2711 * @queue: TX queue index
2713 * This function fills descriptor and request new descriptors according to
2714 * buffer length to fill
2716 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2717 int total_len, bool last_segment, u32 queue)
2719 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2720 struct dma_desc *desc;
2724 tmp_len = total_len;
2726 while (tmp_len > 0) {
2727 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2728 desc = tx_q->dma_tx + tx_q->cur_tx;
2730 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2731 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2732 TSO_MAX_BUFF_SIZE : tmp_len;
2734 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
2736 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2739 tmp_len -= TSO_MAX_BUFF_SIZE;
2744 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2745 * @skb : the socket buffer
2746 * @dev : device pointer
2747 * Description: this is the transmit function that is called on TSO frames
2748 * (support available on GMAC4 and newer chips).
2749 * Diagram below show the ring programming in case of TSO frames:
2753 * | DES0 |---> buffer1 = L2/L3/L4 header
2754 * | DES1 |---> TCP Payload (can continue on next descr...)
2755 * | DES2 |---> buffer 1 and 2 len
2756 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2762 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2764 * | DES2 | --> buffer 1 and 2 len
2768 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2770 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2772 struct dma_desc *desc, *first, *mss_desc = NULL;
2773 struct stmmac_priv *priv = netdev_priv(dev);
2774 int nfrags = skb_shinfo(skb)->nr_frags;
2775 u32 queue = skb_get_queue_mapping(skb);
2776 unsigned int first_entry, des;
2777 struct stmmac_tx_queue *tx_q;
2778 int tmp_pay_len = 0;
2783 tx_q = &priv->tx_queue[queue];
2785 /* Compute header lengths */
2786 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2788 /* Desc availability based on threshold should be enough safe */
2789 if (unlikely(stmmac_tx_avail(priv, queue) <
2790 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2791 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2792 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2794 /* This is a hard error, log it. */
2795 netdev_err(priv->dev,
2796 "%s: Tx Ring full when queue awake\n",
2799 return NETDEV_TX_BUSY;
2802 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2804 mss = skb_shinfo(skb)->gso_size;
2806 /* set new MSS value if needed */
2807 if (mss != priv->mss) {
2808 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2809 priv->hw->desc->set_mss(mss_desc, mss);
2811 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2814 if (netif_msg_tx_queued(priv)) {
2815 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2816 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2817 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2821 first_entry = tx_q->cur_tx;
2823 desc = tx_q->dma_tx + first_entry;
2826 /* first descriptor: fill Headers on Buf1 */
2827 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2829 if (dma_mapping_error(priv->device, des))
2832 tx_q->tx_skbuff_dma[first_entry].buf = des;
2833 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2835 first->des0 = cpu_to_le32(des);
2837 /* Fill start of payload in buff2 of first descriptor */
2839 first->des1 = cpu_to_le32(des + proto_hdr_len);
2841 /* If needed take extra descriptors to fill the remaining payload */
2842 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2844 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2846 /* Prepare fragments */
2847 for (i = 0; i < nfrags; i++) {
2848 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2850 des = skb_frag_dma_map(priv->device, frag, 0,
2851 skb_frag_size(frag),
2853 if (dma_mapping_error(priv->device, des))
2856 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2857 (i == nfrags - 1), queue);
2859 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2860 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2861 tx_q->tx_skbuff[tx_q->cur_tx] = NULL;
2862 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2865 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2867 /* Only the last descriptor gets to point to the skb. */
2868 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2870 /* We've used all descriptors we need for this skb, however,
2871 * advance cur_tx so that it references a fresh descriptor.
2872 * ndo_start_xmit will fill this descriptor the next time it's
2873 * called and stmmac_tx_clean may clean up to this descriptor.
2875 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2877 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2878 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2880 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2883 dev->stats.tx_bytes += skb->len;
2884 priv->xstats.tx_tso_frames++;
2885 priv->xstats.tx_tso_nfrags += nfrags;
2887 /* Manage tx mitigation */
2888 priv->tx_count_frames += nfrags + 1;
2889 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2890 mod_timer(&priv->txtimer,
2891 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2893 priv->tx_count_frames = 0;
2894 priv->hw->desc->set_tx_ic(desc);
2895 priv->xstats.tx_set_ic_bit++;
2898 if (!priv->hwts_tx_en)
2899 skb_tx_timestamp(skb);
2901 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2902 priv->hwts_tx_en)) {
2903 /* declare that device is doing timestamping */
2904 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2905 priv->hw->desc->enable_tx_timestamp(first);
2908 /* Complete the first descriptor before granting the DMA */
2909 priv->hw->desc->prepare_tso_tx_desc(first, 1,
2912 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2913 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2915 /* If context desc is used to change MSS */
2917 priv->hw->desc->set_tx_owner(mss_desc);
2919 /* The own bit must be the latest setting done when prepare the
2920 * descriptor and then barrier is needed to make sure that
2921 * all is coherent before granting the DMA engine.
2925 if (netif_msg_pktdata(priv)) {
2926 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2927 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2928 tx_q->cur_tx, first, nfrags);
2930 priv->hw->desc->display_ring((void *)tx_q->dma_tx, DMA_TX_SIZE,
2933 pr_info(">>> frame to be transmitted: ");
2934 print_pkt(skb->data, skb_headlen(skb));
2937 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2939 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,
2942 return NETDEV_TX_OK;
2945 dev_err(priv->device, "Tx dma map failed\n");
2947 priv->dev->stats.tx_dropped++;
2948 return NETDEV_TX_OK;
2952 * stmmac_xmit - Tx entry point of the driver
2953 * @skb : the socket buffer
2954 * @dev : device pointer
2955 * Description : this is the tx entry point of the driver.
2956 * It programs the chain or the ring and supports oversized frames
2959 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2961 struct stmmac_priv *priv = netdev_priv(dev);
2962 unsigned int nopaged_len = skb_headlen(skb);
2963 int i, csum_insertion = 0, is_jumbo = 0;
2964 u32 queue = skb_get_queue_mapping(skb);
2965 int nfrags = skb_shinfo(skb)->nr_frags;
2967 unsigned int first_entry;
2968 struct dma_desc *desc, *first;
2969 struct stmmac_tx_queue *tx_q;
2970 unsigned int enh_desc;
2973 tx_q = &priv->tx_queue[queue];
2975 /* Manage oversized TCP frames for GMAC4 device */
2976 if (skb_is_gso(skb) && priv->tso) {
2977 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2978 return stmmac_tso_xmit(skb, dev);
2981 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
2982 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2983 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2985 /* This is a hard error, log it. */
2986 netdev_err(priv->dev,
2987 "%s: Tx Ring full when queue awake\n",
2990 return NETDEV_TX_BUSY;
2993 if (priv->tx_path_in_lpi_mode)
2994 stmmac_disable_eee_mode(priv);
2996 entry = tx_q->cur_tx;
2997 first_entry = entry;
2999 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3001 if (likely(priv->extend_desc))
3002 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3004 desc = tx_q->dma_tx + entry;
3008 enh_desc = priv->plat->enh_desc;
3009 /* To program the descriptors according to the size of the frame */
3011 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
3013 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
3015 entry = priv->hw->mode->jumbo_frm(tx_q, skb, csum_insertion);
3016 if (unlikely(entry < 0))
3020 for (i = 0; i < nfrags; i++) {
3021 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3022 int len = skb_frag_size(frag);
3023 bool last_segment = (i == (nfrags - 1));
3025 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3027 if (likely(priv->extend_desc))
3028 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3030 desc = tx_q->dma_tx + entry;
3032 des = skb_frag_dma_map(priv->device, frag, 0, len,
3034 if (dma_mapping_error(priv->device, des))
3035 goto dma_map_err; /* should reuse desc w/o issues */
3037 tx_q->tx_skbuff[entry] = NULL;
3039 tx_q->tx_skbuff_dma[entry].buf = des;
3040 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3041 desc->des0 = cpu_to_le32(des);
3043 desc->des2 = cpu_to_le32(des);
3045 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3046 tx_q->tx_skbuff_dma[entry].len = len;
3047 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3049 /* Prepare the descriptor and set the own bit too */
3050 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
3051 priv->mode, 1, last_segment,
3055 /* Only the last descriptor gets to point to the skb. */
3056 tx_q->tx_skbuff[entry] = skb;
3058 /* We've used all descriptors we need for this skb, however,
3059 * advance cur_tx so that it references a fresh descriptor.
3060 * ndo_start_xmit will fill this descriptor the next time it's
3061 * called and stmmac_tx_clean may clean up to this descriptor.
3063 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3064 tx_q->cur_tx = entry;
3066 if (netif_msg_pktdata(priv)) {
3069 netdev_dbg(priv->dev,
3070 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3071 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3072 entry, first, nfrags);
3074 if (priv->extend_desc)
3075 tx_head = (void *)tx_q->dma_etx;
3077 tx_head = (void *)tx_q->dma_tx;
3079 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
3081 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3082 print_pkt(skb->data, skb->len);
3085 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3086 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3088 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3091 dev->stats.tx_bytes += skb->len;
3093 /* According to the coalesce parameter the IC bit for the latest
3094 * segment is reset and the timer re-started to clean the tx status.
3095 * This approach takes care about the fragments: desc is the first
3096 * element in case of no SG.
3098 priv->tx_count_frames += nfrags + 1;
3099 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
3100 mod_timer(&priv->txtimer,
3101 STMMAC_COAL_TIMER(priv->tx_coal_timer));
3103 priv->tx_count_frames = 0;
3104 priv->hw->desc->set_tx_ic(desc);
3105 priv->xstats.tx_set_ic_bit++;
3108 if (!priv->hwts_tx_en)
3109 skb_tx_timestamp(skb);
3111 /* Ready to fill the first descriptor and set the OWN bit w/o any
3112 * problems because all the descriptors are actually ready to be
3113 * passed to the DMA engine.
3115 if (likely(!is_jumbo)) {
3116 bool last_segment = (nfrags == 0);
3118 des = dma_map_single(priv->device, skb->data,
3119 nopaged_len, DMA_TO_DEVICE);
3120 if (dma_mapping_error(priv->device, des))
3123 tx_q->tx_skbuff_dma[first_entry].buf = des;
3124 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3125 first->des0 = cpu_to_le32(des);
3127 first->des2 = cpu_to_le32(des);
3129 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3130 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3132 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3133 priv->hwts_tx_en)) {
3134 /* declare that device is doing timestamping */
3135 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3136 priv->hw->desc->enable_tx_timestamp(first);
3139 /* Prepare the first descriptor setting the OWN bit too */
3140 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
3141 csum_insertion, priv->mode, 1,
3142 last_segment, skb->len);
3144 /* The own bit must be the latest setting done when prepare the
3145 * descriptor and then barrier is needed to make sure that
3146 * all is coherent before granting the DMA engine.
3151 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3153 if (priv->synopsys_id < DWMAC_CORE_4_00)
3154 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
3156 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, tx_q->tx_tail_addr,
3159 return NETDEV_TX_OK;
3162 netdev_err(priv->dev, "Tx DMA map failed\n");
3164 priv->dev->stats.tx_dropped++;
3165 return NETDEV_TX_OK;
3168 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3170 struct ethhdr *ehdr;
3173 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
3174 NETIF_F_HW_VLAN_CTAG_RX &&
3175 !__vlan_get_tag(skb, &vlanid)) {
3176 /* pop the vlan tag */
3177 ehdr = (struct ethhdr *)skb->data;
3178 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
3179 skb_pull(skb, VLAN_HLEN);
3180 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
3185 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3187 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3194 * stmmac_rx_refill - refill used skb preallocated buffers
3195 * @priv: driver private structure
3196 * @queue: RX queue index
3197 * Description : this is to reallocate the skb for the reception process
3198 * that is based on zero-copy.
3200 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3202 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3203 int dirty = stmmac_rx_dirty(priv, queue);
3204 unsigned int entry = rx_q->dirty_rx;
3206 int bfsize = priv->dma_buf_sz;
3208 while (dirty-- > 0) {
3211 if (priv->extend_desc)
3212 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3214 p = rx_q->dma_rx + entry;
3216 if (likely(!rx_q->rx_skbuff[entry])) {
3217 struct sk_buff *skb;
3219 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3220 if (unlikely(!skb)) {
3221 /* so for a while no zero-copy! */
3222 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3223 if (unlikely(net_ratelimit()))
3224 dev_err(priv->device,
3225 "fail to alloc skb entry %d\n",
3230 rx_q->rx_skbuff[entry] = skb;
3231 rx_q->rx_skbuff_dma[entry] =
3232 dma_map_single(priv->device, skb->data, bfsize,
3234 if (dma_mapping_error(priv->device,
3235 rx_q->rx_skbuff_dma[entry])) {
3236 netdev_err(priv->dev, "Rx DMA map failed\n");
3241 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
3242 p->des0 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);
3245 p->des2 = cpu_to_le32(rx_q->rx_skbuff_dma[entry]);
3247 if (priv->hw->mode->refill_desc3)
3248 priv->hw->mode->refill_desc3(rx_q, p);
3250 if (rx_q->rx_zeroc_thresh > 0)
3251 rx_q->rx_zeroc_thresh--;
3253 netif_dbg(priv, rx_status, priv->dev,
3254 "refill entry #%d\n", entry);
3258 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3259 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
3261 priv->hw->desc->set_rx_owner(p);
3265 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3267 rx_q->dirty_rx = entry;
3271 * stmmac_rx - manage the receive process
3272 * @priv: driver private structure
3273 * @limit: napi bugget
3274 * @queue: RX queue index.
3275 * Description : this the function called by the napi poll method.
3276 * It gets all the frames inside the ring.
3278 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3280 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3281 unsigned int entry = rx_q->cur_rx;
3282 int coe = priv->hw->rx_csum;
3283 unsigned int next_entry;
3284 unsigned int count = 0;
3286 if (netif_msg_rx_status(priv)) {
3289 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3290 if (priv->extend_desc)
3291 rx_head = (void *)rx_q->dma_erx;
3293 rx_head = (void *)rx_q->dma_rx;
3295 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
3297 while (count < limit) {
3300 struct dma_desc *np;
3302 if (priv->extend_desc)
3303 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3305 p = rx_q->dma_rx + entry;
3307 /* read the status of the incoming frame */
3308 status = priv->hw->desc->rx_status(&priv->dev->stats,
3310 /* check if managed by the DMA otherwise go ahead */
3311 if (unlikely(status & dma_own))
3316 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3317 next_entry = rx_q->cur_rx;
3319 if (priv->extend_desc)
3320 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3322 np = rx_q->dma_rx + next_entry;
3326 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
3327 priv->hw->desc->rx_extended_status(&priv->dev->stats,
3331 if (unlikely(status == discard_frame)) {
3332 priv->dev->stats.rx_errors++;
3333 if (priv->hwts_rx_en && !priv->extend_desc) {
3334 /* DESC2 & DESC3 will be overwritten by device
3335 * with timestamp value, hence reinitialize
3336 * them in stmmac_rx_refill() function so that
3337 * device can reuse it.
3339 rx_q->rx_skbuff[entry] = NULL;
3340 dma_unmap_single(priv->device,
3341 rx_q->rx_skbuff_dma[entry],
3346 struct sk_buff *skb;
3350 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
3351 des = le32_to_cpu(p->des0);
3353 des = le32_to_cpu(p->des2);
3355 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
3357 /* If frame length is greater than skb buffer size
3358 * (preallocated during init) then the packet is
3361 if (frame_len > priv->dma_buf_sz) {
3362 netdev_err(priv->dev,
3363 "len %d larger than size (%d)\n",
3364 frame_len, priv->dma_buf_sz);
3365 priv->dev->stats.rx_length_errors++;
3369 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3370 * Type frames (LLC/LLC-SNAP)
3372 if (unlikely(status != llc_snap))
3373 frame_len -= ETH_FCS_LEN;
3375 if (netif_msg_rx_status(priv)) {
3376 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3378 if (frame_len > ETH_FRAME_LEN)
3379 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3383 /* The zero-copy is always used for all the sizes
3384 * in case of GMAC4 because it needs
3385 * to refill the used descriptors, always.
3387 if (unlikely(!priv->plat->has_gmac4 &&
3388 ((frame_len < priv->rx_copybreak) ||
3389 stmmac_rx_threshold_count(rx_q)))) {
3390 skb = netdev_alloc_skb_ip_align(priv->dev,
3392 if (unlikely(!skb)) {
3393 if (net_ratelimit())
3394 dev_warn(priv->device,
3395 "packet dropped\n");
3396 priv->dev->stats.rx_dropped++;
3400 dma_sync_single_for_cpu(priv->device,
3404 skb_copy_to_linear_data(skb,
3406 rx_skbuff[entry]->data,
3409 skb_put(skb, frame_len);
3410 dma_sync_single_for_device(priv->device,
3415 skb = rx_q->rx_skbuff[entry];
3416 if (unlikely(!skb)) {
3417 netdev_err(priv->dev,
3418 "%s: Inconsistent Rx chain\n",
3420 priv->dev->stats.rx_dropped++;
3423 prefetch(skb->data - NET_IP_ALIGN);
3424 rx_q->rx_skbuff[entry] = NULL;
3425 rx_q->rx_zeroc_thresh++;
3427 skb_put(skb, frame_len);
3428 dma_unmap_single(priv->device,
3429 rx_q->rx_skbuff_dma[entry],
3434 if (netif_msg_pktdata(priv)) {
3435 netdev_dbg(priv->dev, "frame received (%dbytes)",
3437 print_pkt(skb->data, frame_len);
3440 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3442 stmmac_rx_vlan(priv->dev, skb);
3444 skb->protocol = eth_type_trans(skb, priv->dev);
3447 skb_checksum_none_assert(skb);
3449 skb->ip_summed = CHECKSUM_UNNECESSARY;
3451 napi_gro_receive(&rx_q->napi, skb);
3453 priv->dev->stats.rx_packets++;
3454 priv->dev->stats.rx_bytes += frame_len;
3459 stmmac_rx_refill(priv, queue);
3461 priv->xstats.rx_pkt_n += count;
3467 * stmmac_poll - stmmac poll method (NAPI)
3468 * @napi : pointer to the napi structure.
3469 * @budget : maximum number of packets that the current CPU can receive from
3472 * To look at the incoming frames and clear the tx resources.
3474 static int stmmac_poll(struct napi_struct *napi, int budget)
3476 struct stmmac_rx_queue *rx_q =
3477 container_of(napi, struct stmmac_rx_queue, napi);
3478 struct stmmac_priv *priv = rx_q->priv_data;
3479 u32 tx_count = priv->plat->tx_queues_to_use;
3480 u32 chan = rx_q->queue_index;
3484 priv->xstats.napi_poll++;
3486 /* check all the queues */
3487 for (queue = 0; queue < tx_count; queue++)
3488 stmmac_tx_clean(priv, queue);
3490 work_done = stmmac_rx(priv, budget, rx_q->queue_index);
3491 if (work_done < budget) {
3492 napi_complete_done(napi, work_done);
3493 stmmac_enable_dma_irq(priv, chan);
3500 * @dev : Pointer to net device structure
3501 * Description: this function is called when a packet transmission fails to
3502 * complete within a reasonable time. The driver will mark the error in the
3503 * netdev structure and arrange for the device to be reset to a sane state
3504 * in order to transmit a new packet.
3506 static void stmmac_tx_timeout(struct net_device *dev)
3508 struct stmmac_priv *priv = netdev_priv(dev);
3509 u32 tx_count = priv->plat->tx_queues_to_use;
3512 /* Clear Tx resources and restart transmitting again */
3513 for (chan = 0; chan < tx_count; chan++)
3514 stmmac_tx_err(priv, chan);
3518 * stmmac_set_rx_mode - entry point for multicast addressing
3519 * @dev : pointer to the device structure
3521 * This function is a driver entry point which gets called by the kernel
3522 * whenever multicast addresses must be enabled/disabled.
3526 static void stmmac_set_rx_mode(struct net_device *dev)
3528 struct stmmac_priv *priv = netdev_priv(dev);
3530 priv->hw->mac->set_filter(priv->hw, dev);
3534 * stmmac_change_mtu - entry point to change MTU size for the device.
3535 * @dev : device pointer.
3536 * @new_mtu : the new MTU size for the device.
3537 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3538 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3539 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3541 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3544 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3546 struct stmmac_priv *priv = netdev_priv(dev);
3548 if (netif_running(dev)) {
3549 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3555 netdev_update_features(dev);
3560 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3561 netdev_features_t features)
3563 struct stmmac_priv *priv = netdev_priv(dev);
3565 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3566 features &= ~NETIF_F_RXCSUM;
3568 if (!priv->plat->tx_coe)
3569 features &= ~NETIF_F_CSUM_MASK;
3571 /* Some GMAC devices have a bugged Jumbo frame support that
3572 * needs to have the Tx COE disabled for oversized frames
3573 * (due to limited buffer sizes). In this case we disable
3574 * the TX csum insertion in the TDES and not use SF.
3576 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3577 features &= ~NETIF_F_CSUM_MASK;
3579 /* Disable tso if asked by ethtool */
3580 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3581 if (features & NETIF_F_TSO)
3590 static int stmmac_set_features(struct net_device *netdev,
3591 netdev_features_t features)
3593 struct stmmac_priv *priv = netdev_priv(netdev);
3595 /* Keep the COE Type in case of csum is supporting */
3596 if (features & NETIF_F_RXCSUM)
3597 priv->hw->rx_csum = priv->plat->rx_coe;
3599 priv->hw->rx_csum = 0;
3600 /* No check needed because rx_coe has been set before and it will be
3601 * fixed in case of issue.
3603 priv->hw->mac->rx_ipc(priv->hw);
3609 * stmmac_interrupt - main ISR
3610 * @irq: interrupt number.
3611 * @dev_id: to pass the net device pointer.
3612 * Description: this is the main driver interrupt service routine.
3614 * o DMA service routine (to manage incoming frame reception and transmission
3616 * o Core interrupts to manage: remote wake-up, management counter, LPI
3619 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3621 struct net_device *dev = (struct net_device *)dev_id;
3622 struct stmmac_priv *priv = netdev_priv(dev);
3623 u32 rx_cnt = priv->plat->rx_queues_to_use;
3624 u32 tx_cnt = priv->plat->tx_queues_to_use;
3628 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3631 pm_wakeup_event(priv->device, 0);
3633 if (unlikely(!dev)) {
3634 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3638 /* To handle GMAC own interrupts */
3639 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
3640 int status = priv->hw->mac->host_irq_status(priv->hw,
3643 if (unlikely(status)) {
3644 /* For LPI we need to save the tx status */
3645 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3646 priv->tx_path_in_lpi_mode = true;
3647 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3648 priv->tx_path_in_lpi_mode = false;
3651 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3652 for (queue = 0; queue < queues_count; queue++) {
3653 struct stmmac_rx_queue *rx_q =
3654 &priv->rx_queue[queue];
3657 priv->hw->mac->host_mtl_irq_status(priv->hw,
3660 if (status & CORE_IRQ_MTL_RX_OVERFLOW &&
3661 priv->hw->dma->set_rx_tail_ptr)
3662 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
3668 /* PCS link status */
3669 if (priv->hw->pcs) {
3670 if (priv->xstats.pcs_link)
3671 netif_carrier_on(dev);
3673 netif_carrier_off(dev);
3677 /* To handle DMA interrupts */
3678 stmmac_dma_interrupt(priv);
3683 #ifdef CONFIG_NET_POLL_CONTROLLER
3684 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3685 * to allow network I/O with interrupts disabled.
3687 static void stmmac_poll_controller(struct net_device *dev)
3689 disable_irq(dev->irq);
3690 stmmac_interrupt(dev->irq, dev);
3691 enable_irq(dev->irq);
3696 * stmmac_ioctl - Entry point for the Ioctl
3697 * @dev: Device pointer.
3698 * @rq: An IOCTL specefic structure, that can contain a pointer to
3699 * a proprietary structure used to pass information to the driver.
3700 * @cmd: IOCTL command
3702 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3704 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3706 int ret = -EOPNOTSUPP;
3708 if (!netif_running(dev))
3717 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3720 ret = stmmac_hwtstamp_ioctl(dev, rq);
3729 #ifdef CONFIG_DEBUG_FS
3730 static struct dentry *stmmac_fs_dir;
3732 static void sysfs_display_ring(void *head, int size, int extend_desc,
3733 struct seq_file *seq)
3736 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3737 struct dma_desc *p = (struct dma_desc *)head;
3739 for (i = 0; i < size; i++) {
3741 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3742 i, (unsigned int)virt_to_phys(ep),
3743 le32_to_cpu(ep->basic.des0),
3744 le32_to_cpu(ep->basic.des1),
3745 le32_to_cpu(ep->basic.des2),
3746 le32_to_cpu(ep->basic.des3));
3749 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3750 i, (unsigned int)virt_to_phys(p),
3751 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3752 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3755 seq_printf(seq, "\n");
3759 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
3761 struct net_device *dev = seq->private;
3762 struct stmmac_priv *priv = netdev_priv(dev);
3763 u32 rx_count = priv->plat->rx_queues_to_use;
3764 u32 tx_count = priv->plat->tx_queues_to_use;
3767 for (queue = 0; queue < rx_count; queue++) {
3768 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3770 seq_printf(seq, "RX Queue %d:\n", queue);
3772 if (priv->extend_desc) {
3773 seq_printf(seq, "Extended descriptor ring:\n");
3774 sysfs_display_ring((void *)rx_q->dma_erx,
3775 DMA_RX_SIZE, 1, seq);
3777 seq_printf(seq, "Descriptor ring:\n");
3778 sysfs_display_ring((void *)rx_q->dma_rx,
3779 DMA_RX_SIZE, 0, seq);
3783 for (queue = 0; queue < tx_count; queue++) {
3784 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3786 seq_printf(seq, "TX Queue %d:\n", queue);
3788 if (priv->extend_desc) {
3789 seq_printf(seq, "Extended descriptor ring:\n");
3790 sysfs_display_ring((void *)tx_q->dma_etx,
3791 DMA_TX_SIZE, 1, seq);
3793 seq_printf(seq, "Descriptor ring:\n");
3794 sysfs_display_ring((void *)tx_q->dma_tx,
3795 DMA_TX_SIZE, 0, seq);
3802 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3804 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3807 /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */
3809 static const struct file_operations stmmac_rings_status_fops = {
3810 .owner = THIS_MODULE,
3811 .open = stmmac_sysfs_ring_open,
3813 .llseek = seq_lseek,
3814 .release = single_release,
3817 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3819 struct net_device *dev = seq->private;
3820 struct stmmac_priv *priv = netdev_priv(dev);
3822 if (!priv->hw_cap_support) {
3823 seq_printf(seq, "DMA HW features not supported\n");
3827 seq_printf(seq, "==============================\n");
3828 seq_printf(seq, "\tDMA HW features\n");
3829 seq_printf(seq, "==============================\n");
3831 seq_printf(seq, "\t10/100 Mbps: %s\n",
3832 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3833 seq_printf(seq, "\t1000 Mbps: %s\n",
3834 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3835 seq_printf(seq, "\tHalf duplex: %s\n",
3836 (priv->dma_cap.half_duplex) ? "Y" : "N");
3837 seq_printf(seq, "\tHash Filter: %s\n",
3838 (priv->dma_cap.hash_filter) ? "Y" : "N");
3839 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3840 (priv->dma_cap.multi_addr) ? "Y" : "N");
3841 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3842 (priv->dma_cap.pcs) ? "Y" : "N");
3843 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3844 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3845 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3846 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3847 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3848 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3849 seq_printf(seq, "\tRMON module: %s\n",
3850 (priv->dma_cap.rmon) ? "Y" : "N");
3851 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3852 (priv->dma_cap.time_stamp) ? "Y" : "N");
3853 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3854 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3855 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3856 (priv->dma_cap.eee) ? "Y" : "N");
3857 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3858 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3859 (priv->dma_cap.tx_coe) ? "Y" : "N");
3860 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3861 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3862 (priv->dma_cap.rx_coe) ? "Y" : "N");
3864 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3865 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3866 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3867 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3869 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3870 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3871 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3872 priv->dma_cap.number_rx_channel);
3873 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3874 priv->dma_cap.number_tx_channel);
3875 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3876 (priv->dma_cap.enh_desc) ? "Y" : "N");
3881 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3883 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3886 static const struct file_operations stmmac_dma_cap_fops = {
3887 .owner = THIS_MODULE,
3888 .open = stmmac_sysfs_dma_cap_open,
3890 .llseek = seq_lseek,
3891 .release = single_release,
3894 static int stmmac_init_fs(struct net_device *dev)
3896 struct stmmac_priv *priv = netdev_priv(dev);
3898 /* Create per netdev entries */
3899 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3901 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3902 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3907 /* Entry to report DMA RX/TX rings */
3908 priv->dbgfs_rings_status =
3909 debugfs_create_file("descriptors_status", S_IRUGO,
3910 priv->dbgfs_dir, dev,
3911 &stmmac_rings_status_fops);
3913 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3914 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3915 debugfs_remove_recursive(priv->dbgfs_dir);
3920 /* Entry to report the DMA HW features */
3921 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3923 dev, &stmmac_dma_cap_fops);
3925 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3926 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
3927 debugfs_remove_recursive(priv->dbgfs_dir);
3935 static void stmmac_exit_fs(struct net_device *dev)
3937 struct stmmac_priv *priv = netdev_priv(dev);
3939 debugfs_remove_recursive(priv->dbgfs_dir);
3941 #endif /* CONFIG_DEBUG_FS */
3943 static const struct net_device_ops stmmac_netdev_ops = {
3944 .ndo_open = stmmac_open,
3945 .ndo_start_xmit = stmmac_xmit,
3946 .ndo_stop = stmmac_release,
3947 .ndo_change_mtu = stmmac_change_mtu,
3948 .ndo_fix_features = stmmac_fix_features,
3949 .ndo_set_features = stmmac_set_features,
3950 .ndo_set_rx_mode = stmmac_set_rx_mode,
3951 .ndo_tx_timeout = stmmac_tx_timeout,
3952 .ndo_do_ioctl = stmmac_ioctl,
3953 #ifdef CONFIG_NET_POLL_CONTROLLER
3954 .ndo_poll_controller = stmmac_poll_controller,
3956 .ndo_set_mac_address = eth_mac_addr,
3960 * stmmac_hw_init - Init the MAC device
3961 * @priv: driver private structure
3962 * Description: this function is to configure the MAC device according to
3963 * some platform parameters or the HW capability register. It prepares the
3964 * driver to use either ring or chain modes and to setup either enhanced or
3965 * normal descriptors.
3967 static int stmmac_hw_init(struct stmmac_priv *priv)
3969 struct mac_device_info *mac;
3971 /* Identify the MAC HW device */
3972 if (priv->plat->has_gmac) {
3973 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3974 mac = dwmac1000_setup(priv->ioaddr,
3975 priv->plat->multicast_filter_bins,
3976 priv->plat->unicast_filter_entries,
3977 &priv->synopsys_id);
3978 } else if (priv->plat->has_gmac4) {
3979 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3980 mac = dwmac4_setup(priv->ioaddr,
3981 priv->plat->multicast_filter_bins,
3982 priv->plat->unicast_filter_entries,
3983 &priv->synopsys_id);
3985 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3992 /* To use the chained or ring mode */
3993 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3994 priv->hw->mode = &dwmac4_ring_mode_ops;
3997 priv->hw->mode = &chain_mode_ops;
3998 dev_info(priv->device, "Chain mode enabled\n");
3999 priv->mode = STMMAC_CHAIN_MODE;
4001 priv->hw->mode = &ring_mode_ops;
4002 dev_info(priv->device, "Ring mode enabled\n");
4003 priv->mode = STMMAC_RING_MODE;
4007 /* Get the HW capability (new GMAC newer than 3.50a) */
4008 priv->hw_cap_support = stmmac_get_hw_features(priv);
4009 if (priv->hw_cap_support) {
4010 dev_info(priv->device, "DMA HW capability register supported\n");
4012 /* We can override some gmac/dma configuration fields: e.g.
4013 * enh_desc, tx_coe (e.g. that are passed through the
4014 * platform) with the values from the HW capability
4015 * register (if supported).
4017 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4018 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4019 priv->hw->pmt = priv->plat->pmt;
4021 /* TXCOE doesn't work in thresh DMA mode */
4022 if (priv->plat->force_thresh_dma_mode)
4023 priv->plat->tx_coe = 0;
4025 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4027 /* In case of GMAC4 rx_coe is from HW cap register. */
4028 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4030 if (priv->dma_cap.rx_coe_type2)
4031 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4032 else if (priv->dma_cap.rx_coe_type1)
4033 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4036 dev_info(priv->device, "No HW DMA feature register supported\n");
4039 /* To use alternate (extended), normal or GMAC4 descriptor structures */
4040 if (priv->synopsys_id >= DWMAC_CORE_4_00)
4041 priv->hw->desc = &dwmac4_desc_ops;
4043 stmmac_selec_desc_mode(priv);
4045 if (priv->plat->rx_coe) {
4046 priv->hw->rx_csum = priv->plat->rx_coe;
4047 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4048 if (priv->synopsys_id < DWMAC_CORE_4_00)
4049 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4051 if (priv->plat->tx_coe)
4052 dev_info(priv->device, "TX Checksum insertion supported\n");
4054 if (priv->plat->pmt) {
4055 dev_info(priv->device, "Wake-Up On Lan supported\n");
4056 device_set_wakeup_capable(priv->device, 1);
4059 if (priv->dma_cap.tsoen)
4060 dev_info(priv->device, "TSO supported\n");
4067 * @device: device pointer
4068 * @plat_dat: platform data pointer
4069 * @res: stmmac resource pointer
4070 * Description: this is the main probe function used to
4071 * call the alloc_etherdev, allocate the priv structure.
4073 * returns 0 on success, otherwise errno.
4075 int stmmac_dvr_probe(struct device *device,
4076 struct plat_stmmacenet_data *plat_dat,
4077 struct stmmac_resources *res)
4079 struct net_device *ndev = NULL;
4080 struct stmmac_priv *priv;
4084 ndev = alloc_etherdev_mqs(sizeof(struct stmmac_priv),
4090 SET_NETDEV_DEV(ndev, device);
4092 priv = netdev_priv(ndev);
4093 priv->device = device;
4096 stmmac_set_ethtool_ops(ndev);
4097 priv->pause = pause;
4098 priv->plat = plat_dat;
4099 priv->ioaddr = res->addr;
4100 priv->dev->base_addr = (unsigned long)res->addr;
4102 priv->dev->irq = res->irq;
4103 priv->wol_irq = res->wol_irq;
4104 priv->lpi_irq = res->lpi_irq;
4107 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4109 dev_set_drvdata(device, priv->dev);
4111 /* Verify driver arguments */
4112 stmmac_verify_args();
4114 /* Override with kernel parameters if supplied XXX CRS XXX
4115 * this needs to have multiple instances
4117 if ((phyaddr >= 0) && (phyaddr <= 31))
4118 priv->plat->phy_addr = phyaddr;
4120 if (priv->plat->stmmac_rst)
4121 reset_control_deassert(priv->plat->stmmac_rst);
4123 /* Init MAC and get the capabilities */
4124 ret = stmmac_hw_init(priv);
4128 /* Configure real RX and TX queues */
4129 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4130 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4132 ndev->netdev_ops = &stmmac_netdev_ops;
4134 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4137 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4138 ndev->hw_features |= NETIF_F_TSO;
4140 dev_info(priv->device, "TSO feature enabled\n");
4142 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4143 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4144 #ifdef STMMAC_VLAN_TAG_USED
4145 /* Both mac100 and gmac support receive VLAN tag detection */
4146 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4148 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4150 /* MTU range: 46 - hw-specific max */
4151 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4152 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4153 ndev->max_mtu = JUMBO_LEN;
4155 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4156 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4157 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4159 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4160 (priv->plat->maxmtu >= ndev->min_mtu))
4161 ndev->max_mtu = priv->plat->maxmtu;
4162 else if (priv->plat->maxmtu < ndev->min_mtu)
4163 dev_warn(priv->device,
4164 "%s: warning: maxmtu having invalid value (%d)\n",
4165 __func__, priv->plat->maxmtu);
4168 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4170 /* Rx Watchdog is available in the COREs newer than the 3.40.
4171 * In some case, for example on bugged HW this feature
4172 * has to be disable and this can be done by passing the
4173 * riwt_off field from the platform.
4175 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
4177 dev_info(priv->device,
4178 "Enable RX Mitigation via HW Watchdog Timer\n");
4181 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4182 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4184 netif_napi_add(ndev, &rx_q->napi, stmmac_poll,
4185 (8 * priv->plat->rx_queues_to_use));
4188 spin_lock_init(&priv->lock);
4190 /* If a specific clk_csr value is passed from the platform
4191 * this means that the CSR Clock Range selection cannot be
4192 * changed at run-time and it is fixed. Viceversa the driver'll try to
4193 * set the MDC clock dynamically according to the csr actual
4196 if (!priv->plat->clk_csr)
4197 stmmac_clk_csr_set(priv);
4199 priv->clk_csr = priv->plat->clk_csr;
4201 stmmac_check_pcs_mode(priv);
4203 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4204 priv->hw->pcs != STMMAC_PCS_TBI &&
4205 priv->hw->pcs != STMMAC_PCS_RTBI) {
4206 /* MDIO bus Registration */
4207 ret = stmmac_mdio_register(ndev);
4209 dev_err(priv->device,
4210 "%s: MDIO bus (id: %d) registration failed",
4211 __func__, priv->plat->bus_id);
4212 goto error_mdio_register;
4216 ret = register_netdev(ndev);
4218 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4220 goto error_netdev_register;
4225 error_netdev_register:
4226 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4227 priv->hw->pcs != STMMAC_PCS_TBI &&
4228 priv->hw->pcs != STMMAC_PCS_RTBI)
4229 stmmac_mdio_unregister(ndev);
4230 error_mdio_register:
4231 for (queue = 0; queue < priv->plat->rx_queues_to_use; queue++) {
4232 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4234 netif_napi_del(&rx_q->napi);
4241 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4245 * @dev: device pointer
4246 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4247 * changes the link status, releases the DMA descriptor rings.
4249 int stmmac_dvr_remove(struct device *dev)
4251 struct net_device *ndev = dev_get_drvdata(dev);
4252 struct stmmac_priv *priv = netdev_priv(ndev);
4254 netdev_info(priv->dev, "%s: removing driver", __func__);
4256 stmmac_stop_all_dma(priv);
4258 priv->hw->mac->set_mac(priv->ioaddr, false);
4259 netif_carrier_off(ndev);
4260 unregister_netdev(ndev);
4261 if (priv->plat->stmmac_rst)
4262 reset_control_assert(priv->plat->stmmac_rst);
4263 clk_disable_unprepare(priv->plat->pclk);
4264 clk_disable_unprepare(priv->plat->stmmac_clk);
4265 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4266 priv->hw->pcs != STMMAC_PCS_TBI &&
4267 priv->hw->pcs != STMMAC_PCS_RTBI)
4268 stmmac_mdio_unregister(ndev);
4273 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4276 * stmmac_suspend - suspend callback
4277 * @dev: device pointer
4278 * Description: this is the function to suspend the device and it is called
4279 * by the platform driver to stop the network queue, release the resources,
4280 * program the PMT register (for WoL), clean and release driver resources.
4282 int stmmac_suspend(struct device *dev)
4284 struct net_device *ndev = dev_get_drvdata(dev);
4285 struct stmmac_priv *priv = netdev_priv(ndev);
4286 unsigned long flags;
4288 if (!ndev || !netif_running(ndev))
4292 phy_stop(ndev->phydev);
4294 spin_lock_irqsave(&priv->lock, flags);
4296 netif_device_detach(ndev);
4297 stmmac_stop_all_queues(priv);
4299 stmmac_disable_all_queues(priv);
4301 /* Stop TX/RX DMA */
4302 stmmac_stop_all_dma(priv);
4304 /* Enable Power down mode by programming the PMT regs */
4305 if (device_may_wakeup(priv->device)) {
4306 priv->hw->mac->pmt(priv->hw, priv->wolopts);
4309 priv->hw->mac->set_mac(priv->ioaddr, false);
4310 pinctrl_pm_select_sleep_state(priv->device);
4311 /* Disable clock in case of PWM is off */
4312 clk_disable(priv->plat->pclk);
4313 clk_disable(priv->plat->stmmac_clk);
4315 spin_unlock_irqrestore(&priv->lock, flags);
4318 priv->speed = SPEED_UNKNOWN;
4319 priv->oldduplex = DUPLEX_UNKNOWN;
4322 EXPORT_SYMBOL_GPL(stmmac_suspend);
4325 * stmmac_reset_queues_param - reset queue parameters
4326 * @dev: device pointer
4328 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4330 u32 rx_cnt = priv->plat->rx_queues_to_use;
4331 u32 tx_cnt = priv->plat->tx_queues_to_use;
4334 for (queue = 0; queue < rx_cnt; queue++) {
4335 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4341 for (queue = 0; queue < tx_cnt; queue++) {
4342 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4350 * stmmac_resume - resume callback
4351 * @dev: device pointer
4352 * Description: when resume this function is invoked to setup the DMA and CORE
4353 * in a usable state.
4355 int stmmac_resume(struct device *dev)
4357 struct net_device *ndev = dev_get_drvdata(dev);
4358 struct stmmac_priv *priv = netdev_priv(ndev);
4359 unsigned long flags;
4361 if (!netif_running(ndev))
4364 /* Power Down bit, into the PM register, is cleared
4365 * automatically as soon as a magic packet or a Wake-up frame
4366 * is received. Anyway, it's better to manually clear
4367 * this bit because it can generate problems while resuming
4368 * from another devices (e.g. serial console).
4370 if (device_may_wakeup(priv->device)) {
4371 spin_lock_irqsave(&priv->lock, flags);
4372 priv->hw->mac->pmt(priv->hw, 0);
4373 spin_unlock_irqrestore(&priv->lock, flags);
4376 pinctrl_pm_select_default_state(priv->device);
4377 /* enable the clk previously disabled */
4378 clk_enable(priv->plat->stmmac_clk);
4379 clk_enable(priv->plat->pclk);
4380 /* reset the phy so that it's ready */
4382 stmmac_mdio_reset(priv->mii);
4385 netif_device_attach(ndev);
4387 spin_lock_irqsave(&priv->lock, flags);
4389 stmmac_reset_queues_param(priv);
4391 /* reset private mss value to force mss context settings at
4392 * next tso xmit (only used for gmac4).
4396 stmmac_clear_descriptors(priv);
4398 stmmac_hw_setup(ndev, false);
4399 stmmac_init_tx_coalesce(priv);
4400 stmmac_set_rx_mode(ndev);
4402 stmmac_enable_all_queues(priv);
4404 stmmac_start_all_queues(priv);
4406 spin_unlock_irqrestore(&priv->lock, flags);
4409 phy_start(ndev->phydev);
4413 EXPORT_SYMBOL_GPL(stmmac_resume);
4416 static int __init stmmac_cmdline_opt(char *str)
4422 while ((opt = strsep(&str, ",")) != NULL) {
4423 if (!strncmp(opt, "debug:", 6)) {
4424 if (kstrtoint(opt + 6, 0, &debug))
4426 } else if (!strncmp(opt, "phyaddr:", 8)) {
4427 if (kstrtoint(opt + 8, 0, &phyaddr))
4429 } else if (!strncmp(opt, "buf_sz:", 7)) {
4430 if (kstrtoint(opt + 7, 0, &buf_sz))
4432 } else if (!strncmp(opt, "tc:", 3)) {
4433 if (kstrtoint(opt + 3, 0, &tc))
4435 } else if (!strncmp(opt, "watchdog:", 9)) {
4436 if (kstrtoint(opt + 9, 0, &watchdog))
4438 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4439 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4441 } else if (!strncmp(opt, "pause:", 6)) {
4442 if (kstrtoint(opt + 6, 0, &pause))
4444 } else if (!strncmp(opt, "eee_timer:", 10)) {
4445 if (kstrtoint(opt + 10, 0, &eee_timer))
4447 } else if (!strncmp(opt, "chain_mode:", 11)) {
4448 if (kstrtoint(opt + 11, 0, &chain_mode))
4455 pr_err("%s: ERROR broken module parameter conversion", __func__);
4459 __setup("stmmaceth=", stmmac_cmdline_opt);
4462 static int __init stmmac_init(void)
4464 #ifdef CONFIG_DEBUG_FS
4465 /* Create debugfs main directory if it doesn't exist yet */
4466 if (!stmmac_fs_dir) {
4467 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4469 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4470 pr_err("ERROR %s, debugfs create directory failed\n",
4471 STMMAC_RESOURCE_NAME);
4481 static void __exit stmmac_exit(void)
4483 #ifdef CONFIG_DEBUG_FS
4484 debugfs_remove_recursive(stmmac_fs_dir);
4488 module_init(stmmac_init)
4489 module_exit(stmmac_exit)
4491 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4492 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4493 MODULE_LICENSE("GPL");