drivers/net/phy/dp83640.c

   1 /*
   2  * Driver for the National Semiconductor DP83640 PHYTER
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/ethtool.h>
  24 #include <linux/kernel.h>
  25 #include <linux/list.h>
  26 #include <linux/mii.h>
  27 #include <linux/module.h>
  28 #include <linux/net_tstamp.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/if_vlan.h>
  31 #include <linux/phy.h>
  32 #include <linux/ptp_classify.h>
  33 #include <linux/ptp_clock_kernel.h>
  34
  35 #include "dp83640_reg.h"
  36
  37 #define DP83640_PHY_ID  0x20005ce1
  38 #define PAGESEL         0x13
  39 #define LAYER4          0x02
  40 #define LAYER2          0x01
  41 #define MAX_RXTS        64
  42 #define N_EXT_TS        6
  43 #define N_PER_OUT       7
  44 #define PSF_PTPVER      2
  45 #define PSF_EVNT        0x4000
  46 #define PSF_RX          0x2000
  47 #define PSF_TX          0x1000
  48 #define EXT_EVENT       1
  49 #define CAL_EVENT       7
  50 #define CAL_TRIGGER     7
  51 #define DP83640_N_PINS  12
  52
  53 #define MII_DP83640_MICR 0x11
  54 #define MII_DP83640_MISR 0x12
  55
  56 #define MII_DP83640_MICR_OE 0x1
  57 #define MII_DP83640_MICR_IE 0x2
  58
  59 #define MII_DP83640_MISR_RHF_INT_EN 0x01
  60 #define MII_DP83640_MISR_FHF_INT_EN 0x02
  61 #define MII_DP83640_MISR_ANC_INT_EN 0x04
  62 #define MII_DP83640_MISR_DUP_INT_EN 0x08
  63 #define MII_DP83640_MISR_SPD_INT_EN 0x10
  64 #define MII_DP83640_MISR_LINK_INT_EN 0x20
  65 #define MII_DP83640_MISR_ED_INT_EN 0x40
  66 #define MII_DP83640_MISR_LQ_INT_EN 0x80
  67
  68 /* phyter seems to miss the mark by 16 ns */
  69 #define ADJTIME_FIX     16
  70
  71 #if defined(__BIG_ENDIAN)
  72 #define ENDIAN_FLAG     0
  73 #elif defined(__LITTLE_ENDIAN)
  74 #define ENDIAN_FLAG     PSF_ENDIAN
  75 #endif
  76
  77 struct dp83640_skb_info {
  78         int ptp_type;
  79         unsigned long tmo;
  80 };
  81
  82 struct phy_rxts {
  83         u16 ns_lo;   /* ns[15:0] */
  84         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  85         u16 sec_lo;  /* sec[15:0] */
  86         u16 sec_hi;  /* sec[31:16] */
  87         u16 seqid;   /* sequenceId[15:0] */
  88         u16 msgtype; /* messageType[3:0], hash[11:0] */
  89 };
  90
  91 struct phy_txts {
  92         u16 ns_lo;   /* ns[15:0] */
  93         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  94         u16 sec_lo;  /* sec[15:0] */
  95         u16 sec_hi;  /* sec[31:16] */
  96 };
  97
  98 struct rxts {
  99         struct list_head list;
 100         unsigned long tmo;
 101         u64 ns;
 102         u16 seqid;
 103         u8  msgtype;
 104         u16 hash;
 105 };
 106
 107 struct dp83640_clock;
 108
 109 struct dp83640_private {
 110         struct list_head list;
 111         struct dp83640_clock *clock;
 112         struct phy_device *phydev;
 113         struct work_struct ts_work;
 114         int hwts_tx_en;
 115         int hwts_rx_en;
 116         int layer;
 117         int version;
 118         /* remember state of cfg0 during calibration */
 119         int cfg0;
 120         /* remember the last event time stamp */
 121         struct phy_txts edata;
 122         /* list of rx timestamps */
 123         struct list_head rxts;
 124         struct list_head rxpool;
 125         struct rxts rx_pool_data[MAX_RXTS];
 126         /* protects above three fields from concurrent access */
 127         spinlock_t rx_lock;
 128         /* queues of incoming and outgoing packets */
 129         struct sk_buff_head rx_queue;
 130         struct sk_buff_head tx_queue;
 131 };
 132
 133 struct dp83640_clock {
 134         /* keeps the instance in the 'phyter_clocks' list */
 135         struct list_head list;
 136         /* we create one clock instance per MII bus */
 137         struct mii_bus *bus;
 138         /* protects extended registers from concurrent access */
 139         struct mutex extreg_lock;
 140         /* remembers which page was last selected */
 141         int page;
 142         /* our advertised capabilities */
 143         struct ptp_clock_info caps;
 144         /* protects the three fields below from concurrent access */
 145         struct mutex clock_lock;
 146         /* the one phyter from which we shall read */
 147         struct dp83640_private *chosen;
 148         /* list of the other attached phyters, not chosen */
 149         struct list_head phylist;
 150         /* reference to our PTP hardware clock */
 151         struct ptp_clock *ptp_clock;
 152 };
 153
 154 /* globals */
 155
 156 enum {
 157         CALIBRATE_GPIO,
 158         PEROUT_GPIO,
 159         EXTTS0_GPIO,
 160         EXTTS1_GPIO,
 161         EXTTS2_GPIO,
 162         EXTTS3_GPIO,
 163         EXTTS4_GPIO,
 164         EXTTS5_GPIO,
 165         GPIO_TABLE_SIZE
 166 };
 167
 168 static int chosen_phy = -1;
 169 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
 170         1, 2, 3, 4, 8, 9, 10, 11
 171 };
 172
 173 module_param(chosen_phy, int, 0444);
 174 module_param_array(gpio_tab, ushort, NULL, 0444);
 175
 176 MODULE_PARM_DESC(chosen_phy, \
 177         "The address of the PHY to use for the ancillary clock features");
 178 MODULE_PARM_DESC(gpio_tab, \
 179         "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
 180
 181 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
 182 {
 183         int i, index;
 184
 185         for (i = 0; i < DP83640_N_PINS; i++) {
 186                 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
 187                 pd[i].index = i;
 188         }
 189
 190         for (i = 0; i < GPIO_TABLE_SIZE; i++) {
 191                 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
 192                         pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
 193                         return;
 194                 }
 195         }
 196
 197         index = gpio_tab[CALIBRATE_GPIO] - 1;
 198         pd[index].func = PTP_PF_PHYSYNC;
 199         pd[index].chan = 0;
 200
 201         index = gpio_tab[PEROUT_GPIO] - 1;
 202         pd[index].func = PTP_PF_PEROUT;
 203         pd[index].chan = 0;
 204
 205         for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
 206                 index = gpio_tab[i] - 1;
 207                 pd[index].func = PTP_PF_EXTTS;
 208                 pd[index].chan = i - EXTTS0_GPIO;
 209         }
 210 }
 211
 212 /* a list of clocks and a mutex to protect it */
 213 static LIST_HEAD(phyter_clocks);
 214 static DEFINE_MUTEX(phyter_clocks_lock);
 215
 216 static void rx_timestamp_work(struct work_struct *work);
 217
 218 /* extended register access functions */
 219
 220 #define BROADCAST_ADDR 31
 221
 222 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
 223 {
 224         return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
 225 }
 226
 227 /* Caller must hold extreg_lock. */
 228 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
 229 {
 230         struct dp83640_private *dp83640 = phydev->priv;
 231         int val;
 232
 233         if (dp83640->clock->page != page) {
 234                 broadcast_write(phydev->bus, PAGESEL, page);
 235                 dp83640->clock->page = page;
 236         }
 237         val = phy_read(phydev, regnum);
 238
 239         return val;
 240 }
 241
 242 /* Caller must hold extreg_lock. */
 243 static void ext_write(int broadcast, struct phy_device *phydev,
 244                       int page, u32 regnum, u16 val)
 245 {
 246         struct dp83640_private *dp83640 = phydev->priv;
 247
 248         if (dp83640->clock->page != page) {
 249                 broadcast_write(phydev->bus, PAGESEL, page);
 250                 dp83640->clock->page = page;
 251         }
 252         if (broadcast)
 253                 broadcast_write(phydev->bus, regnum, val);
 254         else
 255                 phy_write(phydev, regnum, val);
 256 }
 257
 258 /* Caller must hold extreg_lock. */
 259 static int tdr_write(int bc, struct phy_device *dev,
 260                      const struct timespec64 *ts, u16 cmd)
 261 {
 262         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0]  */
 263         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);   /* ns[31:16] */
 264         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
 265         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);    /* sec[31:16]*/
 266
 267         ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
 268
 269         return 0;
 270 }
 271
 272 /* convert phy timestamps into driver timestamps */
 273
 274 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
 275 {
 276         u32 sec;
 277
 278         sec = p->sec_lo;
 279         sec |= p->sec_hi << 16;
 280
 281         rxts->ns = p->ns_lo;
 282         rxts->ns |= (p->ns_hi & 0x3fff) << 16;
 283         rxts->ns += ((u64)sec) * 1000000000ULL;
 284         rxts->seqid = p->seqid;
 285         rxts->msgtype = (p->msgtype >> 12) & 0xf;
 286         rxts->hash = p->msgtype & 0x0fff;
 287         rxts->tmo = jiffies + 2;
 288 }
 289
 290 static u64 phy2txts(struct phy_txts *p)
 291 {
 292         u64 ns;
 293         u32 sec;
 294
 295         sec = p->sec_lo;
 296         sec |= p->sec_hi << 16;
 297
 298         ns = p->ns_lo;
 299         ns |= (p->ns_hi & 0x3fff) << 16;
 300         ns += ((u64)sec) * 1000000000ULL;
 301
 302         return ns;
 303 }
 304
 305 static int periodic_output(struct dp83640_clock *clock,
 306                            struct ptp_clock_request *clkreq, bool on,
 307                            int trigger)
 308 {
 309         struct dp83640_private *dp83640 = clock->chosen;
 310         struct phy_device *phydev = dp83640->phydev;
 311         u32 sec, nsec, pwidth;
 312         u16 gpio, ptp_trig, val;
 313
 314         if (on) {
 315                 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
 316                                         trigger);
 317                 if (gpio < 1)
 318                         return -EINVAL;
 319         } else {
 320                 gpio = 0;
 321         }
 322
 323         ptp_trig = TRIG_WR |
 324                 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
 325                 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
 326                 TRIG_PER |
 327                 TRIG_PULSE;
 328
 329         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 330
 331         if (!on) {
 332                 val |= TRIG_DIS;
 333                 mutex_lock(&clock->extreg_lock);
 334                 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 335                 ext_write(0, phydev, PAGE4, PTP_CTL, val);
 336                 mutex_unlock(&clock->extreg_lock);
 337                 return 0;
 338         }
 339
 340         sec = clkreq->perout.start.sec;
 341         nsec = clkreq->perout.start.nsec;
 342         pwidth = clkreq->perout.period.sec * 1000000000UL;
 343         pwidth += clkreq->perout.period.nsec;
 344         pwidth /= 2;
 345
 346         mutex_lock(&clock->extreg_lock);
 347
 348         ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 349
 350         /*load trigger*/
 351         val |= TRIG_LOAD;
 352         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 353         ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff);   /* ns[15:0] */
 354         ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16);      /* ns[31:16] */
 355         ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff);    /* sec[15:0] */
 356         ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16);       /* sec[31:16] */
 357         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
 358         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);    /* ns[31:16] */
 359         /* Triggers 0 and 1 has programmable pulsewidth2 */
 360         if (trigger < 2) {
 361                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
 362                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
 363         }
 364
 365         /*enable trigger*/
 366         val &= ~TRIG_LOAD;
 367         val |= TRIG_EN;
 368         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 369
 370         mutex_unlock(&clock->extreg_lock);
 371         return 0;
 372 }
 373
 374 /* ptp clock methods */
 375
 376 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 377 {
 378         struct dp83640_clock *clock =
 379                 container_of(ptp, struct dp83640_clock, caps);
 380         struct phy_device *phydev = clock->chosen->phydev;
 381         u64 rate;
 382         int neg_adj = 0;
 383         u16 hi, lo;
 384
 385         if (ppb < 0) {
 386                 neg_adj = 1;
 387                 ppb = -ppb;
 388         }
 389         rate = ppb;
 390         rate <<= 26;
 391         rate = div_u64(rate, 1953125);
 392
 393         hi = (rate >> 16) & PTP_RATE_HI_MASK;
 394         if (neg_adj)
 395                 hi |= PTP_RATE_DIR;
 396
 397         lo = rate & 0xffff;
 398
 399         mutex_lock(&clock->extreg_lock);
 400
 401         ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
 402         ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
 403
 404         mutex_unlock(&clock->extreg_lock);
 405
 406         return 0;
 407 }
 408
 409 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
 410 {
 411         struct dp83640_clock *clock =
 412                 container_of(ptp, struct dp83640_clock, caps);
 413         struct phy_device *phydev = clock->chosen->phydev;
 414         struct timespec64 ts;
 415         int err;
 416
 417         delta += ADJTIME_FIX;
 418
 419         ts = ns_to_timespec64(delta);
 420
 421         mutex_lock(&clock->extreg_lock);
 422
 423         err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
 424
 425         mutex_unlock(&clock->extreg_lock);
 426
 427         return err;
 428 }
 429
 430 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
 431                                struct timespec64 *ts)
 432 {
 433         struct dp83640_clock *clock =
 434                 container_of(ptp, struct dp83640_clock, caps);
 435         struct phy_device *phydev = clock->chosen->phydev;
 436         unsigned int val[4];
 437
 438         mutex_lock(&clock->extreg_lock);
 439
 440         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
 441
 442         val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
 443         val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
 444         val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
 445         val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
 446
 447         mutex_unlock(&clock->extreg_lock);
 448
 449         ts->tv_nsec = val[0] | (val[1] << 16);
 450         ts->tv_sec  = val[2] | (val[3] << 16);
 451
 452         return 0;
 453 }
 454
 455 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
 456                                const struct timespec64 *ts)
 457 {
 458         struct dp83640_clock *clock =
 459                 container_of(ptp, struct dp83640_clock, caps);
 460         struct phy_device *phydev = clock->chosen->phydev;
 461         int err;
 462
 463         mutex_lock(&clock->extreg_lock);
 464
 465         err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
 466
 467         mutex_unlock(&clock->extreg_lock);
 468
 469         return err;
 470 }
 471
 472 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
 473                               struct ptp_clock_request *rq, int on)
 474 {
 475         struct dp83640_clock *clock =
 476                 container_of(ptp, struct dp83640_clock, caps);
 477         struct phy_device *phydev = clock->chosen->phydev;
 478         unsigned int index;
 479         u16 evnt, event_num, gpio_num;
 480
 481         switch (rq->type) {
 482         case PTP_CLK_REQ_EXTTS:
 483                 index = rq->extts.index;
 484                 if (index >= N_EXT_TS)
 485                         return -EINVAL;
 486                 event_num = EXT_EVENT + index;
 487                 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 488                 if (on) {
 489                         gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
 490                                                     PTP_PF_EXTTS, index);
 491                         if (gpio_num < 1)
 492                                 return -EINVAL;
 493                         evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 494                         if (rq->extts.flags & PTP_FALLING_EDGE)
 495                                 evnt |= EVNT_FALL;
 496                         else
 497                                 evnt |= EVNT_RISE;
 498                 }
 499                 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
 500                 return 0;
 501
 502         case PTP_CLK_REQ_PEROUT:
 503                 if (rq->perout.index >= N_PER_OUT)
 504                         return -EINVAL;
 505                 return periodic_output(clock, rq, on, rq->perout.index);
 506
 507         default:
 508                 break;
 509         }
 510
 511         return -EOPNOTSUPP;
 512 }
 513
 514 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
 515                               enum ptp_pin_function func, unsigned int chan)
 516 {
 517         struct dp83640_clock *clock =
 518                 container_of(ptp, struct dp83640_clock, caps);
 519
 520         if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
 521             !list_empty(&clock->phylist))
 522                 return 1;
 523
 524         if (func == PTP_PF_PHYSYNC)
 525                 return 1;
 526
 527         return 0;
 528 }
 529
 530 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
 531 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
 532
 533 static void enable_status_frames(struct phy_device *phydev, bool on)
 534 {
 535         u16 cfg0 = 0, ver;
 536
 537         if (on)
 538                 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
 539
 540         ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
 541
 542         ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
 543         ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
 544
 545         if (!phydev->attached_dev) {
 546                 pr_warn("expected to find an attached netdevice\n");
 547                 return;
 548         }
 549
 550         if (on) {
 551                 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
 552                         pr_warn("failed to add mc address\n");
 553         } else {
 554                 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
 555                         pr_warn("failed to delete mc address\n");
 556         }
 557 }
 558
 559 static bool is_status_frame(struct sk_buff *skb, int type)
 560 {
 561         struct ethhdr *h = eth_hdr(skb);
 562
 563         if (PTP_CLASS_V2_L2 == type &&
 564             !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
 565                 return true;
 566         else
 567                 return false;
 568 }
 569
 570 static int expired(struct rxts *rxts)
 571 {
 572         return time_after(jiffies, rxts->tmo);
 573 }
 574
 575 /* Caller must hold rx_lock. */
 576 static void prune_rx_ts(struct dp83640_private *dp83640)
 577 {
 578         struct list_head *this, *next;
 579         struct rxts *rxts;
 580
 581         list_for_each_safe(this, next, &dp83640->rxts) {
 582                 rxts = list_entry(this, struct rxts, list);
 583                 if (expired(rxts)) {
 584                         list_del_init(&rxts->list);
 585                         list_add(&rxts->list, &dp83640->rxpool);
 586                 }
 587         }
 588 }
 589
 590 /* synchronize the phyters so they act as one clock */
 591
 592 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
 593 {
 594         int val;
 595         phy_write(phydev, PAGESEL, 0);
 596         val = phy_read(phydev, PHYCR2);
 597         if (on)
 598                 val |= BC_WRITE;
 599         else
 600                 val &= ~BC_WRITE;
 601         phy_write(phydev, PHYCR2, val);
 602         phy_write(phydev, PAGESEL, init_page);
 603 }
 604
 605 static void recalibrate(struct dp83640_clock *clock)
 606 {
 607         s64 now, diff;
 608         struct phy_txts event_ts;
 609         struct timespec64 ts;
 610         struct list_head *this;
 611         struct dp83640_private *tmp;
 612         struct phy_device *master = clock->chosen->phydev;
 613         u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
 614
 615         trigger = CAL_TRIGGER;
 616         cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
 617         if (cal_gpio < 1) {
 618                 pr_err("PHY calibration pin not available - PHY is not calibrated.");
 619                 return;
 620         }
 621
 622         mutex_lock(&clock->extreg_lock);
 623
 624         /*
 625          * enable broadcast, disable status frames, enable ptp clock
 626          */
 627         list_for_each(this, &clock->phylist) {
 628                 tmp = list_entry(this, struct dp83640_private, list);
 629                 enable_broadcast(tmp->phydev, clock->page, 1);
 630                 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
 631                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
 632                 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
 633         }
 634         enable_broadcast(master, clock->page, 1);
 635         cfg0 = ext_read(master, PAGE5, PSF_CFG0);
 636         ext_write(0, master, PAGE5, PSF_CFG0, 0);
 637         ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
 638
 639         /*
 640          * enable an event timestamp
 641          */
 642         evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
 643         evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 644         evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 645
 646         list_for_each(this, &clock->phylist) {
 647                 tmp = list_entry(this, struct dp83640_private, list);
 648                 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
 649         }
 650         ext_write(0, master, PAGE5, PTP_EVNT, evnt);
 651
 652         /*
 653          * configure a trigger
 654          */
 655         ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
 656         ptp_trig |= (trigger  & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
 657         ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
 658         ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
 659
 660         /* load trigger */
 661         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 662         val |= TRIG_LOAD;
 663         ext_write(0, master, PAGE4, PTP_CTL, val);
 664
 665         /* enable trigger */
 666         val &= ~TRIG_LOAD;
 667         val |= TRIG_EN;
 668         ext_write(0, master, PAGE4, PTP_CTL, val);
 669
 670         /* disable trigger */
 671         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 672         val |= TRIG_DIS;
 673         ext_write(0, master, PAGE4, PTP_CTL, val);
 674
 675         /*
 676          * read out and correct offsets
 677          */
 678         val = ext_read(master, PAGE4, PTP_STS);
 679         pr_info("master PTP_STS  0x%04hx\n", val);
 680         val = ext_read(master, PAGE4, PTP_ESTS);
 681         pr_info("master PTP_ESTS 0x%04hx\n", val);
 682         event_ts.ns_lo  = ext_read(master, PAGE4, PTP_EDATA);
 683         event_ts.ns_hi  = ext_read(master, PAGE4, PTP_EDATA);
 684         event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
 685         event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
 686         now = phy2txts(&event_ts);
 687
 688         list_for_each(this, &clock->phylist) {
 689                 tmp = list_entry(this, struct dp83640_private, list);
 690                 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
 691                 pr_info("slave  PTP_STS  0x%04hx\n", val);
 692                 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
 693                 pr_info("slave  PTP_ESTS 0x%04hx\n", val);
 694                 event_ts.ns_lo  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 695                 event_ts.ns_hi  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 696                 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 697                 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 698                 diff = now - (s64) phy2txts(&event_ts);
 699                 pr_info("slave offset %lld nanoseconds\n", diff);
 700                 diff += ADJTIME_FIX;
 701                 ts = ns_to_timespec64(diff);
 702                 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
 703         }
 704
 705         /*
 706          * restore status frames
 707          */
 708         list_for_each(this, &clock->phylist) {
 709                 tmp = list_entry(this, struct dp83640_private, list);
 710                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
 711         }
 712         ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
 713
 714         mutex_unlock(&clock->extreg_lock);
 715 }
 716
 717 /* time stamping methods */
 718
 719 static inline u16 exts_chan_to_edata(int ch)
 720 {
 721         return 1 << ((ch + EXT_EVENT) * 2);
 722 }
 723
 724 static int decode_evnt(struct dp83640_private *dp83640,
 725                        void *data, int len, u16 ests)
 726 {
 727         struct phy_txts *phy_txts;
 728         struct ptp_clock_event event;
 729         int i, parsed;
 730         int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
 731         u16 ext_status = 0;
 732
 733         /* calculate length of the event timestamp status message */
 734         if (ests & MULT_EVNT)
 735                 parsed = (words + 2) * sizeof(u16);
 736         else
 737                 parsed = (words + 1) * sizeof(u16);
 738
 739         /* check if enough data is available */
 740         if (len < parsed)
 741                 return len;
 742
 743         if (ests & MULT_EVNT) {
 744                 ext_status = *(u16 *) data;
 745                 data += sizeof(ext_status);
 746         }
 747
 748         phy_txts = data;
 749
 750         switch (words) { /* fall through in every case */
 751         case 3:
 752                 dp83640->edata.sec_hi = phy_txts->sec_hi;
 753         case 2:
 754                 dp83640->edata.sec_lo = phy_txts->sec_lo;
 755         case 1:
 756                 dp83640->edata.ns_hi = phy_txts->ns_hi;
 757         case 0:
 758                 dp83640->edata.ns_lo = phy_txts->ns_lo;
 759         }
 760
 761         if (!ext_status) {
 762                 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
 763                 ext_status = exts_chan_to_edata(i);
 764         }
 765
 766         event.type = PTP_CLOCK_EXTTS;
 767         event.timestamp = phy2txts(&dp83640->edata);
 768
 769         /* Compensate for input path and synchronization delays */
 770         event.timestamp -= 35;
 771
 772         for (i = 0; i < N_EXT_TS; i++) {
 773                 if (ext_status & exts_chan_to_edata(i)) {
 774                         event.index = i;
 775                         ptp_clock_event(dp83640->clock->ptp_clock, &event);
 776                 }
 777         }
 778
 779         return parsed;
 780 }
 781
 782 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
 783 {
 784         u16 *seqid;
 785         unsigned int offset = 0;
 786         u8 *msgtype, *data = skb_mac_header(skb);
 787
 788         /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
 789
 790         if (type & PTP_CLASS_VLAN)
 791                 offset += VLAN_HLEN;
 792
 793         switch (type & PTP_CLASS_PMASK) {
 794         case PTP_CLASS_IPV4:
 795                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 796                 break;
 797         case PTP_CLASS_IPV6:
 798                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 799                 break;
 800         case PTP_CLASS_L2:
 801                 offset += ETH_HLEN;
 802                 break;
 803         default:
 804                 return 0;
 805         }
 806
 807         if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
 808                 return 0;
 809
 810         if (unlikely(type & PTP_CLASS_V1))
 811                 msgtype = data + offset + OFF_PTP_CONTROL;
 812         else
 813                 msgtype = data + offset;
 814
 815         seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 816
 817         return rxts->msgtype == (*msgtype & 0xf) &&
 818                 rxts->seqid   == ntohs(*seqid);
 819 }
 820
 821 static void decode_rxts(struct dp83640_private *dp83640,
 822                         struct phy_rxts *phy_rxts)
 823 {
 824         struct rxts *rxts;
 825         struct skb_shared_hwtstamps *shhwtstamps = NULL;
 826         struct sk_buff *skb;
 827         unsigned long flags;
 828
 829         spin_lock_irqsave(&dp83640->rx_lock, flags);
 830
 831         prune_rx_ts(dp83640);
 832
 833         if (list_empty(&dp83640->rxpool)) {
 834                 pr_debug("rx timestamp pool is empty\n");
 835                 goto out;
 836         }
 837         rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
 838         list_del_init(&rxts->list);
 839         phy2rxts(phy_rxts, rxts);
 840
 841         spin_lock_irqsave(&dp83640->rx_queue.lock, flags);
 842         skb_queue_walk(&dp83640->rx_queue, skb) {
 843                 struct dp83640_skb_info *skb_info;
 844
 845                 skb_info = (struct dp83640_skb_info *)skb->cb;
 846                 if (match(skb, skb_info->ptp_type, rxts)) {
 847                         __skb_unlink(skb, &dp83640->rx_queue);
 848                         shhwtstamps = skb_hwtstamps(skb);
 849                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 850                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
 851                         netif_rx_ni(skb);
 852                         list_add(&rxts->list, &dp83640->rxpool);
 853                         break;
 854                 }
 855         }
 856         spin_unlock_irqrestore(&dp83640->rx_queue.lock, flags);
 857
 858         if (!shhwtstamps)
 859                 list_add_tail(&rxts->list, &dp83640->rxts);
 860 out:
 861         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
 862 }
 863
 864 static void decode_txts(struct dp83640_private *dp83640,
 865                         struct phy_txts *phy_txts)
 866 {
 867         struct skb_shared_hwtstamps shhwtstamps;
 868         struct sk_buff *skb;
 869         u64 ns;
 870
 871         /* We must already have the skb that triggered this. */
 872
 873         skb = skb_dequeue(&dp83640->tx_queue);
 874
 875         if (!skb) {
 876                 pr_debug("have timestamp but tx_queue empty\n");
 877                 return;
 878         }
 879         ns = phy2txts(phy_txts);
 880         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 881         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 882         skb_complete_tx_timestamp(skb, &shhwtstamps);
 883 }
 884
 885 static void decode_status_frame(struct dp83640_private *dp83640,
 886                                 struct sk_buff *skb)
 887 {
 888         struct phy_rxts *phy_rxts;
 889         struct phy_txts *phy_txts;
 890         u8 *ptr;
 891         int len, size;
 892         u16 ests, type;
 893
 894         ptr = skb->data + 2;
 895
 896         for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
 897
 898                 type = *(u16 *)ptr;
 899                 ests = type & 0x0fff;
 900                 type = type & 0xf000;
 901                 len -= sizeof(type);
 902                 ptr += sizeof(type);
 903
 904                 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
 905
 906                         phy_rxts = (struct phy_rxts *) ptr;
 907                         decode_rxts(dp83640, phy_rxts);
 908                         size = sizeof(*phy_rxts);
 909
 910                 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
 911
 912                         phy_txts = (struct phy_txts *) ptr;
 913                         decode_txts(dp83640, phy_txts);
 914                         size = sizeof(*phy_txts);
 915
 916                 } else if (PSF_EVNT == type) {
 917
 918                         size = decode_evnt(dp83640, ptr, len, ests);
 919
 920                 } else {
 921                         size = 0;
 922                         break;
 923                 }
 924                 ptr += size;
 925         }
 926 }
 927
 928 static int is_sync(struct sk_buff *skb, int type)
 929 {
 930         u8 *data = skb->data, *msgtype;
 931         unsigned int offset = 0;
 932
 933         if (type & PTP_CLASS_VLAN)
 934                 offset += VLAN_HLEN;
 935
 936         switch (type & PTP_CLASS_PMASK) {
 937         case PTP_CLASS_IPV4:
 938                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 939                 break;
 940         case PTP_CLASS_IPV6:
 941                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 942                 break;
 943         case PTP_CLASS_L2:
 944                 offset += ETH_HLEN;
 945                 break;
 946         default:
 947                 return 0;
 948         }
 949
 950         if (type & PTP_CLASS_V1)
 951                 offset += OFF_PTP_CONTROL;
 952
 953         if (skb->len < offset + 1)
 954                 return 0;
 955
 956         msgtype = data + offset;
 957
 958         return (*msgtype & 0xf) == 0;
 959 }
 960
 961 static void dp83640_free_clocks(void)
 962 {
 963         struct dp83640_clock *clock;
 964         struct list_head *this, *next;
 965
 966         mutex_lock(&phyter_clocks_lock);
 967
 968         list_for_each_safe(this, next, &phyter_clocks) {
 969                 clock = list_entry(this, struct dp83640_clock, list);
 970                 if (!list_empty(&clock->phylist)) {
 971                         pr_warn("phy list non-empty while unloading\n");
 972                         BUG();
 973                 }
 974                 list_del(&clock->list);
 975                 mutex_destroy(&clock->extreg_lock);
 976                 mutex_destroy(&clock->clock_lock);
 977                 put_device(&clock->bus->dev);
 978                 kfree(clock->caps.pin_config);
 979                 kfree(clock);
 980         }
 981
 982         mutex_unlock(&phyter_clocks_lock);
 983 }
 984
 985 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
 986 {
 987         INIT_LIST_HEAD(&clock->list);
 988         clock->bus = bus;
 989         mutex_init(&clock->extreg_lock);
 990         mutex_init(&clock->clock_lock);
 991         INIT_LIST_HEAD(&clock->phylist);
 992         clock->caps.owner = THIS_MODULE;
 993         sprintf(clock->caps.name, "dp83640 timer");
 994         clock->caps.max_adj     = 1953124;
 995         clock->caps.n_alarm     = 0;
 996         clock->caps.n_ext_ts    = N_EXT_TS;
 997         clock->caps.n_per_out   = N_PER_OUT;
 998         clock->caps.n_pins      = DP83640_N_PINS;
 999         clock->caps.pps         = 0;
1000         clock->caps.adjfreq     = ptp_dp83640_adjfreq;
1001         clock->caps.adjtime     = ptp_dp83640_adjtime;
1002         clock->caps.gettime64   = ptp_dp83640_gettime;
1003         clock->caps.settime64   = ptp_dp83640_settime;
1004         clock->caps.enable      = ptp_dp83640_enable;
1005         clock->caps.verify      = ptp_dp83640_verify;
1006         /*
1007          * Convert the module param defaults into a dynamic pin configuration.
1008          */
1009         dp83640_gpio_defaults(clock->caps.pin_config);
1010         /*
1011          * Get a reference to this bus instance.
1012          */
1013         get_device(&bus->dev);
1014 }
1015
1016 static int choose_this_phy(struct dp83640_clock *clock,
1017                            struct phy_device *phydev)
1018 {
1019         if (chosen_phy == -1 && !clock->chosen)
1020                 return 1;
1021
1022         if (chosen_phy == phydev->addr)
1023                 return 1;
1024
1025         return 0;
1026 }
1027
1028 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1029 {
1030         if (clock)
1031                 mutex_lock(&clock->clock_lock);
1032         return clock;
1033 }
1034
1035 /*
1036  * Look up and lock a clock by bus instance.
1037  * If there is no clock for this bus, then create it first.
1038  */
1039 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1040 {
1041         struct dp83640_clock *clock = NULL, *tmp;
1042         struct list_head *this;
1043
1044         mutex_lock(&phyter_clocks_lock);
1045
1046         list_for_each(this, &phyter_clocks) {
1047                 tmp = list_entry(this, struct dp83640_clock, list);
1048                 if (tmp->bus == bus) {
1049                         clock = tmp;
1050                         break;
1051                 }
1052         }
1053         if (clock)
1054                 goto out;
1055
1056         clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1057         if (!clock)
1058                 goto out;
1059
1060         clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1061                                          DP83640_N_PINS, GFP_KERNEL);
1062         if (!clock->caps.pin_config) {
1063                 kfree(clock);
1064                 clock = NULL;
1065                 goto out;
1066         }
1067         dp83640_clock_init(clock, bus);
1068         list_add_tail(&phyter_clocks, &clock->list);
1069 out:
1070         mutex_unlock(&phyter_clocks_lock);
1071
1072         return dp83640_clock_get(clock);
1073 }
1074
1075 static void dp83640_clock_put(struct dp83640_clock *clock)
1076 {
1077         mutex_unlock(&clock->clock_lock);
1078 }
1079
1080 static int dp83640_probe(struct phy_device *phydev)
1081 {
1082         struct dp83640_clock *clock;
1083         struct dp83640_private *dp83640;
1084         int err = -ENOMEM, i;
1085
1086         if (phydev->addr == BROADCAST_ADDR)
1087                 return 0;
1088
1089         clock = dp83640_clock_get_bus(phydev->bus);
1090         if (!clock)
1091                 goto no_clock;
1092
1093         dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1094         if (!dp83640)
1095                 goto no_memory;
1096
1097         dp83640->phydev = phydev;
1098         INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
1099
1100         INIT_LIST_HEAD(&dp83640->rxts);
1101         INIT_LIST_HEAD(&dp83640->rxpool);
1102         for (i = 0; i < MAX_RXTS; i++)
1103                 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1104
1105         phydev->priv = dp83640;
1106
1107         spin_lock_init(&dp83640->rx_lock);
1108         skb_queue_head_init(&dp83640->rx_queue);
1109         skb_queue_head_init(&dp83640->tx_queue);
1110
1111         dp83640->clock = clock;
1112
1113         if (choose_this_phy(clock, phydev)) {
1114                 clock->chosen = dp83640;
1115                 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
1116                 if (IS_ERR(clock->ptp_clock)) {
1117                         err = PTR_ERR(clock->ptp_clock);
1118                         goto no_register;
1119                 }
1120         } else
1121                 list_add_tail(&dp83640->list, &clock->phylist);
1122
1123         dp83640_clock_put(clock);
1124         return 0;
1125
1126 no_register:
1127         clock->chosen = NULL;
1128         kfree(dp83640);
1129 no_memory:
1130         dp83640_clock_put(clock);
1131 no_clock:
1132         return err;
1133 }
1134
1135 static void dp83640_remove(struct phy_device *phydev)
1136 {
1137         struct dp83640_clock *clock;
1138         struct list_head *this, *next;
1139         struct dp83640_private *tmp, *dp83640 = phydev->priv;
1140
1141         if (phydev->addr == BROADCAST_ADDR)
1142                 return;
1143
1144         enable_status_frames(phydev, false);
1145         cancel_work_sync(&dp83640->ts_work);
1146
1147         skb_queue_purge(&dp83640->rx_queue);
1148         skb_queue_purge(&dp83640->tx_queue);
1149
1150         clock = dp83640_clock_get(dp83640->clock);
1151
1152         if (dp83640 == clock->chosen) {
1153                 ptp_clock_unregister(clock->ptp_clock);
1154                 clock->chosen = NULL;
1155         } else {
1156                 list_for_each_safe(this, next, &clock->phylist) {
1157                         tmp = list_entry(this, struct dp83640_private, list);
1158                         if (tmp == dp83640) {
1159                                 list_del_init(&tmp->list);
1160                                 break;
1161                         }
1162                 }
1163         }
1164
1165         dp83640_clock_put(clock);
1166         kfree(dp83640);
1167 }
1168
1169 static int dp83640_config_init(struct phy_device *phydev)
1170 {
1171         struct dp83640_private *dp83640 = phydev->priv;
1172         struct dp83640_clock *clock = dp83640->clock;
1173
1174         if (clock->chosen && !list_empty(&clock->phylist))
1175                 recalibrate(clock);
1176         else
1177                 enable_broadcast(phydev, clock->page, 1);
1178
1179         enable_status_frames(phydev, true);
1180         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1181         return 0;
1182 }
1183
1184 static int dp83640_ack_interrupt(struct phy_device *phydev)
1185 {
1186         int err = phy_read(phydev, MII_DP83640_MISR);
1187
1188         if (err < 0)
1189                 return err;
1190
1191         return 0;
1192 }
1193
1194 static int dp83640_config_intr(struct phy_device *phydev)
1195 {
1196         int micr;
1197         int misr;
1198         int err;
1199
1200         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1201                 misr = phy_read(phydev, MII_DP83640_MISR);
1202                 if (misr < 0)
1203                         return misr;
1204                 misr |=
1205                         (MII_DP83640_MISR_ANC_INT_EN |
1206                         MII_DP83640_MISR_DUP_INT_EN |
1207                         MII_DP83640_MISR_SPD_INT_EN |
1208                         MII_DP83640_MISR_LINK_INT_EN);
1209                 err = phy_write(phydev, MII_DP83640_MISR, misr);
1210                 if (err < 0)
1211                         return err;
1212
1213                 micr = phy_read(phydev, MII_DP83640_MICR);
1214                 if (micr < 0)
1215                         return micr;
1216                 micr |=
1217                         (MII_DP83640_MICR_OE |
1218                         MII_DP83640_MICR_IE);
1219                 return phy_write(phydev, MII_DP83640_MICR, micr);
1220         } else {
1221                 micr = phy_read(phydev, MII_DP83640_MICR);
1222                 if (micr < 0)
1223                         return micr;
1224                 micr &=
1225                         ~(MII_DP83640_MICR_OE |
1226                         MII_DP83640_MICR_IE);
1227                 err = phy_write(phydev, MII_DP83640_MICR, micr);
1228                 if (err < 0)
1229                         return err;
1230
1231                 misr = phy_read(phydev, MII_DP83640_MISR);
1232                 if (misr < 0)
1233                         return misr;
1234                 misr &=
1235                         ~(MII_DP83640_MISR_ANC_INT_EN |
1236                         MII_DP83640_MISR_DUP_INT_EN |
1237                         MII_DP83640_MISR_SPD_INT_EN |
1238                         MII_DP83640_MISR_LINK_INT_EN);
1239                 return phy_write(phydev, MII_DP83640_MISR, misr);
1240         }
1241 }
1242
1243 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1244 {
1245         struct dp83640_private *dp83640 = phydev->priv;
1246         struct hwtstamp_config cfg;
1247         u16 txcfg0, rxcfg0;
1248
1249         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1250                 return -EFAULT;
1251
1252         if (cfg.flags) /* reserved for future extensions */
1253                 return -EINVAL;
1254
1255         if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1256                 return -ERANGE;
1257
1258         dp83640->hwts_tx_en = cfg.tx_type;
1259
1260         switch (cfg.rx_filter) {
1261         case HWTSTAMP_FILTER_NONE:
1262                 dp83640->hwts_rx_en = 0;
1263                 dp83640->layer = 0;
1264                 dp83640->version = 0;
1265                 break;
1266         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1267         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1268         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1269                 dp83640->hwts_rx_en = 1;
1270                 dp83640->layer = LAYER4;
1271                 dp83640->version = 1;
1272                 break;
1273         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1274         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1275         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1276                 dp83640->hwts_rx_en = 1;
1277                 dp83640->layer = LAYER4;
1278                 dp83640->version = 2;
1279                 break;
1280         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1281         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1282         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1283                 dp83640->hwts_rx_en = 1;
1284                 dp83640->layer = LAYER2;
1285                 dp83640->version = 2;
1286                 break;
1287         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1288         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1289         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1290                 dp83640->hwts_rx_en = 1;
1291                 dp83640->layer = LAYER4|LAYER2;
1292                 dp83640->version = 2;
1293                 break;
1294         default:
1295                 return -ERANGE;
1296         }
1297
1298         txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1299         rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1300
1301         if (dp83640->layer & LAYER2) {
1302                 txcfg0 |= TX_L2_EN;
1303                 rxcfg0 |= RX_L2_EN;
1304         }
1305         if (dp83640->layer & LAYER4) {
1306                 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1307                 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1308         }
1309
1310         if (dp83640->hwts_tx_en)
1311                 txcfg0 |= TX_TS_EN;
1312
1313         if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1314                 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1315
1316         if (dp83640->hwts_rx_en)
1317                 rxcfg0 |= RX_TS_EN;
1318
1319         mutex_lock(&dp83640->clock->extreg_lock);
1320
1321         ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1322         ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1323
1324         mutex_unlock(&dp83640->clock->extreg_lock);
1325
1326         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1327 }
1328
1329 static void rx_timestamp_work(struct work_struct *work)
1330 {
1331         struct dp83640_private *dp83640 =
1332                 container_of(work, struct dp83640_private, ts_work);
1333         struct sk_buff *skb;
1334
1335         /* Deliver expired packets. */
1336         while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1337                 struct dp83640_skb_info *skb_info;
1338
1339                 skb_info = (struct dp83640_skb_info *)skb->cb;
1340                 if (!time_after(jiffies, skb_info->tmo)) {
1341                         skb_queue_head(&dp83640->rx_queue, skb);
1342                         break;
1343                 }
1344
1345                 netif_rx_ni(skb);
1346         }
1347
1348         if (!skb_queue_empty(&dp83640->rx_queue))
1349                 schedule_work(&dp83640->ts_work);
1350 }
1351
1352 static bool dp83640_rxtstamp(struct phy_device *phydev,
1353                              struct sk_buff *skb, int type)
1354 {
1355         struct dp83640_private *dp83640 = phydev->priv;
1356         struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1357         struct list_head *this, *next;
1358         struct rxts *rxts;
1359         struct skb_shared_hwtstamps *shhwtstamps = NULL;
1360         unsigned long flags;
1361
1362         if (is_status_frame(skb, type)) {
1363                 decode_status_frame(dp83640, skb);
1364                 kfree_skb(skb);
1365                 return true;
1366         }
1367
1368         if (!dp83640->hwts_rx_en)
1369                 return false;
1370
1371         spin_lock_irqsave(&dp83640->rx_lock, flags);
1372         list_for_each_safe(this, next, &dp83640->rxts) {
1373                 rxts = list_entry(this, struct rxts, list);
1374                 if (match(skb, type, rxts)) {
1375                         shhwtstamps = skb_hwtstamps(skb);
1376                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1377                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1378                         netif_rx_ni(skb);
1379                         list_del_init(&rxts->list);
1380                         list_add(&rxts->list, &dp83640->rxpool);
1381                         break;
1382                 }
1383         }
1384         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1385
1386         if (!shhwtstamps) {
1387                 skb_info->ptp_type = type;
1388                 skb_info->tmo = jiffies + 2;
1389                 skb_queue_tail(&dp83640->rx_queue, skb);
1390                 schedule_work(&dp83640->ts_work);
1391         }
1392
1393         return true;
1394 }
1395
1396 static void dp83640_txtstamp(struct phy_device *phydev,
1397                              struct sk_buff *skb, int type)
1398 {
1399         struct dp83640_private *dp83640 = phydev->priv;
1400
1401         switch (dp83640->hwts_tx_en) {
1402
1403         case HWTSTAMP_TX_ONESTEP_SYNC:
1404                 if (is_sync(skb, type)) {
1405                         kfree_skb(skb);
1406                         return;
1407                 }
1408                 /* fall through */
1409         case HWTSTAMP_TX_ON:
1410                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1411                 skb_queue_tail(&dp83640->tx_queue, skb);
1412                 break;
1413
1414         case HWTSTAMP_TX_OFF:
1415         default:
1416                 kfree_skb(skb);
1417                 break;
1418         }
1419 }
1420
1421 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1422 {
1423         struct dp83640_private *dp83640 = dev->priv;
1424
1425         info->so_timestamping =
1426                 SOF_TIMESTAMPING_TX_HARDWARE |
1427                 SOF_TIMESTAMPING_RX_HARDWARE |
1428                 SOF_TIMESTAMPING_RAW_HARDWARE;
1429         info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1430         info->tx_types =
1431                 (1 << HWTSTAMP_TX_OFF) |
1432                 (1 << HWTSTAMP_TX_ON) |
1433                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1434         info->rx_filters =
1435                 (1 << HWTSTAMP_FILTER_NONE) |
1436                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1437                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1438                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1439                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1440                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1441                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1442                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1443                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
1444                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
1445                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1446                 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1447                 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
1448         return 0;
1449 }
1450
1451 static struct phy_driver dp83640_driver = {
1452         .phy_id         = DP83640_PHY_ID,
1453         .phy_id_mask    = 0xfffffff0,
1454         .name           = "NatSemi DP83640",
1455         .features       = PHY_BASIC_FEATURES,
1456         .flags          = PHY_HAS_INTERRUPT,
1457         .probe          = dp83640_probe,
1458         .remove         = dp83640_remove,
1459         .config_init    = dp83640_config_init,
1460         .config_aneg    = genphy_config_aneg,
1461         .read_status    = genphy_read_status,
1462         .ack_interrupt  = dp83640_ack_interrupt,
1463         .config_intr    = dp83640_config_intr,
1464         .ts_info        = dp83640_ts_info,
1465         .hwtstamp       = dp83640_hwtstamp,
1466         .rxtstamp       = dp83640_rxtstamp,
1467         .txtstamp       = dp83640_txtstamp,
1468         .driver         = {.owner = THIS_MODULE,}
1469 };
1470
1471 static int __init dp83640_init(void)
1472 {
1473         return phy_driver_register(&dp83640_driver);
1474 }
1475
1476 static void __exit dp83640_exit(void)
1477 {
1478         dp83640_free_clocks();
1479         phy_driver_unregister(&dp83640_driver);
1480 }
1481
1482 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1483 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1484 MODULE_LICENSE("GPL");
1485
1486 module_init(dp83640_init);
1487 module_exit(dp83640_exit);
1488
1489 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1490         { DP83640_PHY_ID, 0xfffffff0 },
1491         { }
1492 };
1493
1494 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);