drivers/net/wireless/rtlwifi/rtl8188ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44 #include "pwrseqcmd.h"
  45 #include "pwrseq.h"
  46
  47 #define LLT_CONFIG              5
  48
  49 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  50                                       u8 set_bits, u8 clear_bits)
  51 {
  52         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  53         struct rtl_priv *rtlpriv = rtl_priv(hw);
  54
  55         rtlpci->reg_bcn_ctrl_val |= set_bits;
  56         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  57
  58         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  59 }
  60
  61 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
  62 {
  63         struct rtl_priv *rtlpriv = rtl_priv(hw);
  64         u8 tmp1byte;
  65
  66         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  67         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  68         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  69         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  70         tmp1byte &= ~(BIT(0));
  71         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  72 }
  73
  74 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
  75 {
  76         struct rtl_priv *rtlpriv = rtl_priv(hw);
  77         u8 tmp1byte;
  78
  79         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  80         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  81         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  82         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  83         tmp1byte |= BIT(0);
  84         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  85 }
  86
  87 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  88 {
  89         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  90 }
  91
  92 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  93 {
  94         struct rtl_priv *rtlpriv = rtl_priv(hw);
  95         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  96         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  97
  98         while (skb_queue_len(&ring->queue)) {
  99                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
 100                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
 101
 102                 pci_unmap_single(rtlpci->pdev,
 103                                  rtlpriv->cfg->ops->get_desc(
 104                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 105                                  skb->len, PCI_DMA_TODEVICE);
 106                 kfree_skb(skb);
 107                 ring->idx = (ring->idx + 1) % ring->entries;
 108         }
 109 }
 110
 111 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                      u8 rpwm_val, bool need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool schedule_timer = need_turn_off_ckk;
 124
 125         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 126                                       (u8 *)(&support_remote_wake_up));
 127         if (!rtlhal->fw_ready)
 128                 return;
 129         if (!rtlpriv->psc.fw_current_inpsmode)
 130                 return;
 131
 132         while (1) {
 133                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 134                 if (rtlhal->fw_clk_change_in_progress) {
 135                         while (rtlhal->fw_clk_change_in_progress) {
 136                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 137                                 udelay(100);
 138                                 if (++count > 1000)
 139                                         return;
 140                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 141                         }
 142                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 143                 } else {
 144                         rtlhal->fw_clk_change_in_progress = false;
 145                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 146                         break;
 147                 }
 148         }
 149
 150         if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
 151                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 152                                               (u8 *)(&rpwm_val));
 153                 if (FW_PS_IS_ACK(rpwm_val)) {
 154                         isr_regaddr = REG_HISR;
 155                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 156                         while (!(content & IMR_CPWM) && (count < 500)) {
 157                                 udelay(50);
 158                                 count++;
 159                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 160                         }
 161
 162                         if (content & IMR_CPWM) {
 163                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 164                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
 165                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 166                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 167                                          rtlhal->fw_ps_state);
 168                         }
 169                 }
 170
 171                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 172                 rtlhal->fw_clk_change_in_progress = false;
 173                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 if (schedule_timer) {
 175                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 176                                   jiffies + MSECS(10));
 177                 }
 178         } else  {
 179                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 180                 rtlhal->fw_clk_change_in_progress = false;
 181                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 182         }
 183 }
 184
 185 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
 186                                       u8 rpwm_val)
 187 {
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 190         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 191         struct rtl8192_tx_ring *ring;
 192         enum rf_pwrstate rtstate;
 193         bool schedule_timer = false;
 194         u8 queue;
 195
 196         if (!rtlhal->fw_ready)
 197                 return;
 198         if (!rtlpriv->psc.fw_current_inpsmode)
 199                 return;
 200         if (!rtlhal->allow_sw_to_change_hwclc)
 201                 return;
 202         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 203         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 204                 return;
 205
 206         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 207                 ring = &rtlpci->tx_ring[queue];
 208                 if (skb_queue_len(&ring->queue)) {
 209                         schedule_timer = true;
 210                         break;
 211                 }
 212         }
 213
 214         if (schedule_timer) {
 215                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 216                           jiffies + MSECS(10));
 217                 return;
 218         }
 219
 220         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 221             FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
 222                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 223                 if (!rtlhal->fw_clk_change_in_progress) {
 224                         rtlhal->fw_clk_change_in_progress = true;
 225                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 226                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 227                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 228                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 229                                                       (u8 *)(&rpwm_val));
 230                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 231                         rtlhal->fw_clk_change_in_progress = false;
 232                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 233                 } else {
 234                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 235                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 236                                   jiffies + MSECS(10));
 237                 }
 238         }
 239 }
 240
 241 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 242 {
 243         u8 rpwm_val = 0;
 244
 245         rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
 246         _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
 247 }
 248
 249 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 250 {
 251         u8 rpwm_val = 0;
 252
 253         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
 254         _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 255 }
 256
 257 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
 258 {
 259         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 260
 261         _rtl88ee_set_fw_ps_rf_off_low_power(hw);
 262 }
 263
 264 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
 265 {
 266         struct rtl_priv *rtlpriv = rtl_priv(hw);
 267         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 268         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 269         bool fw_current_inps = false;
 270         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 271
 272         if (ppsc->low_power_enable) {
 273                 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
 274                 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
 275                 rtlhal->allow_sw_to_change_hwclc = false;
 276                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 277                                               (u8 *)(&fw_pwrmode));
 278                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 279                                               (u8 *)(&fw_current_inps));
 280         } else {
 281                 rpwm_val = FW_PS_STATE_ALL_ON_88E;      /* RF on */
 282                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 283                                               (u8 *)(&rpwm_val));
 284                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 285                                               (u8 *)(&fw_pwrmode));
 286                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 287                                               (u8 *)(&fw_current_inps));
 288         }
 289 }
 290
 291 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
 292 {
 293         struct rtl_priv *rtlpriv = rtl_priv(hw);
 294         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 295         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 296         bool fw_current_inps = true;
 297         u8 rpwm_val;
 298
 299         if (ppsc->low_power_enable) {
 300                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;      /* RF off */
 301                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 302                                               (u8 *)(&fw_current_inps));
 303                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 304                                               (u8 *)(&ppsc->fwctrl_psmode));
 305                 rtlhal->allow_sw_to_change_hwclc = true;
 306                 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 307         } else {
 308                 rpwm_val = FW_PS_STATE_RF_OFF_88E;      /* RF off */
 309                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 310                                               (u8 *)(&fw_current_inps));
 311                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 312                                               (u8 *)(&ppsc->fwctrl_psmode));
 313                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 314                                               (u8 *)(&rpwm_val));
 315         }
 316 }
 317
 318 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 319 {
 320         struct rtl_priv *rtlpriv = rtl_priv(hw);
 321         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 322         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 323
 324         switch (variable) {
 325         case HW_VAR_RCR:
 326                 *((u32 *)(val)) = rtlpci->receive_config;
 327                 break;
 328         case HW_VAR_RF_STATE:
 329                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 330                 break;
 331         case HW_VAR_FWLPS_RF_ON:{
 332                         enum rf_pwrstate rfstate;
 333                         u32 val_rcr;
 334
 335                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 336                                                       (u8 *)(&rfstate));
 337                         if (rfstate == ERFOFF) {
 338                                 *((bool *)(val)) = true;
 339                         } else {
 340                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 341                                 val_rcr &= 0x00070000;
 342                                 if (val_rcr)
 343                                         *((bool *)(val)) = false;
 344                                 else
 345                                         *((bool *)(val)) = true;
 346                         }
 347                         break;
 348                 }
 349         case HW_VAR_FW_PSMODE_STATUS:
 350                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 351                 break;
 352         case HW_VAR_CORRECT_TSF:{
 353                 u64 tsf;
 354                 u32 *ptsf_low = (u32 *)&tsf;
 355                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 356
 357                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 358                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 359
 360                 *((u64 *)(val)) = tsf;
 361                 break; }
 362         default:
 363                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 364                          "switch case not process %x\n", variable);
 365                 break;
 366         }
 367 }
 368
 369 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 370 {
 371         struct rtl_priv *rtlpriv = rtl_priv(hw);
 372         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 373         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 374         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 375         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 376         u8 idx;
 377
 378         switch (variable) {
 379         case HW_VAR_ETHER_ADDR:
 380                 for (idx = 0; idx < ETH_ALEN; idx++)
 381                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 382                 break;
 383         case HW_VAR_BASIC_RATE:{
 384                 u16 rate_cfg = ((u16 *)val)[0];
 385                 u8 rate_index = 0;
 386                 rate_cfg = rate_cfg & 0x15f;
 387                 rate_cfg |= 0x01;
 388                 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 389                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (rate_cfg >> 8) & 0xff);
 390                 while (rate_cfg > 0x1) {
 391                         rate_cfg = (rate_cfg >> 1);
 392                         rate_index++;
 393                 }
 394                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
 395                 break; }
 396         case HW_VAR_BSSID:
 397                 for (idx = 0; idx < ETH_ALEN; idx++)
 398                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 399                 break;
 400         case HW_VAR_SIFS:
 401                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 402                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 403
 404                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 405                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 406
 407                 if (!mac->ht_enable)
 408                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 409                 else
 410                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 411                                        *((u16 *)val));
 412                 break;
 413         case HW_VAR_SLOT_TIME:{
 414                 u8 e_aci;
 415
 416                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 417                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 418
 419                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 420
 421                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 422                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 423                                                       (u8 *)(&e_aci));
 424                 }
 425                 break; }
 426         case HW_VAR_ACK_PREAMBLE:{
 427                 u8 reg_tmp;
 428                 u8 short_preamble = (bool) (*(u8 *)val);
 429                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 430                 if (short_preamble) {
 431                         reg_tmp |= 0x02;
 432                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 433                 } else {
 434                         reg_tmp |= 0xFD;
 435                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 436                 }
 437                 break; }
 438         case HW_VAR_WPA_CONFIG:
 439                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 440                 break;
 441         case HW_VAR_AMPDU_MIN_SPACE:{
 442                 u8 min_spacing_to_set;
 443                 u8 sec_min_space;
 444
 445                 min_spacing_to_set = *((u8 *)val);
 446                 if (min_spacing_to_set <= 7) {
 447                         sec_min_space = 0;
 448
 449                         if (min_spacing_to_set < sec_min_space)
 450                                 min_spacing_to_set = sec_min_space;
 451
 452                         mac->min_space_cfg = ((mac->min_space_cfg &
 453                                                0xf8) | min_spacing_to_set);
 454
 455                         *val = min_spacing_to_set;
 456
 457                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 458                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 459                                   mac->min_space_cfg);
 460
 461                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 462                                        mac->min_space_cfg);
 463                 }
 464                 break; }
 465         case HW_VAR_SHORTGI_DENSITY:{
 466                 u8 density_to_set;
 467
 468                 density_to_set = *((u8 *)val);
 469                 mac->min_space_cfg |= (density_to_set << 3);
 470
 471                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 472                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 473                           mac->min_space_cfg);
 474
 475                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 476                                mac->min_space_cfg);
 477                 break; }
 478         case HW_VAR_AMPDU_FACTOR:{
 479                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 480                 u8 factor;
 481                 u8 *reg = NULL;
 482                 u8 id = 0;
 483
 484                 reg = regtoset_normal;
 485
 486                 factor = *((u8 *)val);
 487                 if (factor <= 3) {
 488                         factor = (1 << (factor + 2));
 489                         if (factor > 0xf)
 490                                 factor = 0xf;
 491
 492                         for (id = 0; id < 4; id++) {
 493                                 if ((reg[id] & 0xf0) > (factor << 4))
 494                                         reg[id] = (reg[id] & 0x0f) |
 495                                                   (factor << 4);
 496
 497                                 if ((reg[id] & 0x0f) > factor)
 498                                         reg[id] = (reg[id] & 0xf0) | (factor);
 499
 500                                 rtl_write_byte(rtlpriv, (REG_AGGLEN_LMT + id),
 501                                                reg[id]);
 502                         }
 503
 504                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 505                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n", factor);
 506                 }
 507                 break; }
 508         case HW_VAR_AC_PARAM:{
 509                 u8 e_aci = *((u8 *)val);
 510                 rtl88e_dm_init_edca_turbo(hw);
 511
 512                 if (rtlpci->acm_method != eAcmWay2_SW)
 513                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 514                                                       (u8 *)(&e_aci));
 515                 break; }
 516         case HW_VAR_ACM_CTRL:{
 517                 u8 e_aci = *((u8 *)val);
 518                 union aci_aifsn *p_aci_aifsn =
 519                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 520                 u8 acm = p_aci_aifsn->f.acm;
 521                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 522
 523                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 524
 525                 if (acm) {
 526                         switch (e_aci) {
 527                         case AC0_BE:
 528                                 acm_ctrl |= ACMHW_BEQEN;
 529                                 break;
 530                         case AC2_VI:
 531                                 acm_ctrl |= ACMHW_VIQEN;
 532                                 break;
 533                         case AC3_VO:
 534                                 acm_ctrl |= ACMHW_VOQEN;
 535                                 break;
 536                         default:
 537                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 538                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 539                                          acm);
 540                                 break;
 541                         }
 542                 } else {
 543                         switch (e_aci) {
 544                         case AC0_BE:
 545                                 acm_ctrl &= (~ACMHW_BEQEN);
 546                                 break;
 547                         case AC2_VI:
 548                                 acm_ctrl &= (~ACMHW_VIQEN);
 549                                 break;
 550                         case AC3_VO:
 551                                 acm_ctrl &= (~ACMHW_BEQEN);
 552                                 break;
 553                         default:
 554                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 555                                          "switch case not process\n");
 556                                 break;
 557                         }
 558                 }
 559
 560                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 561                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 562                          acm_ctrl);
 563                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 564                 break; }
 565         case HW_VAR_RCR:
 566                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 567                 rtlpci->receive_config = ((u32 *)(val))[0];
 568                 break;
 569         case HW_VAR_RETRY_LIMIT:{
 570                 u8 retry_limit = ((u8 *)(val))[0];
 571
 572                 rtl_write_word(rtlpriv, REG_RL,
 573                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 574                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 575                 break; }
 576         case HW_VAR_DUAL_TSF_RST:
 577                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 578                 break;
 579         case HW_VAR_EFUSE_BYTES:
 580                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 581                 break;
 582         case HW_VAR_EFUSE_USAGE:
 583                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 584                 break;
 585         case HW_VAR_IO_CMD:
 586                 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 587                 break;
 588         case HW_VAR_SET_RPWM:{
 589                 u8 rpwm_val;
 590
 591                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 592                 udelay(1);
 593
 594                 if (rpwm_val & BIT(7)) {
 595                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 596                                        (*(u8 *)val));
 597                 } else {
 598                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 599                                        ((*(u8 *)val) | BIT(7)));
 600                 }
 601                 break; }
 602         case HW_VAR_H2C_FW_PWRMODE:
 603                 rtl88e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 604                 break;
 605         case HW_VAR_FW_PSMODE_STATUS:
 606                 ppsc->fw_current_inpsmode = *((bool *)val);
 607                 break;
 608         case HW_VAR_RESUME_CLK_ON:
 609                 _rtl88ee_set_fw_ps_rf_on(hw);
 610                 break;
 611         case HW_VAR_FW_LPS_ACTION:{
 612                 bool enter_fwlps = *((bool *)val);
 613
 614                 if (enter_fwlps)
 615                         _rtl88ee_fwlps_enter(hw);
 616                  else
 617                         _rtl88ee_fwlps_leave(hw);
 618                  break; }
 619         case HW_VAR_H2C_FW_JOINBSSRPT:{
 620                 u8 mstatus = (*(u8 *)val);
 621                 u8 tmp, tmp_reg422, uval;
 622                 u8 count = 0, dlbcn_count = 0;
 623                 bool recover = false;
 624
 625                 if (mstatus == RT_MEDIA_CONNECT) {
 626                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 627
 628                         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
 629                         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(0)));
 630
 631                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 632                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 633
 634                         tmp_reg422 = rtl_read_byte(rtlpriv,
 635                                                    REG_FWHW_TXQ_CTRL + 2);
 636                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 637                                        tmp_reg422 & (~BIT(6)));
 638                         if (tmp_reg422 & BIT(6))
 639                                 recover = true;
 640
 641                         do {
 642                                 uval = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 643                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
 644                                                (uval | BIT(0)));
 645                                 _rtl88ee_return_beacon_queue_skb(hw);
 646
 647                                 rtl88e_set_fw_rsvdpagepkt(hw, 0);
 648                                 uval = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 649                                 count = 0;
 650                                 while (!(uval & BIT(0)) && count < 20) {
 651                                         count++;
 652                                         udelay(10);
 653                                         uval = rtl_read_byte(rtlpriv,
 654                                                              REG_TDECTRL+2);
 655                                 }
 656                                 dlbcn_count++;
 657                         } while (!(uval & BIT(0)) && dlbcn_count < 5);
 658
 659                         if (uval & BIT(0))
 660                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 661
 662                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 663                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 664
 665                         if (recover) {
 666                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 667                                                tmp_reg422);
 668                         }
 669                         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & ~(BIT(0))));
 670                 }
 671                 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 672                 break; }
 673         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 674                 rtl88e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 675                 break;
 676         case HW_VAR_AID:{
 677                 u16 u2btmp;
 678                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 679                 u2btmp &= 0xC000;
 680                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 681                                mac->assoc_id));
 682                 break; }
 683         case HW_VAR_CORRECT_TSF:{
 684                 u8 btype_ibss = ((u8 *)(val))[0];
 685
 686                 if (btype_ibss == true)
 687                         _rtl88ee_stop_tx_beacon(hw);
 688
 689                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 690
 691                 rtl_write_dword(rtlpriv, REG_TSFTR,
 692                                 (u32) (mac->tsf & 0xffffffff));
 693                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 694                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 695
 696                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 697
 698                 if (btype_ibss == true)
 699                         _rtl88ee_resume_tx_beacon(hw);
 700                 break; }
 701         default:
 702                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 703                          "switch case not process %x\n", variable);
 704                 break;
 705         }
 706 }
 707
 708 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 709 {
 710         struct rtl_priv *rtlpriv = rtl_priv(hw);
 711         bool status = true;
 712         long count = 0;
 713         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 714                     _LLT_OP(_LLT_WRITE_ACCESS);
 715
 716         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 717
 718         do {
 719                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 720                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 721                         break;
 722
 723                 if (count > POLLING_LLT_THRESHOLD) {
 724                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 725                                  "Failed to polling write LLT done at address %d!\n",
 726                                  address);
 727                         status = false;
 728                         break;
 729                 }
 730         } while (++count);
 731
 732         return status;
 733 }
 734
 735 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
 736 {
 737         struct rtl_priv *rtlpriv = rtl_priv(hw);
 738         unsigned short i;
 739         u8 txpktbuf_bndy;
 740         u8 maxpage;
 741         bool status;
 742
 743         maxpage = 0xAF;
 744         txpktbuf_bndy = 0xAB;
 745
 746         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
 747         rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
 748
 749
 750         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
 751         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 752
 753         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 754         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 755
 756         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 757         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 758         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 759
 760         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 761                 status = _rtl88ee_llt_write(hw, i, i + 1);
 762                 if (true != status)
 763                         return status;
 764         }
 765
 766         status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 767         if (true != status)
 768                 return status;
 769
 770         for (i = txpktbuf_bndy; i < maxpage; i++) {
 771                 status = _rtl88ee_llt_write(hw, i, (i + 1));
 772                 if (true != status)
 773                         return status;
 774         }
 775
 776         status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
 777         if (true != status)
 778                 return status;
 779
 780         return true;
 781 }
 782
 783 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 784 {
 785         struct rtl_priv *rtlpriv = rtl_priv(hw);
 786         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 787         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 788         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 789
 790         if (rtlpriv->rtlhal.up_first_time)
 791                 return;
 792
 793         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 794                 rtl88ee_sw_led_on(hw, pLed0);
 795         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 796                 rtl88ee_sw_led_on(hw, pLed0);
 797         else
 798                 rtl88ee_sw_led_off(hw, pLed0);
 799 }
 800
 801 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
 802 {
 803         struct rtl_priv *rtlpriv = rtl_priv(hw);
 804         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 805         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 806         u8 bytetmp;
 807         u16 wordtmp;
 808
 809         /*Disable XTAL OUTPUT for power saving. YJ, add, 111206. */
 810         bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
 811         rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
 812         /*Auto Power Down to CHIP-off State*/
 813         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 814         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 815
 816         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 817         /* HW Power on sequence */
 818         if (!rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 819                                         PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 820                                         Rtl8188E_NIC_ENABLE_FLOW)) {
 821                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 822                          "init MAC Fail as rtl88_hal_pwrseqcmdparsing\n");
 823                 return false;
 824         }
 825
 826         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 827         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 828
 829         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 830         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
 831
 832         bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
 833         rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
 834
 835         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
 836         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
 837
 838         bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
 839         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
 840         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
 841         rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
 842
 843         /*Add for wake up online*/
 844         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 845
 846         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
 847         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
 848         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
 849         rtl_write_byte(rtlpriv, 0x367, 0x80);
 850
 851         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 852         rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
 853         rtl_write_byte(rtlpriv, REG_CR+2, 0x00);
 854
 855         if (!rtlhal->mac_func_enable) {
 856                 if (_rtl88ee_llt_table_init(hw) == false) {
 857                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 858                                  "LLT table init fail\n");
 859                         return false;
 860                 }
 861         }
 862
 863
 864         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 865         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 866
 867         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 868         wordtmp &= 0xf;
 869         wordtmp |= 0xE771;
 870         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 871
 872         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 873         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 874         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 875
 876         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 877                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 878                         DMA_BIT_MASK(32));
 879         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 880                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 881                         DMA_BIT_MASK(32));
 882         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 883                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 884         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 885                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 886         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 887                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 888         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 889                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 890         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 891                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 892                         DMA_BIT_MASK(32));
 893         rtl_write_dword(rtlpriv, REG_RX_DESA,
 894                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 895                         DMA_BIT_MASK(32));
 896
 897         /* if we want to support 64 bit DMA, we should set it here,
 898          * but at the moment we do not support 64 bit DMA
 899          */
 900
 901         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 902
 903         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 904         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
 905
 906         if (rtlhal->earlymode_enable) {/*Early mode enable*/
 907                 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
 908                 bytetmp |= 0x1f;
 909                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
 910                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
 911         }
 912         _rtl88ee_gen_refresh_led_state(hw);
 913         return true;
 914 }
 915
 916 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
 917 {
 918         struct rtl_priv *rtlpriv = rtl_priv(hw);
 919         u32 reg_prsr;
 920
 921         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 922
 923         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 924         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 925 }
 926
 927 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
 928 {
 929         struct rtl_priv *rtlpriv = rtl_priv(hw);
 930         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 931         u8 tmp1byte = 0;
 932         u32 tmp4Byte = 0, count;
 933
 934         rtl_write_word(rtlpriv, 0x354, 0x8104);
 935         rtl_write_word(rtlpriv, 0x358, 0x24);
 936
 937         rtl_write_word(rtlpriv, 0x350, 0x70c);
 938         rtl_write_byte(rtlpriv, 0x352, 0x2);
 939         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 940         count = 0;
 941         while (tmp1byte && count < 20) {
 942                 udelay(10);
 943                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 944                 count++;
 945         }
 946         if (0 == tmp1byte) {
 947                 tmp4Byte = rtl_read_dword(rtlpriv, 0x34c);
 948                 rtl_write_dword(rtlpriv, 0x348, tmp4Byte|BIT(31));
 949                 rtl_write_word(rtlpriv, 0x350, 0xf70c);
 950                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 951         }
 952
 953         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 954         count = 0;
 955         while (tmp1byte && count < 20) {
 956                 udelay(10);
 957                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 958                 count++;
 959         }
 960
 961         rtl_write_word(rtlpriv, 0x350, 0x718);
 962         rtl_write_byte(rtlpriv, 0x352, 0x2);
 963         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 964         count = 0;
 965         while (tmp1byte && count < 20) {
 966                 udelay(10);
 967                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 968                 count++;
 969         }
 970         if (ppsc->support_backdoor || (0 == tmp1byte)) {
 971                 tmp4Byte = rtl_read_dword(rtlpriv, 0x34c);
 972                 rtl_write_dword(rtlpriv, 0x348, tmp4Byte|BIT(11)|BIT(12));
 973                 rtl_write_word(rtlpriv, 0x350, 0xf718);
 974                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 975         }
 976         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 977         count = 0;
 978         while (tmp1byte && count < 20) {
 979                 udelay(10);
 980                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 981                 count++;
 982         }
 983 }
 984
 985 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
 986 {
 987         struct rtl_priv *rtlpriv = rtl_priv(hw);
 988         u8 sec_reg_value;
 989
 990         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 991                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 992                  rtlpriv->sec.pairwise_enc_algorithm,
 993                  rtlpriv->sec.group_enc_algorithm);
 994
 995         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 996                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 997                          "not open hw encryption\n");
 998                 return;
 999         }
1000         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1001
1002         if (rtlpriv->sec.use_defaultkey) {
1003                 sec_reg_value |= SCR_TXUSEDK;
1004                 sec_reg_value |= SCR_RXUSEDK;
1005         }
1006
1007         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1008
1009         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1010
1011         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1012                  "The SECR-value %x\n", sec_reg_value);
1013         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1014 }
1015
1016 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1017 {
1018         struct rtl_priv *rtlpriv = rtl_priv(hw);
1019         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1020         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1021         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1022         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1023         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1024         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1025         bool rtstatus = true;
1026         int err = 0;
1027         u8 tmp_u1b, u1byte;
1028
1029         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Rtl8188EE hw init\n");
1030         rtlpriv->rtlhal.being_init_adapter = true;
1031         rtlpriv->intf_ops->disable_aspm(hw);
1032
1033         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1034         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1035         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1036                 rtlhal->mac_func_enable = true;
1037         } else {
1038                 rtlhal->mac_func_enable = false;
1039                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1040         }
1041
1042         rtstatus = _rtl88ee_init_mac(hw);
1043         if (rtstatus != true) {
1044                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1045                 err = 1;
1046                 return err;
1047         }
1048
1049         err = rtl88e_download_fw(hw, false);
1050         if (err) {
1051                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1052                          "Failed to download FW. Init HW without FW now..\n");
1053                 err = 1;
1054                 rtlhal->fw_ready = false;
1055                 return err;
1056         } else {
1057                 rtlhal->fw_ready = true;
1058         }
1059         /*fw related variable initialize */
1060         rtlhal->last_hmeboxnum = 0;
1061         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1062         rtlhal->fw_clk_change_in_progress = false;
1063         rtlhal->allow_sw_to_change_hwclc = false;
1064         ppsc->fw_current_inpsmode = false;
1065
1066         rtl88e_phy_mac_config(hw);
1067         /* because last function modifies RCR, we update
1068          * rcr var here, or TP will be unstable for receive_config
1069          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1070          * RCR_APP_ICV will cause mac80211 disassoc for cisco 1252
1071          */
1072         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1073         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1074
1075         rtl88e_phy_bb_config(hw);
1076         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1077         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1078
1079         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1080         rtl88e_phy_rf_config(hw);
1081
1082         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1083                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1084         rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1085
1086         _rtl88ee_hw_configure(hw);
1087         rtl_cam_reset_all_entry(hw);
1088         rtl88ee_enable_hw_security_config(hw);
1089
1090         rtlhal->mac_func_enable = true;
1091         ppsc->rfpwr_state = ERFON;
1092
1093         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1094         _rtl88ee_enable_aspm_back_door(hw);
1095         rtlpriv->intf_ops->enable_aspm(hw);
1096
1097         if (ppsc->rfpwr_state == ERFON) {
1098                 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1099                     ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1100                     (rtlhal->oem_id == RT_CID_819x_HP))) {
1101                         rtl88e_phy_set_rfpath_switch(hw, true);
1102                         rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1103                 } else {
1104                         rtl88e_phy_set_rfpath_switch(hw, false);
1105                         rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1106                 }
1107                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1108                          "rx idle ant %s\n",
1109                          (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1110                          ("MAIN_ANT") : ("AUX_ANT"));
1111
1112                 if (rtlphy->iqk_initialized) {
1113                         rtl88e_phy_iq_calibrate(hw, true);
1114                 } else {
1115                         rtl88e_phy_iq_calibrate(hw, false);
1116                         rtlphy->iqk_initialized = true;
1117                 }
1118                 rtl88e_dm_check_txpower_tracking(hw);
1119                 rtl88e_phy_lc_calibrate(hw);
1120         }
1121
1122         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1123         if (!(tmp_u1b & BIT(0))) {
1124                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1125                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1126         }
1127
1128         if (!(tmp_u1b & BIT(4))) {
1129                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1130                 tmp_u1b &= 0x0F;
1131                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1132                 udelay(10);
1133                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1134                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1135         }
1136         rtl_write_byte(rtlpriv, REG_NAV_CTRL+2,  ((30000+127)/128));
1137         rtl88e_dm_init(hw);
1138         rtlpriv->rtlhal.being_init_adapter = false;
1139         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "end of Rtl8188EE hw init %x\n",
1140                  err);
1141         return 0;
1142 }
1143
1144 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1145 {
1146         struct rtl_priv *rtlpriv = rtl_priv(hw);
1147         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1148         enum version_8188e version = VERSION_UNKNOWN;
1149         u32 value32;
1150
1151         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1152         if (value32 & TRP_VAUX_EN) {
1153                 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1154         } else {
1155                 version = NORMAL_CHIP;
1156                 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1157                 version = version | ((value32 & VENDOR_ID) ?
1158                           CHIP_VENDOR_UMC : 0);
1159         }
1160
1161         rtlphy->rf_type = RF_1T1R;
1162         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1163                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1164                  "RF_2T2R" : "RF_1T1R");
1165
1166         return version;
1167 }
1168
1169 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1170                                      enum nl80211_iftype type)
1171 {
1172         struct rtl_priv *rtlpriv = rtl_priv(hw);
1173         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1174         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1175         bt_msr &= 0xfc;
1176
1177         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1178             type == NL80211_IFTYPE_STATION) {
1179                 _rtl88ee_stop_tx_beacon(hw);
1180                 _rtl88ee_enable_bcn_sub_func(hw);
1181         } else if (type == NL80211_IFTYPE_ADHOC ||
1182                 type == NL80211_IFTYPE_AP ||
1183                 type == NL80211_IFTYPE_MESH_POINT) {
1184                 _rtl88ee_resume_tx_beacon(hw);
1185                 _rtl88ee_disable_bcn_sub_func(hw);
1186         } else {
1187                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1188                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1189                          type);
1190         }
1191
1192         switch (type) {
1193         case NL80211_IFTYPE_UNSPECIFIED:
1194                 bt_msr |= MSR_NOLINK;
1195                 ledaction = LED_CTL_LINK;
1196                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1197                          "Set Network type to NO LINK!\n");
1198                 break;
1199         case NL80211_IFTYPE_ADHOC:
1200                 bt_msr |= MSR_ADHOC;
1201                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1202                          "Set Network type to Ad Hoc!\n");
1203                 break;
1204         case NL80211_IFTYPE_STATION:
1205                 bt_msr |= MSR_INFRA;
1206                 ledaction = LED_CTL_LINK;
1207                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1208                          "Set Network type to STA!\n");
1209                 break;
1210         case NL80211_IFTYPE_AP:
1211                 bt_msr |= MSR_AP;
1212                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1213                          "Set Network type to AP!\n");
1214                 break;
1215         case NL80211_IFTYPE_MESH_POINT:
1216                 bt_msr |= MSR_ADHOC;
1217                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1218                          "Set Network type to Mesh Point!\n");
1219                 break;
1220         default:
1221                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1222                          "Network type %d not support!\n", type);
1223                 return 1;
1224         }
1225
1226         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1227         rtlpriv->cfg->ops->led_control(hw, ledaction);
1228         if ((bt_msr & 0xfc) == MSR_AP)
1229                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1230         else
1231                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1232         return 0;
1233 }
1234
1235 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1236 {
1237         struct rtl_priv *rtlpriv = rtl_priv(hw);
1238         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1239         u32 reg_rcr = rtlpci->receive_config;
1240
1241         if (rtlpriv->psc.rfpwr_state != ERFON)
1242                 return;
1243
1244         if (check_bssid == true) {
1245                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1246                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1247                                               (u8 *)(&reg_rcr));
1248                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1249         } else if (check_bssid == false) {
1250                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1251                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1252                 rtlpriv->cfg->ops->set_hw_reg(hw,
1253                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1254         }
1255 }
1256
1257 int rtl88ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1258 {
1259         struct rtl_priv *rtlpriv = rtl_priv(hw);
1260
1261         if (_rtl88ee_set_media_status(hw, type))
1262                 return -EOPNOTSUPP;
1263
1264         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1265                 if (type != NL80211_IFTYPE_AP &&
1266                     type != NL80211_IFTYPE_MESH_POINT)
1267                         rtl88ee_set_check_bssid(hw, true);
1268         } else {
1269                 rtl88ee_set_check_bssid(hw, false);
1270         }
1271
1272         return 0;
1273 }
1274
1275 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1276 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1277 {
1278         struct rtl_priv *rtlpriv = rtl_priv(hw);
1279         rtl88e_dm_init_edca_turbo(hw);
1280         switch (aci) {
1281         case AC1_BK:
1282                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1283                 break;
1284         case AC0_BE:
1285                 break;
1286         case AC2_VI:
1287                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1288                 break;
1289         case AC3_VO:
1290                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1291                 break;
1292         default:
1293                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1294                 break;
1295         }
1296 }
1297
1298 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1299 {
1300         struct rtl_priv *rtlpriv = rtl_priv(hw);
1301         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1302
1303         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1304         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1305         rtlpci->irq_enabled = true;
1306         /* there are some C2H CMDs have been sent before system interrupt
1307          * is enabled, e.g., C2H, CPWM.
1308          * So we need to clear all C2H events that FW has notified, otherwise
1309          * FW won't schedule any commands anymore.
1310          */
1311         rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1312         /*enable system interrupt*/
1313         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1314 }
1315
1316 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1317 {
1318         struct rtl_priv *rtlpriv = rtl_priv(hw);
1319         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1320
1321         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1322         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1323         rtlpci->irq_enabled = false;
1324         synchronize_irq(rtlpci->pdev->irq);
1325 }
1326
1327 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1328 {
1329         struct rtl_priv *rtlpriv = rtl_priv(hw);
1330         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1331         u8 u1b_tmp;
1332         u32 count = 0;
1333         rtlhal->mac_func_enable = false;
1334         rtlpriv->intf_ops->enable_aspm(hw);
1335
1336         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1337         u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1338         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1339
1340         u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1341         while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1342                 udelay(10);
1343                 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1344                 count++;
1345         }
1346         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1347
1348         rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1349                                    PWR_INTF_PCI_MSK,
1350                                    Rtl8188E_NIC_LPS_ENTER_FLOW);
1351
1352         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1353
1354         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1355                 rtl88e_firmware_selfreset(hw);
1356
1357         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1358         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1359         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1360
1361         u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1362         rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1363
1364         rtl88_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1365                                    PWR_INTF_PCI_MSK, Rtl8188E_NIC_DISABLE_FLOW);
1366
1367         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1368         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1369         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1370         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1371
1372         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1373
1374         u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1375         rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1376         rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1377
1378         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1379         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1380         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1381         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1382
1383         rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1384 }
1385
1386 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1387 {
1388         struct rtl_priv *rtlpriv = rtl_priv(hw);
1389         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1390         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1391         enum nl80211_iftype opmode;
1392
1393         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1394
1395         mac->link_state = MAC80211_NOLINK;
1396         opmode = NL80211_IFTYPE_UNSPECIFIED;
1397
1398         _rtl88ee_set_media_status(hw, opmode);
1399
1400         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1401             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1402                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1403
1404         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1405         _rtl88ee_poweroff_adapter(hw);
1406
1407         /* after power off we should do iqk again */
1408         rtlpriv->phy.iqk_initialized = false;
1409 }
1410
1411 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1412                                   u32 *p_inta, u32 *p_intb)
1413 {
1414         struct rtl_priv *rtlpriv = rtl_priv(hw);
1415         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1416
1417         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1418         rtl_write_dword(rtlpriv, ISR, *p_inta);
1419
1420         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1421         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1422 }
1423
1424 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1425 {
1426         struct rtl_priv *rtlpriv = rtl_priv(hw);
1427         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1428         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1429         u16 bcn_interval, atim_window;
1430
1431         bcn_interval = mac->beacon_interval;
1432         atim_window = 2;        /*FIX MERGE */
1433         rtl88ee_disable_interrupt(hw);
1434         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1435         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1436         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1437         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1438         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1439         rtl_write_byte(rtlpriv, 0x606, 0x30);
1440         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1441         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1442         /*rtl88ee_enable_interrupt(hw);*/
1443 }
1444
1445 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1446 {
1447         struct rtl_priv *rtlpriv = rtl_priv(hw);
1448         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1449         u16 bcn_interval = mac->beacon_interval;
1450
1451         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1452                  "beacon_interval:%d\n", bcn_interval);
1453         /*rtl88ee_disable_interrupt(hw);*/
1454         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1455         /*rtl88ee_enable_interrupt(hw);*/
1456 }
1457
1458 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1459                                    u32 add_msr, u32 rm_msr)
1460 {
1461         struct rtl_priv *rtlpriv = rtl_priv(hw);
1462         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1463
1464         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1465                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1466
1467         rtl88ee_disable_interrupt(hw);
1468         if (add_msr)
1469                 rtlpci->irq_mask[0] |= add_msr;
1470         if (rm_msr)
1471                 rtlpci->irq_mask[0] &= (~rm_msr);
1472         rtl88ee_enable_interrupt(hw);
1473 }
1474
1475 static inline u8 get_chnl_group(u8 chnl)
1476 {
1477         u8 group;
1478
1479         group = chnl / 3;
1480         if (chnl == 14)
1481                 group = 5;
1482
1483         return group;
1484 }
1485
1486 static void set_diff0_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1487                          u32 i, u32 eadr)
1488 {
1489         pwr2g->bw40_diff[path][i] = 0;
1490         if (hwinfo[eadr] == 0xFF) {
1491                 pwr2g->bw20_diff[path][i] = 0x02;
1492         } else {
1493                 pwr2g->bw20_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1494                 /*bit sign number to 8 bit sign number*/
1495                 if (pwr2g->bw20_diff[path][i] & BIT(3))
1496                         pwr2g->bw20_diff[path][i] |= 0xF0;
1497         }
1498
1499         if (hwinfo[eadr] == 0xFF) {
1500                 pwr2g->ofdm_diff[path][i] = 0x04;
1501         } else {
1502                 pwr2g->ofdm_diff[path][i] = (hwinfo[eadr] & 0x0f);
1503                 /*bit sign number to 8 bit sign number*/
1504                 if (pwr2g->ofdm_diff[path][i] & BIT(3))
1505                         pwr2g->ofdm_diff[path][i] |= 0xF0;
1506         }
1507         pwr2g->cck_diff[path][i] = 0;
1508 }
1509
1510 static void set_diff0_5g(struct txpower_info_5g *pwr5g, u8 *hwinfo, u32 path,
1511                          u32 i, u32 eadr)
1512 {
1513         pwr5g->bw40_diff[path][i] = 0;
1514         if (hwinfo[eadr] == 0xFF) {
1515                 pwr5g->bw20_diff[path][i] = 0;
1516         } else {
1517                 pwr5g->bw20_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1518                 /*bit sign number to 8 bit sign number*/
1519                 if (pwr5g->bw20_diff[path][i] & BIT(3))
1520                         pwr5g->bw20_diff[path][i] |= 0xF0;
1521         }
1522
1523         if (hwinfo[eadr] == 0xFF) {
1524                 pwr5g->ofdm_diff[path][i] = 0x04;
1525         } else {
1526                 pwr5g->ofdm_diff[path][i] = (hwinfo[eadr] & 0x0f);
1527                 /*bit sign number to 8 bit sign number*/
1528                 if (pwr5g->ofdm_diff[path][i] & BIT(3))
1529                         pwr5g->ofdm_diff[path][i] |= 0xF0;
1530         }
1531 }
1532
1533 static void set_diff1_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1534                          u32 i, u32 eadr)
1535 {
1536         if (hwinfo[eadr] == 0xFF) {
1537                 pwr2g->bw40_diff[path][i] = 0xFE;
1538         } else {
1539                 pwr2g->bw40_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1540                 if (pwr2g->bw40_diff[path][i] & BIT(3))
1541                         pwr2g->bw40_diff[path][i] |= 0xF0;
1542         }
1543
1544         if (hwinfo[eadr] == 0xFF) {
1545                 pwr2g->bw20_diff[path][i] = 0xFE;
1546         } else {
1547                 pwr2g->bw20_diff[path][i] = (hwinfo[eadr]&0x0f);
1548                 if (pwr2g->bw20_diff[path][i] & BIT(3))
1549                         pwr2g->bw20_diff[path][i] |= 0xF0;
1550         }
1551 }
1552
1553 static void set_diff1_5g(struct txpower_info_5g *pwr5g, u8 *hwinfo, u32 path,
1554                          u32 i, u32 eadr)
1555 {
1556         if (hwinfo[eadr] == 0xFF) {
1557                 pwr5g->bw40_diff[path][i] = 0xFE;
1558         } else {
1559                 pwr5g->bw40_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1560                 if (pwr5g->bw40_diff[path][i] & BIT(3))
1561                         pwr5g->bw40_diff[path][i] |= 0xF0;
1562         }
1563
1564         if (hwinfo[eadr] == 0xFF) {
1565                 pwr5g->bw20_diff[path][i] = 0xFE;
1566         } else {
1567                 pwr5g->bw20_diff[path][i] = (hwinfo[eadr] & 0x0f);
1568                 if (pwr5g->bw20_diff[path][i] & BIT(3))
1569                         pwr5g->bw20_diff[path][i] |= 0xF0;
1570         }
1571 }
1572
1573 static void set_diff2_2g(struct txpower_info_2g *pwr2g, u8 *hwinfo, u32 path,
1574                          u32 i, u32 eadr)
1575 {
1576         if (hwinfo[eadr] == 0xFF) {
1577                 pwr2g->ofdm_diff[path][i] = 0xFE;
1578         } else {
1579                 pwr2g->ofdm_diff[path][i] = (hwinfo[eadr]&0xf0)>>4;
1580                 if (pwr2g->ofdm_diff[path][i] & BIT(3))
1581                         pwr2g->ofdm_diff[path][i] |= 0xF0;
1582         }
1583
1584         if (hwinfo[eadr] == 0xFF) {
1585                 pwr2g->cck_diff[path][i] = 0xFE;
1586         } else {
1587                 pwr2g->cck_diff[path][i] = (hwinfo[eadr]&0x0f);
1588                 if (pwr2g->cck_diff[path][i] & BIT(3))
1589                         pwr2g->cck_diff[path][i] |= 0xF0;
1590         }
1591 }
1592
1593 static void _rtl8188e_read_power_value_fromprom(struct ieee80211_hw *hw,
1594                                                 struct txpower_info_2g *pwr2g,
1595                                                 struct txpower_info_5g *pwr5g,
1596                                                 bool autoload_fail,
1597                                                 u8 *hwinfo)
1598 {
1599         struct rtl_priv *rtlpriv = rtl_priv(hw);
1600         u32 path, eadr = EEPROM_TX_PWR_INX, i;
1601
1602         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1603                  "hal_ReadPowerValueFromPROM88E(): PROMContent[0x%x]= 0x%x\n",
1604                  (eadr+1), hwinfo[eadr+1]);
1605         if (0xFF == hwinfo[eadr+1])
1606                 autoload_fail = true;
1607
1608         if (autoload_fail) {
1609                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1610                          "auto load fail : Use Default value!\n");
1611                 for (path = 0; path < MAX_RF_PATH; path++) {
1612                         /* 2.4G default value */
1613                         for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1614                                 pwr2g->index_cck_base[path][i] = 0x2D;
1615                                 pwr2g->index_bw40_base[path][i] = 0x2D;
1616                         }
1617                         for (i = 0; i < MAX_TX_COUNT; i++) {
1618                                 if (i == 0) {
1619                                         pwr2g->bw20_diff[path][0] = 0x02;
1620                                         pwr2g->ofdm_diff[path][0] = 0x04;
1621                                 } else {
1622                                         pwr2g->bw20_diff[path][i] = 0xFE;
1623                                         pwr2g->bw40_diff[path][i] = 0xFE;
1624                                         pwr2g->cck_diff[path][i] = 0xFE;
1625                                         pwr2g->ofdm_diff[path][i] = 0xFE;
1626                                 }
1627                         }
1628                 }
1629                 return;
1630         }
1631
1632         for (path = 0; path < MAX_RF_PATH; path++) {
1633                 /*2.4G default value*/
1634                 for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1635                         pwr2g->index_cck_base[path][i] = hwinfo[eadr++];
1636                         if (pwr2g->index_cck_base[path][i] == 0xFF)
1637                                 pwr2g->index_cck_base[path][i] = 0x2D;
1638                 }
1639                 for (i = 0; i < MAX_CHNL_GROUP_24G; i++) {
1640                         pwr2g->index_bw40_base[path][i] = hwinfo[eadr++];
1641                         if (pwr2g->index_bw40_base[path][i] == 0xFF)
1642                                 pwr2g->index_bw40_base[path][i] = 0x2D;
1643                 }
1644                 for (i = 0; i < MAX_TX_COUNT; i++) {
1645                         if (i == 0) {
1646                                 set_diff0_2g(pwr2g, hwinfo, path, i, eadr);
1647                                 eadr++;
1648                         } else {
1649                                 set_diff1_2g(pwr2g, hwinfo, path, i, eadr);
1650                                 eadr++;
1651
1652                                 set_diff2_2g(pwr2g, hwinfo, path, i, eadr);
1653                                 eadr++;
1654                         }
1655                 }
1656
1657                 /*5G default value*/
1658                 for (i = 0; i < MAX_CHNL_GROUP_5G; i++) {
1659                         pwr5g->index_bw40_base[path][i] = hwinfo[eadr++];
1660                         if (pwr5g->index_bw40_base[path][i] == 0xFF)
1661                                 pwr5g->index_bw40_base[path][i] = 0xFE;
1662                 }
1663
1664                 for (i = 0; i < MAX_TX_COUNT; i++) {
1665                         if (i == 0) {
1666                                 set_diff0_5g(pwr5g, hwinfo, path, i, eadr);
1667                                 eadr++;
1668                         } else {
1669                                 set_diff1_5g(pwr5g, hwinfo, path, i, eadr);
1670                                 eadr++;
1671                         }
1672                 }
1673
1674                 if (hwinfo[eadr] == 0xFF) {
1675                         pwr5g->ofdm_diff[path][1] = 0xFE;
1676                         pwr5g->ofdm_diff[path][2] = 0xFE;
1677                 } else {
1678                         pwr5g->ofdm_diff[path][1] = (hwinfo[eadr] & 0xf0) >> 4;
1679                         pwr5g->ofdm_diff[path][2] = (hwinfo[eadr] & 0x0f);
1680                 }
1681                 eadr++;
1682
1683                 if (hwinfo[eadr] == 0xFF)
1684                         pwr5g->ofdm_diff[path][3] = 0xFE;
1685                 else
1686                         pwr5g->ofdm_diff[path][3] = (hwinfo[eadr]&0x0f);
1687                 eadr++;
1688
1689                 for (i = 1; i < MAX_TX_COUNT; i++) {
1690                         if (pwr5g->ofdm_diff[path][i] == 0xFF)
1691                                 pwr5g->ofdm_diff[path][i] = 0xFE;
1692                         else if (pwr5g->ofdm_diff[path][i] & BIT(3))
1693                                 pwr5g->ofdm_diff[path][i] |= 0xF0;
1694                 }
1695         }
1696 }
1697
1698 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1699                                                  bool autoload_fail,
1700                                                  u8 *hwinfo)
1701 {
1702         struct rtl_priv *rtlpriv = rtl_priv(hw);
1703         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1704         struct txpower_info_2g pwrinfo24g;
1705         struct txpower_info_5g pwrinfo5g;
1706         u8 rf_path, index;
1707         u8 i;
1708         int jj = EEPROM_RF_BOARD_OPTION_88E;
1709         int kk = EEPROM_THERMAL_METER_88E;
1710
1711         _rtl8188e_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g,
1712                                             autoload_fail, hwinfo);
1713
1714         for (rf_path = 0; rf_path < 2; rf_path++) {
1715                 for (i = 0; i < 14; i++) {
1716                         index = get_chnl_group(i+1);
1717
1718                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1719                                  pwrinfo24g.index_cck_base[rf_path][index];
1720                         if (i == 13)
1721                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1722                                      pwrinfo24g.index_bw40_base[rf_path][4];
1723                         else
1724                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1725                                      pwrinfo24g.index_bw40_base[rf_path][index];
1726                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1727                                  pwrinfo24g.bw20_diff[rf_path][0];
1728                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1729                                  pwrinfo24g.ofdm_diff[rf_path][0];
1730                 }
1731
1732                 for (i = 0; i < 14; i++) {
1733                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1734                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = "
1735                                 "[0x%x / 0x%x ]\n", rf_path, i,
1736                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1737                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1738                 }
1739         }
1740
1741         if (!autoload_fail)
1742                 rtlefuse->eeprom_thermalmeter = hwinfo[kk];
1743         else
1744                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1745
1746         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1747                 rtlefuse->apk_thermalmeterignore = true;
1748                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1749         }
1750
1751         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1752         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1753                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1754
1755         if (!autoload_fail) {
1756                 rtlefuse->eeprom_regulatory = hwinfo[jj] & 0x07;/*bit0~2*/
1757                 if (hwinfo[jj] == 0xFF)
1758                         rtlefuse->eeprom_regulatory = 0;
1759         } else {
1760                 rtlefuse->eeprom_regulatory = 0;
1761         }
1762         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1763                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1764 }
1765
1766 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1767 {
1768         struct rtl_priv *rtlpriv = rtl_priv(hw);
1769         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1770         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1771         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
1772         u16 i, usvalue;
1773         u8 hwinfo[HWSET_MAX_SIZE];
1774         u16 eeprom_id;
1775         int jj = EEPROM_RF_BOARD_OPTION_88E;
1776         int kk = EEPROM_RF_FEATURE_OPTION_88E;
1777
1778         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1779                 rtl_efuse_shadow_map_update(hw);
1780
1781                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1782                        HWSET_MAX_SIZE);
1783         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1784                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1785                          "RTL819X Not boot from eeprom, check it !!");
1786         }
1787
1788         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1789                       hwinfo, HWSET_MAX_SIZE);
1790
1791         eeprom_id = *((u16 *)&hwinfo[0]);
1792         if (eeprom_id != RTL8188E_EEPROM_ID) {
1793                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1794                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1795                 rtlefuse->autoload_failflag = true;
1796         } else {
1797                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1798                 rtlefuse->autoload_failflag = false;
1799         }
1800
1801         if (rtlefuse->autoload_failflag == true)
1802                 return;
1803         /*VID DID SVID SDID*/
1804         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1805         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1806         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1807         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1808         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1809                  "EEPROMId = 0x%4x\n", eeprom_id);
1810         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1811                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1812         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1813                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1814         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1815                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1816         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1817                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1818         /*customer ID*/
1819         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1820         if (rtlefuse->eeprom_oemid == 0xFF)
1821                 rtlefuse->eeprom_oemid = 0;
1822
1823         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1824                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1825         /*EEPROM version*/
1826         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1827         /*mac address*/
1828         for (i = 0; i < 6; i += 2) {
1829                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1830                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1831         }
1832
1833         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1834                  "dev_addr: %pM\n", rtlefuse->dev_addr);
1835         /*channel plan */
1836         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1837         /* set channel paln to world wide 13 */
1838         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1839         /*tx power*/
1840         _rtl88ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1841                                              hwinfo);
1842         rtlefuse->txpwr_fromeprom = true;
1843
1844         rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1845                                                  rtlefuse->autoload_failflag,
1846                                                  hwinfo);
1847         /*board type*/
1848         rtlefuse->board_type = (((*(u8 *)&hwinfo[jj]) & 0xE0) >> 5);
1849         /*Wake on wlan*/
1850         rtlefuse->wowlan_enable = ((hwinfo[kk] & 0x40) >> 6);
1851         /*parse xtal*/
1852         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1853         if (hwinfo[EEPROM_XTAL_88E])
1854                 rtlefuse->crystalcap = 0x20;
1855         /*antenna diversity*/
1856         rtlefuse->antenna_div_cfg = (hwinfo[jj] & 0x18) >> 3;
1857         if (hwinfo[jj] == 0xFF)
1858                 rtlefuse->antenna_div_cfg = 0;
1859         if (rppriv->bt_coexist.eeprom_bt_coexist != 0 &&
1860             rppriv->bt_coexist.eeprom_bt_ant_num == ANT_X1)
1861                 rtlefuse->antenna_div_cfg = 0;
1862
1863         rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1864         if (rtlefuse->antenna_div_type == 0xFF)
1865                 rtlefuse->antenna_div_type = 0x01;
1866         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1867             rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1868                 rtlefuse->antenna_div_cfg = 1;
1869
1870         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1871                 switch (rtlefuse->eeprom_oemid) {
1872                 case EEPROM_CID_DEFAULT:
1873                         if (rtlefuse->eeprom_did == 0x8179) {
1874                                 if (rtlefuse->eeprom_svid == 0x1025) {
1875                                         rtlhal->oem_id = RT_CID_819x_Acer;
1876                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1877                                             rtlefuse->eeprom_smid == 0x0179) ||
1878                                             (rtlefuse->eeprom_svid == 0x17AA &&
1879                                             rtlefuse->eeprom_smid == 0x0179)) {
1880                                         rtlhal->oem_id = RT_CID_819x_Lenovo;
1881                                 } else if (rtlefuse->eeprom_svid == 0x103c &&
1882                                          rtlefuse->eeprom_smid == 0x197d) {
1883                                         rtlhal->oem_id = RT_CID_819x_HP;
1884                                 } else {
1885                                         rtlhal->oem_id = RT_CID_DEFAULT;
1886                                 }
1887                         } else {
1888                                 rtlhal->oem_id = RT_CID_DEFAULT;
1889                         }
1890                         break;
1891                 case EEPROM_CID_TOSHIBA:
1892                         rtlhal->oem_id = RT_CID_TOSHIBA;
1893                         break;
1894                 case EEPROM_CID_QMI:
1895                         rtlhal->oem_id = RT_CID_819x_QMI;
1896                         break;
1897                 case EEPROM_CID_WHQL:
1898                 default:
1899                         rtlhal->oem_id = RT_CID_DEFAULT;
1900                         break;
1901                 }
1902         }
1903 }
1904
1905 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1906 {
1907         struct rtl_priv *rtlpriv = rtl_priv(hw);
1908         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1909         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1910
1911         pcipriv->ledctl.led_opendrain = true;
1912
1913         switch (rtlhal->oem_id) {
1914         case RT_CID_819x_HP:
1915                 pcipriv->ledctl.led_opendrain = true;
1916                 break;
1917         case RT_CID_819x_Lenovo:
1918         case RT_CID_DEFAULT:
1919         case RT_CID_TOSHIBA:
1920         case RT_CID_CCX:
1921         case RT_CID_819x_Acer:
1922         case RT_CID_WHQL:
1923         default:
1924                 break;
1925         }
1926         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1927                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1928 }
1929
1930 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1931 {
1932         struct rtl_priv *rtlpriv = rtl_priv(hw);
1933         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1934         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1935         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1936         u8 tmp_u1b;
1937
1938         rtlhal->version = _rtl88ee_read_chip_version(hw);
1939         if (get_rf_type(rtlphy) == RF_1T1R) {
1940                 rtlpriv->dm.rfpath_rxenable[0] = true;
1941         } else {
1942                 rtlpriv->dm.rfpath_rxenable[0] = true;
1943                 rtlpriv->dm.rfpath_rxenable[1] = true;
1944         }
1945         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1946                  rtlhal->version);
1947         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1948         if (tmp_u1b & BIT(4)) {
1949                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1950                 rtlefuse->epromtype = EEPROM_93C46;
1951         } else {
1952                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1953                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1954         }
1955         if (tmp_u1b & BIT(5)) {
1956                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1957                 rtlefuse->autoload_failflag = false;
1958                 _rtl88ee_read_adapter_info(hw);
1959         } else {
1960                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1961         }
1962         _rtl88ee_hal_customized_behavior(hw);
1963 }
1964
1965 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1966                                           struct ieee80211_sta *sta)
1967 {
1968         struct rtl_priv *rtlpriv = rtl_priv(hw);
1969         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
1970         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1971         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1972         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1973         u32 ratr_value;
1974         u8 ratr_index = 0;
1975         u8 nmode = mac->ht_enable;
1976         u8 mimo_ps = IEEE80211_SMPS_OFF;
1977         u16 shortgi_rate;
1978         u32 tmp_ratr_value;
1979         u8 ctx40 = mac->bw_40;
1980         u16 cap = sta->ht_cap.cap;
1981         u8 short40 = (cap & IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
1982         u8 short20 = (cap & IEEE80211_HT_CAP_SGI_20) ?  1 : 0;
1983         enum wireless_mode wirelessmode = mac->mode;
1984
1985         if (rtlhal->current_bandtype == BAND_ON_5G)
1986                 ratr_value = sta->supp_rates[1] << 4;
1987         else
1988                 ratr_value = sta->supp_rates[0];
1989         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1990                 ratr_value = 0xfff;
1991         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1992                         sta->ht_cap.mcs.rx_mask[0] << 12);
1993         switch (wirelessmode) {
1994         case WIRELESS_MODE_B:
1995                 if (ratr_value & 0x0000000c)
1996                         ratr_value &= 0x0000000d;
1997                 else
1998                         ratr_value &= 0x0000000f;
1999                 break;
2000         case WIRELESS_MODE_G:
2001                 ratr_value &= 0x00000FF5;
2002                 break;
2003         case WIRELESS_MODE_N_24G:
2004         case WIRELESS_MODE_N_5G:
2005                 nmode = 1;
2006                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2007                         ratr_value &= 0x0007F005;
2008                 } else {
2009                         u32 ratr_mask;
2010
2011                         if (get_rf_type(rtlphy) == RF_1T2R ||
2012                             get_rf_type(rtlphy) == RF_1T1R)
2013                                 ratr_mask = 0x000ff005;
2014                         else
2015                                 ratr_mask = 0x0f0ff005;
2016
2017                         ratr_value &= ratr_mask;
2018                 }
2019                 break;
2020         default:
2021                 if (rtlphy->rf_type == RF_1T2R)
2022                         ratr_value &= 0x000ff0ff;
2023                 else
2024                         ratr_value &= 0x0f0ff0ff;
2025
2026                 break;
2027         }
2028
2029         if ((rppriv->bt_coexist.bt_coexistence) &&
2030             (rppriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
2031             (rppriv->bt_coexist.bt_cur_state) &&
2032             (rppriv->bt_coexist.bt_ant_isolation) &&
2033             ((rppriv->bt_coexist.bt_service == BT_SCO) ||
2034             (rppriv->bt_coexist.bt_service == BT_BUSY)))
2035                 ratr_value &= 0x0fffcfc0;
2036         else
2037                 ratr_value &= 0x0FFFFFFF;
2038
2039         if (nmode && ((ctx40 && short40) ||
2040                       (!ctx40 && short20))) {
2041                 ratr_value |= 0x10000000;
2042                 tmp_ratr_value = (ratr_value >> 12);
2043
2044                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2045                         if ((1 << shortgi_rate) & tmp_ratr_value)
2046                                 break;
2047                 }
2048
2049                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2050                     (shortgi_rate << 4) | (shortgi_rate);
2051         }
2052
2053         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2054
2055         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2056                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2057 }
2058
2059 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2060                                          struct ieee80211_sta *sta, u8 rssi)
2061 {
2062         struct rtl_priv *rtlpriv = rtl_priv(hw);
2063         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2064         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2065         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2066         struct rtl_sta_info *sta_entry = NULL;
2067         u32 ratr_bitmap;
2068         u8 ratr_index;
2069         u16 cap = sta->ht_cap.cap;
2070         u8 ctx40 = (cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2071         u8 short40 = (cap & IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
2072         u8 short20 = (cap & IEEE80211_HT_CAP_SGI_20) ?  1 : 0;
2073         enum wireless_mode wirelessmode = 0;
2074         bool shortgi = false;
2075         u8 rate_mask[5];
2076         u8 macid = 0;
2077         u8 mimo_ps = IEEE80211_SMPS_OFF;
2078
2079         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2080         wirelessmode = sta_entry->wireless_mode;
2081         if (mac->opmode == NL80211_IFTYPE_STATION ||
2082             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2083                 ctx40 = mac->bw_40;
2084         else if (mac->opmode == NL80211_IFTYPE_AP ||
2085                  mac->opmode == NL80211_IFTYPE_ADHOC)
2086                 macid = sta->aid + 1;
2087
2088         if (rtlhal->current_bandtype == BAND_ON_5G)
2089                 ratr_bitmap = sta->supp_rates[1] << 4;
2090         else
2091                 ratr_bitmap = sta->supp_rates[0];
2092         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2093                 ratr_bitmap = 0xfff;
2094         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2095                         sta->ht_cap.mcs.rx_mask[0] << 12);
2096         switch (wirelessmode) {
2097         case WIRELESS_MODE_B:
2098                 ratr_index = RATR_INX_WIRELESS_B;
2099                 if (ratr_bitmap & 0x0000000c)
2100                         ratr_bitmap &= 0x0000000d;
2101                 else
2102                         ratr_bitmap &= 0x0000000f;
2103                 break;
2104         case WIRELESS_MODE_G:
2105                 ratr_index = RATR_INX_WIRELESS_GB;
2106
2107                 if (rssi == 1)
2108                         ratr_bitmap &= 0x00000f00;
2109                 else if (rssi == 2)
2110                         ratr_bitmap &= 0x00000ff0;
2111                 else
2112                         ratr_bitmap &= 0x00000ff5;
2113                 break;
2114         case WIRELESS_MODE_A:
2115                 ratr_index = RATR_INX_WIRELESS_A;
2116                 ratr_bitmap &= 0x00000ff0;
2117                 break;
2118         case WIRELESS_MODE_N_24G:
2119         case WIRELESS_MODE_N_5G:
2120                 ratr_index = RATR_INX_WIRELESS_NGB;
2121
2122                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2123                         if (rssi == 1)
2124                                 ratr_bitmap &= 0x00070000;
2125                         else if (rssi == 2)
2126                                 ratr_bitmap &= 0x0007f000;
2127                         else
2128                                 ratr_bitmap &= 0x0007f005;
2129                 } else {
2130                         if (rtlphy->rf_type == RF_1T2R ||
2131                             rtlphy->rf_type == RF_1T1R) {
2132                                 if (ctx40) {
2133                                         if (rssi == 1)
2134                                                 ratr_bitmap &= 0x000f0000;
2135                                         else if (rssi == 2)
2136                                                 ratr_bitmap &= 0x000ff000;
2137                                         else
2138                                                 ratr_bitmap &= 0x000ff015;
2139                                 } else {
2140                                         if (rssi == 1)
2141                                                 ratr_bitmap &= 0x000f0000;
2142                                         else if (rssi == 2)
2143                                                 ratr_bitmap &= 0x000ff000;
2144                                         else
2145                                                 ratr_bitmap &= 0x000ff005;
2146                                 }
2147                         } else {
2148                                 if (ctx40) {
2149                                         if (rssi == 1)
2150                                                 ratr_bitmap &= 0x0f8f0000;
2151                                         else if (rssi == 2)
2152                                                 ratr_bitmap &= 0x0f8ff000;
2153                                         else
2154                                                 ratr_bitmap &= 0x0f8ff015;
2155                                 } else {
2156                                         if (rssi == 1)
2157                                                 ratr_bitmap &= 0x0f8f0000;
2158                                         else if (rssi == 2)
2159                                                 ratr_bitmap &= 0x0f8ff000;
2160                                         else
2161                                                 ratr_bitmap &= 0x0f8ff005;
2162                                 }
2163                         }
2164                 }
2165
2166                 if ((ctx40 && short40) || (!ctx40 && short20)) {
2167                         if (macid == 0)
2168                                 shortgi = true;
2169                         else if (macid == 1)
2170                                 shortgi = false;
2171                 }
2172                 break;
2173         default:
2174                 ratr_index = RATR_INX_WIRELESS_NGB;
2175
2176                 if (rtlphy->rf_type == RF_1T2R)
2177                         ratr_bitmap &= 0x000ff0ff;
2178                 else
2179                         ratr_bitmap &= 0x0f0ff0ff;
2180                 break;
2181         }
2182         sta_entry->ratr_index = ratr_index;
2183
2184         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2185                  "ratr_bitmap :%x\n", ratr_bitmap);
2186         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2187                              (ratr_index << 28);
2188         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2189         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2190                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2191                  ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2192                  rate_mask[2], rate_mask[3], rate_mask[4]);
2193         rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2194         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2195 }
2196
2197 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2198                 struct ieee80211_sta *sta, u8 rssi)
2199 {
2200         struct rtl_priv *rtlpriv = rtl_priv(hw);
2201
2202         if (rtlpriv->dm.useramask)
2203                 rtl88ee_update_hal_rate_mask(hw, sta, rssi);
2204         else
2205                 rtl88ee_update_hal_rate_table(hw, sta);
2206 }
2207
2208 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2209 {
2210         struct rtl_priv *rtlpriv = rtl_priv(hw);
2211         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2212         u16 sifs_timer;
2213
2214         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2215                                       (u8 *)&mac->slot_time);
2216         if (!mac->ht_enable)
2217                 sifs_timer = 0x0a0a;
2218         else
2219                 sifs_timer = 0x0e0e;
2220         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2221 }
2222
2223 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2224 {
2225         struct rtl_priv *rtlpriv = rtl_priv(hw);
2226         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2227         enum rf_pwrstate state_toset;
2228         u32 u4tmp;
2229         bool actuallyset = false;
2230
2231         if (rtlpriv->rtlhal.being_init_adapter)
2232                 return false;
2233
2234         if (ppsc->swrf_processing)
2235                 return false;
2236
2237         spin_lock(&rtlpriv->locks.rf_ps_lock);
2238         if (ppsc->rfchange_inprogress) {
2239                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2240                 return false;
2241         } else {
2242                 ppsc->rfchange_inprogress = true;
2243                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2244         }
2245
2246         u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2247         state_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2248
2249
2250         if ((ppsc->hwradiooff == true) && (state_toset == ERFON)) {
2251                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2252                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2253
2254                 state_toset = ERFON;
2255                 ppsc->hwradiooff = false;
2256                 actuallyset = true;
2257         } else if ((ppsc->hwradiooff == false) && (state_toset == ERFOFF)) {
2258                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2259                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2260
2261                 state_toset = ERFOFF;
2262                 ppsc->hwradiooff = true;
2263                 actuallyset = true;
2264         }
2265
2266         if (actuallyset) {
2267                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2268                 ppsc->rfchange_inprogress = false;
2269                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2270         } else {
2271                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2272                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2273
2274                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2275                 ppsc->rfchange_inprogress = false;
2276                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2277         }
2278
2279         *valid = 1;
2280         return !ppsc->hwradiooff;
2281 }
2282
2283 static void add_one_key(struct ieee80211_hw *hw, u8 *macaddr,
2284                         struct rtl_mac *mac, u32 key, u32 id,
2285                         u8 enc_algo, bool is_pairwise)
2286 {
2287         struct rtl_priv *rtlpriv = rtl_priv(hw);
2288         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2289
2290         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "add one entry\n");
2291         if (is_pairwise) {
2292                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "set Pairwise key\n");
2293
2294                 rtl_cam_add_one_entry(hw, macaddr, key, id, enc_algo,
2295                                       CAM_CONFIG_NO_USEDK,
2296                                       rtlpriv->sec.key_buf[key]);
2297         } else {
2298                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "set group key\n");
2299
2300                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2301                         rtl_cam_add_one_entry(hw, rtlefuse->dev_addr,
2302                                               PAIRWISE_KEYIDX,
2303                                               CAM_PAIRWISE_KEY_POSITION,
2304                                               enc_algo,
2305                                               CAM_CONFIG_NO_USEDK,
2306                                               rtlpriv->sec.key_buf[id]);
2307                 }
2308
2309                 rtl_cam_add_one_entry(hw, macaddr, key, id, enc_algo,
2310                                       CAM_CONFIG_NO_USEDK,
2311                                       rtlpriv->sec.key_buf[id]);
2312         }
2313 }
2314
2315 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key,
2316                      u8 *mac_ad, bool is_group, u8 enc_algo,
2317                      bool is_wepkey, bool clear_all)
2318 {
2319         struct rtl_priv *rtlpriv = rtl_priv(hw);
2320         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2321         u8 *macaddr = mac_ad;
2322         u32 id = 0;
2323         bool is_pairwise = false;
2324
2325         static u8 cam_const_addr[4][6] = {
2326                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2327                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2328                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2329                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2330         };
2331         static u8 cam_const_broad[] = {
2332                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2333         };
2334
2335         if (clear_all) {
2336                 u8 idx = 0;
2337                 u8 cam_offset = 0;
2338                 u8 clear_number = 5;
2339
2340                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2341
2342                 for (idx = 0; idx < clear_number; idx++) {
2343                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2344                         rtl_cam_empty_entry(hw, cam_offset + idx);
2345
2346                         if (idx < 5) {
2347                                 memset(rtlpriv->sec.key_buf[idx], 0,
2348                                        MAX_KEY_LEN);
2349                                 rtlpriv->sec.key_len[idx] = 0;
2350                         }
2351                 }
2352
2353         } else {
2354                 switch (enc_algo) {
2355                 case WEP40_ENCRYPTION:
2356                         enc_algo = CAM_WEP40;
2357                         break;
2358                 case WEP104_ENCRYPTION:
2359                         enc_algo = CAM_WEP104;
2360                         break;
2361                 case TKIP_ENCRYPTION:
2362                         enc_algo = CAM_TKIP;
2363                         break;
2364                 case AESCCMP_ENCRYPTION:
2365                         enc_algo = CAM_AES;
2366                         break;
2367                 default:
2368                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2369                                  "switch case not processed\n");
2370                         enc_algo = CAM_TKIP;
2371                         break;
2372                 }
2373
2374                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2375                         macaddr = cam_const_addr[key];
2376                         id = key;
2377                 } else {
2378                         if (is_group) {
2379                                 macaddr = cam_const_broad;
2380                                 id = key;
2381                         } else {
2382                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2383                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2384                                         id = rtl_cam_get_free_entry(hw, mac_ad);
2385                                         if (id >=  TOTAL_CAM_ENTRY) {
2386                                                 RT_TRACE(rtlpriv, COMP_SEC,
2387                                                          DBG_EMERG,
2388                                                          "Can not find free hw security cam entry\n");
2389                                                 return;
2390                                         }
2391                                 } else {
2392                                         id = CAM_PAIRWISE_KEY_POSITION;
2393                                 }
2394
2395                                 key = PAIRWISE_KEYIDX;
2396                                 is_pairwise = true;
2397                         }
2398                 }
2399
2400                 if (rtlpriv->sec.key_len[key] == 0) {
2401                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2402                                  "delete one entry, id is %d\n", id);
2403                         if (mac->opmode == NL80211_IFTYPE_AP ||
2404                             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2405                                 rtl_cam_del_entry(hw, mac_ad);
2406                         rtl_cam_delete_one_entry(hw, mac_ad, id);
2407                 } else {
2408                         add_one_key(hw, macaddr, mac, key, id, enc_algo,
2409                                     is_pairwise);
2410                 }
2411         }
2412 }
2413
2414 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2415 {
2416         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2417         struct bt_coexist_info coexist = rppriv->bt_coexist;
2418
2419         coexist.bt_coexistence = rppriv->bt_coexist.eeprom_bt_coexist;
2420         coexist.bt_ant_num = coexist.eeprom_bt_ant_num;
2421         coexist.bt_coexist_type = coexist.eeprom_bt_type;
2422
2423         if (coexist.reg_bt_iso == 2)
2424                 coexist.bt_ant_isolation = coexist.eeprom_bt_ant_isol;
2425         else
2426                 coexist.bt_ant_isolation = coexist.reg_bt_iso;
2427
2428         coexist.bt_radio_shared_type = coexist.eeprom_bt_radio_shared;
2429
2430         if (coexist.bt_coexistence) {
2431                 if (coexist.reg_bt_sco == 1)
2432                         coexist.bt_service = BT_OTHER_ACTION;
2433                 else if (coexist.reg_bt_sco == 2)
2434                         coexist.bt_service = BT_SCO;
2435                 else if (coexist.reg_bt_sco == 4)
2436                         coexist.bt_service = BT_BUSY;
2437                 else if (coexist.reg_bt_sco == 5)
2438                         coexist.bt_service = BT_OTHERBUSY;
2439                 else
2440                         coexist.bt_service = BT_IDLE;
2441
2442                 coexist.bt_edca_ul = 0;
2443                 coexist.bt_edca_dl = 0;
2444                 coexist.bt_rssi_state = 0xff;
2445         }
2446 }
2447
2448 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2449                                               bool auto_load_fail, u8 *hwinfo)
2450 {
2451         rtl8188ee_bt_var_init(hw);
2452 }
2453
2454 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2455 {
2456         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2457
2458         /* 0:Low, 1:High, 2:From Efuse. */
2459         rppriv->bt_coexist.reg_bt_iso = 2;
2460         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2461         rppriv->bt_coexist.reg_bt_sco = 3;
2462         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2463         rppriv->bt_coexist.reg_bt_sco = 0;
2464 }
2465
2466 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2467 {
2468         struct rtl_priv *rtlpriv = rtl_priv(hw);
2469         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2470         struct rtl_pci_priv *rppriv = rtl_pcipriv(hw);
2471         struct bt_coexist_info coexist = rppriv->bt_coexist;
2472         u8 u1_tmp;
2473
2474         if (coexist.bt_coexistence &&
2475             ((coexist.bt_coexist_type == BT_CSR_BC4) ||
2476               coexist.bt_coexist_type == BT_CSR_BC8)) {
2477                 if (coexist.bt_ant_isolation)
2478                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2479
2480                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2481                                        BIT_OFFSET_LEN_MASK_32(0, 1);
2482                 u1_tmp = u1_tmp | ((coexist.bt_ant_isolation == 1) ?
2483                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2484                          ((coexist.bt_service == BT_SCO) ?
2485                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2486                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2487
2488                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2489                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2490                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2491
2492                 /* Config to 1T1R. */
2493                 if (rtlphy->rf_type == RF_1T1R) {
2494                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2495                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2496                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2497
2498                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2499                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2500                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2501                 }
2502         }
2503 }
2504
2505 void rtl88ee_suspend(struct ieee80211_hw *hw)
2506 {
2507 }
2508
2509 void rtl88ee_resume(struct ieee80211_hw *hw)
2510 {
2511 }
2512
2513 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2514 void rtl88ee_allow_all_destaddr(struct ieee80211_hw *hw,
2515                                 bool allow_all_da, bool write_into_reg)
2516 {
2517         struct rtl_priv *rtlpriv = rtl_priv(hw);
2518         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2519
2520         if (allow_all_da) /* Set BIT0 */
2521                 rtlpci->receive_config |= RCR_AAP;
2522          else /* Clear BIT0 */
2523                 rtlpci->receive_config &= ~RCR_AAP;
2524
2525         if (write_into_reg)
2526                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2527
2528         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2529                  "receive_config = 0x%08X, write_into_reg =%d\n",
2530                  rtlpci->receive_config, write_into_reg);
2531 }