drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include <linux/export.h>
  31 #include "dm_common.h"
  32 #include "phy_common.h"
  33 #include "../pci.h"
  34 #include "../base.h"
  35
  36 #define BT_RSSI_STATE_NORMAL_POWER      BIT_OFFSET_LEN_MASK_32(0, 1)
  37 #define BT_RSSI_STATE_AMDPU_OFF         BIT_OFFSET_LEN_MASK_32(1, 1)
  38 #define BT_RSSI_STATE_SPECIAL_LOW       BIT_OFFSET_LEN_MASK_32(2, 1)
  39 #define BT_RSSI_STATE_BG_EDCA_LOW       BIT_OFFSET_LEN_MASK_32(3, 1)
  40 #define BT_RSSI_STATE_TXPOWER_LOW       BIT_OFFSET_LEN_MASK_32(4, 1)
  41
  42 #define RTLPRIV                 (struct rtl_priv *)
  43 #define GET_UNDECORATED_AVERAGE_RSSI(_priv)     \
  44         ((RTLPRIV(_priv))->mac80211.opmode == \
  45                              NL80211_IFTYPE_ADHOC) ?    \
  46         ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \
  47         ((RTLPRIV(_priv))->dm.undec_sm_pwdb)
  48
  49 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  50         0x7f8001fe,
  51         0x788001e2,
  52         0x71c001c7,
  53         0x6b8001ae,
  54         0x65400195,
  55         0x5fc0017f,
  56         0x5a400169,
  57         0x55400155,
  58         0x50800142,
  59         0x4c000130,
  60         0x47c0011f,
  61         0x43c0010f,
  62         0x40000100,
  63         0x3c8000f2,
  64         0x390000e4,
  65         0x35c000d7,
  66         0x32c000cb,
  67         0x300000c0,
  68         0x2d4000b5,
  69         0x2ac000ab,
  70         0x288000a2,
  71         0x26000098,
  72         0x24000090,
  73         0x22000088,
  74         0x20000080,
  75         0x1e400079,
  76         0x1c800072,
  77         0x1b00006c,
  78         0x19800066,
  79         0x18000060,
  80         0x16c0005b,
  81         0x15800056,
  82         0x14400051,
  83         0x1300004c,
  84         0x12000048,
  85         0x11000044,
  86         0x10000040,
  87 };
  88
  89 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  90         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  91         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  92         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  93         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  94         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  95         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  96         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  97         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  98         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  99         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
 100         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
 101         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
 102         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
 103         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
 104         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
 105         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
 106         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
 107         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
 108         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
 109         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
 110         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
 111         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
 112         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
 113         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
 114         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
 115         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
 116         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
 117         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
 118         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
 119         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
 120         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
 121         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
 122         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
 123 };
 124
 125 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
 126         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
 127         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
 128         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
 129         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
 130         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
 131         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
 132         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
 133         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
 134         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
 135         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
 136         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
 137         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
 138         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
 139         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
 140         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
 141         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
 142         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
 143         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
 144         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
 145         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 146         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 147         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
 148         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
 149         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
 150         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
 151         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
 152         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
 153         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
 154         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
 155         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
 156         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
 157         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
 158         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
 159 };
 160
 161 static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
 162 {
 163         struct rtl_priv *rtlpriv = rtl_priv(hw);
 164         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 165
 166         dm_digtable->dig_enable_flag = true;
 167         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 168         dm_digtable->cur_igvalue = 0x20;
 169         dm_digtable->pre_igvalue = 0x0;
 170         dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
 171         dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
 172         dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
 173         dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
 174         dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
 175         dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
 176         dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
 177         dm_digtable->rx_gain_max = DM_DIG_MAX;
 178         dm_digtable->rx_gain_min = DM_DIG_MIN;
 179         dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
 180         dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
 181         dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
 182         dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
 183         dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
 184 }
 185
 186 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
 187 {
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 190         long rssi_val_min = 0;
 191
 192         if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
 193             (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
 194                 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
 195                         rssi_val_min =
 196                             (rtlpriv->dm.entry_min_undec_sm_pwdb >
 197                              rtlpriv->dm.undec_sm_pwdb) ?
 198                             rtlpriv->dm.undec_sm_pwdb :
 199                             rtlpriv->dm.entry_min_undec_sm_pwdb;
 200                 else
 201                         rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 202         } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
 203                    dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
 204                 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 205         } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
 206                 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
 207         }
 208
 209         return (u8) rssi_val_min;
 210 }
 211
 212 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
 213 {
 214         u32 ret_value;
 215         struct rtl_priv *rtlpriv = rtl_priv(hw);
 216         struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
 217
 218         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
 219         falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
 220
 221         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
 222         falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
 223         falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
 224
 225         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
 226         falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
 227         falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
 228             falsealm_cnt->cnt_rate_illegal +
 229             falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
 230
 231         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
 232         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
 233         falsealm_cnt->cnt_cck_fail = ret_value;
 234
 235         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
 236         falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
 237         falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
 238                                  falsealm_cnt->cnt_rate_illegal +
 239                                  falsealm_cnt->cnt_crc8_fail +
 240                                  falsealm_cnt->cnt_mcs_fail +
 241                                  falsealm_cnt->cnt_cck_fail);
 242
 243         rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
 244         rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
 245         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
 246         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
 247
 248         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 249                  "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
 250                  falsealm_cnt->cnt_parity_fail,
 251                  falsealm_cnt->cnt_rate_illegal,
 252                  falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
 253
 254         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 255                  "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
 256                  falsealm_cnt->cnt_ofdm_fail,
 257                  falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
 258 }
 259
 260 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
 261 {
 262         struct rtl_priv *rtlpriv = rtl_priv(hw);
 263         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 264         u8 value_igi = dm_digtable->cur_igvalue;
 265
 266         if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
 267                 value_igi--;
 268         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
 269                 value_igi += 0;
 270         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
 271                 value_igi++;
 272         else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
 273                 value_igi += 2;
 274         if (value_igi > DM_DIG_FA_UPPER)
 275                 value_igi = DM_DIG_FA_UPPER;
 276         else if (value_igi < DM_DIG_FA_LOWER)
 277                 value_igi = DM_DIG_FA_LOWER;
 278         if (rtlpriv->falsealm_cnt.cnt_all > 10000)
 279                 value_igi = 0x32;
 280
 281         dm_digtable->cur_igvalue = value_igi;
 282         rtl92c_dm_write_dig(hw);
 283 }
 284
 285 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
 286 {
 287         struct rtl_priv *rtlpriv = rtl_priv(hw);
 288         struct dig_t *digtable = &rtlpriv->dm_digtable;
 289
 290         if (rtlpriv->falsealm_cnt.cnt_all > digtable->fa_highthresh) {
 291                 if ((digtable->back_val - 2) < digtable->back_range_min)
 292                         digtable->back_val = digtable->back_range_min;
 293                 else
 294                         digtable->back_val -= 2;
 295         } else if (rtlpriv->falsealm_cnt.cnt_all < digtable->fa_lowthresh) {
 296                 if ((digtable->back_val + 2) > digtable->back_range_max)
 297                         digtable->back_val = digtable->back_range_max;
 298                 else
 299                         digtable->back_val += 2;
 300         }
 301
 302         if ((digtable->rssi_val_min + 10 - digtable->back_val) >
 303             digtable->rx_gain_max)
 304                 digtable->cur_igvalue = digtable->rx_gain_max;
 305         else if ((digtable->rssi_val_min + 10 -
 306                   digtable->back_val) < digtable->rx_gain_min)
 307                 digtable->cur_igvalue = digtable->rx_gain_min;
 308         else
 309                 digtable->cur_igvalue = digtable->rssi_val_min + 10 -
 310                     digtable->back_val;
 311
 312         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 313                  "rssi_val_min = %x back_val %x\n",
 314                  digtable->rssi_val_min, digtable->back_val);
 315
 316         rtl92c_dm_write_dig(hw);
 317 }
 318
 319 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
 320 {
 321         static u8 initialized; /* initialized to false */
 322         struct rtl_priv *rtlpriv = rtl_priv(hw);
 323         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 324         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 325         long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
 326         bool multi_sta = false;
 327
 328         if (mac->opmode == NL80211_IFTYPE_ADHOC)
 329                 multi_sta = true;
 330
 331         if (!multi_sta ||
 332             dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
 333                 initialized = false;
 334                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 335                 return;
 336         } else if (initialized == false) {
 337                 initialized = true;
 338                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
 339                 dm_digtable->cur_igvalue = 0x20;
 340                 rtl92c_dm_write_dig(hw);
 341         }
 342
 343         if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
 344                 if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
 345                     (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
 346
 347                         if (dm_digtable->dig_ext_port_stage ==
 348                             DIG_EXT_PORT_STAGE_2) {
 349                                 dm_digtable->cur_igvalue = 0x20;
 350                                 rtl92c_dm_write_dig(hw);
 351                         }
 352
 353                         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
 354                 } else if (rssi_strength > dm_digtable->rssi_highthresh) {
 355                         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
 356                         rtl92c_dm_ctrl_initgain_by_fa(hw);
 357                 }
 358         } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
 359                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
 360                 dm_digtable->cur_igvalue = 0x20;
 361                 rtl92c_dm_write_dig(hw);
 362         }
 363
 364         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 365                  "curmultista_cstate = %x dig_ext_port_stage %x\n",
 366                  dm_digtable->curmultista_cstate,
 367                  dm_digtable->dig_ext_port_stage);
 368 }
 369
 370 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
 371 {
 372         struct rtl_priv *rtlpriv = rtl_priv(hw);
 373         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 374
 375         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 376                  "presta_cstate = %x, cursta_cstate = %x\n",
 377                  dm_digtable->presta_cstate, dm_digtable->cursta_cstate);
 378
 379         if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
 380             dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
 381             dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
 382
 383                 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
 384                         dm_digtable->rssi_val_min =
 385                             rtl92c_dm_initial_gain_min_pwdb(hw);
 386                         rtl92c_dm_ctrl_initgain_by_rssi(hw);
 387                 }
 388         } else {
 389                 dm_digtable->rssi_val_min = 0;
 390                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 391                 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
 392                 dm_digtable->cur_igvalue = 0x20;
 393                 dm_digtable->pre_igvalue = 0;
 394                 rtl92c_dm_write_dig(hw);
 395         }
 396 }
 397
 398 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
 399 {
 400         struct rtl_priv *rtlpriv = rtl_priv(hw);
 401         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 402         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 403
 404         if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
 405                 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
 406
 407                 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
 408                         if (dm_digtable->rssi_val_min <= 25)
 409                                 dm_digtable->cur_cck_pd_state =
 410                                     CCK_PD_STAGE_LowRssi;
 411                         else
 412                                 dm_digtable->cur_cck_pd_state =
 413                                     CCK_PD_STAGE_HighRssi;
 414                 } else {
 415                         if (dm_digtable->rssi_val_min <= 20)
 416                                 dm_digtable->cur_cck_pd_state =
 417                                     CCK_PD_STAGE_LowRssi;
 418                         else
 419                                 dm_digtable->cur_cck_pd_state =
 420                                     CCK_PD_STAGE_HighRssi;
 421                 }
 422         } else {
 423                 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
 424         }
 425
 426         if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
 427                 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
 428                         if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
 429                                 dm_digtable->cur_cck_fa_state =
 430                                     CCK_FA_STAGE_High;
 431                         else
 432                                 dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low;
 433
 434                         if (dm_digtable->pre_cck_fa_state !=
 435                             dm_digtable->cur_cck_fa_state) {
 436                                 if (dm_digtable->cur_cck_fa_state ==
 437                                     CCK_FA_STAGE_Low)
 438                                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
 439                                                       0x83);
 440                                 else
 441                                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
 442                                                       0xcd);
 443
 444                                 dm_digtable->pre_cck_fa_state =
 445                                     dm_digtable->cur_cck_fa_state;
 446                         }
 447
 448                         rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
 449
 450                         if (IS_92C_SERIAL(rtlhal->version))
 451                                 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
 452                                               MASKBYTE2, 0xd7);
 453                 } else {
 454                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
 455                         rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
 456
 457                         if (IS_92C_SERIAL(rtlhal->version))
 458                                 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
 459                                               MASKBYTE2, 0xd3);
 460                 }
 461                 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
 462         }
 463
 464         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
 465                  dm_digtable->cur_cck_pd_state);
 466
 467         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
 468                  IS_92C_SERIAL(rtlhal->version));
 469 }
 470
 471 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
 472 {
 473         struct rtl_priv *rtlpriv = rtl_priv(hw);
 474         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 475         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 476
 477         if (mac->act_scanning)
 478                 return;
 479
 480         if (mac->link_state >= MAC80211_LINKED)
 481                 dm_digtable->cursta_cstate = DIG_STA_CONNECT;
 482         else
 483                 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
 484
 485         rtl92c_dm_initial_gain_sta(hw);
 486         rtl92c_dm_initial_gain_multi_sta(hw);
 487         rtl92c_dm_cck_packet_detection_thresh(hw);
 488
 489         dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
 490
 491 }
 492
 493 static void rtl92c_dm_dig(struct ieee80211_hw *hw)
 494 {
 495         struct rtl_priv *rtlpriv = rtl_priv(hw);
 496         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 497
 498         if (rtlpriv->dm.dm_initialgain_enable == false)
 499                 return;
 500         if (dm_digtable->dig_enable_flag == false)
 501                 return;
 502
 503         rtl92c_dm_ctrl_initgain_by_twoport(hw);
 504
 505 }
 506
 507 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
 508 {
 509         struct rtl_priv *rtlpriv = rtl_priv(hw);
 510
 511         rtlpriv->dm.dynamic_txpower_enable = false;
 512
 513         rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
 514         rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 515 }
 516
 517 void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
 518 {
 519         struct rtl_priv *rtlpriv = rtl_priv(hw);
 520         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 521
 522         RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
 523                  "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
 524                  dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
 525                  dm_digtable->back_val);
 526
 527         dm_digtable->cur_igvalue += 2;
 528         if (dm_digtable->cur_igvalue > 0x3f)
 529                 dm_digtable->cur_igvalue = 0x3f;
 530
 531         if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
 532                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
 533                               dm_digtable->cur_igvalue);
 534                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
 535                               dm_digtable->cur_igvalue);
 536
 537                 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
 538         }
 539 }
 540 EXPORT_SYMBOL(rtl92c_dm_write_dig);
 541
 542 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
 543 {
 544 }
 545
 546 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
 547 {
 548         struct rtl_priv *rtlpriv = rtl_priv(hw);
 549         rtlpriv->dm.current_turbo_edca = false;
 550         rtlpriv->dm.is_any_nonbepkts = false;
 551         rtlpriv->dm.is_cur_rdlstate = false;
 552 }
 553 EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
 554
 555 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
 556 {
 557         struct rtl_priv *rtlpriv = rtl_priv(hw);
 558         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 559         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 560
 561         static u64 last_txok_cnt;
 562         static u64 last_rxok_cnt;
 563         static u32 last_bt_edca_ul;
 564         static u32 last_bt_edca_dl;
 565         u64 cur_txok_cnt = 0;
 566         u64 cur_rxok_cnt = 0;
 567         u32 edca_be_ul = 0x5ea42b;
 568         u32 edca_be_dl = 0x5ea42b;
 569         bool bt_change_edca = false;
 570
 571         if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
 572             (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
 573                 rtlpriv->dm.current_turbo_edca = false;
 574                 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
 575                 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
 576         }
 577
 578         if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
 579                 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
 580                 bt_change_edca = true;
 581         }
 582
 583         if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
 584                 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
 585                 bt_change_edca = true;
 586         }
 587
 588         if (mac->link_state != MAC80211_LINKED) {
 589                 rtlpriv->dm.current_turbo_edca = false;
 590                 return;
 591         }
 592
 593         if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
 594                 if (!(edca_be_ul & 0xffff0000))
 595                         edca_be_ul |= 0x005e0000;
 596
 597                 if (!(edca_be_dl & 0xffff0000))
 598                         edca_be_dl |= 0x005e0000;
 599         }
 600
 601         if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
 602              (!rtlpriv->dm.disable_framebursting))) {
 603
 604                 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
 605                 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
 606
 607                 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
 608                         if (!rtlpriv->dm.is_cur_rdlstate ||
 609                             !rtlpriv->dm.current_turbo_edca) {
 610                                 rtl_write_dword(rtlpriv,
 611                                                 REG_EDCA_BE_PARAM,
 612                                                 edca_be_dl);
 613                                 rtlpriv->dm.is_cur_rdlstate = true;
 614                         }
 615                 } else {
 616                         if (rtlpriv->dm.is_cur_rdlstate ||
 617                             !rtlpriv->dm.current_turbo_edca) {
 618                                 rtl_write_dword(rtlpriv,
 619                                                 REG_EDCA_BE_PARAM,
 620                                                 edca_be_ul);
 621                                 rtlpriv->dm.is_cur_rdlstate = false;
 622                         }
 623                 }
 624                 rtlpriv->dm.current_turbo_edca = true;
 625         } else {
 626                 if (rtlpriv->dm.current_turbo_edca) {
 627                         u8 tmp = AC0_BE;
 628                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 629                                                       &tmp);
 630                         rtlpriv->dm.current_turbo_edca = false;
 631                 }
 632         }
 633
 634         rtlpriv->dm.is_any_nonbepkts = false;
 635         last_txok_cnt = rtlpriv->stats.txbytesunicast;
 636         last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
 637 }
 638
 639 static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
 640                                                              *hw)
 641 {
 642         struct rtl_priv *rtlpriv = rtl_priv(hw);
 643         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 644         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 645         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 646         u8 thermalvalue, delta, delta_lck, delta_iqk;
 647         long ele_a, ele_d, temp_cck, val_x, value32;
 648         long val_y, ele_c = 0;
 649         u8 ofdm_index[2], ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
 650         s8 cck_index = 0;
 651         int i;
 652         bool is2t = IS_92C_SERIAL(rtlhal->version);
 653         s8 txpwr_level[3] = {0, 0, 0};
 654         u8 ofdm_min_index = 6, rf;
 655
 656         rtlpriv->dm.txpower_trackinginit = true;
 657         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 658                  "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
 659
 660         thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
 661
 662         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 663                  "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
 664                  thermalvalue, rtlpriv->dm.thermalvalue,
 665                  rtlefuse->eeprom_thermalmeter);
 666
 667         rtl92c_phy_ap_calibrate(hw, (thermalvalue -
 668                                      rtlefuse->eeprom_thermalmeter));
 669         if (is2t)
 670                 rf = 2;
 671         else
 672                 rf = 1;
 673
 674         if (thermalvalue) {
 675                 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 676                                       MASKDWORD) & MASKOFDM_D;
 677
 678                 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
 679                         if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
 680                                 ofdm_index_old[0] = (u8) i;
 681
 682                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 683                                          "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
 684                                          ROFDM0_XATXIQIMBALANCE,
 685                                          ele_d, ofdm_index_old[0]);
 686                                 break;
 687                         }
 688                 }
 689
 690                 if (is2t) {
 691                         ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
 692                                               MASKDWORD) & MASKOFDM_D;
 693
 694                         for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
 695                                 if (ele_d == (ofdmswing_table[i] &
 696                                     MASKOFDM_D)) {
 697                                         ofdm_index_old[1] = (u8) i;
 698                                         RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 699                                                  DBG_LOUD,
 700                                                  "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
 701                                                  ROFDM0_XBTXIQIMBALANCE, ele_d,
 702                                                  ofdm_index_old[1]);
 703                                         break;
 704                                 }
 705                         }
 706                 }
 707
 708                 temp_cck =
 709                     rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
 710
 711                 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
 712                         if (rtlpriv->dm.cck_inch14) {
 713                                 if (memcmp((void *)&temp_cck,
 714                                            (void *)&cckswing_table_ch14[i][2],
 715                                            4) == 0) {
 716                                         cck_index_old = (u8) i;
 717
 718                                         RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 719                                                  DBG_LOUD,
 720                                                  "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
 721                                                  RCCK0_TXFILTER2, temp_cck,
 722                                                  cck_index_old,
 723                                                  rtlpriv->dm.cck_inch14);
 724                                         break;
 725                                 }
 726                         } else {
 727                                 if (memcmp((void *)&temp_cck,
 728                                            (void *)
 729                                            &cckswing_table_ch1ch13[i][2],
 730                                            4) == 0) {
 731                                         cck_index_old = (u8) i;
 732
 733                                         RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 734                                                  DBG_LOUD,
 735                                                  "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
 736                                                  RCCK0_TXFILTER2, temp_cck,
 737                                                  cck_index_old,
 738                                                  rtlpriv->dm.cck_inch14);
 739                                         break;
 740                                 }
 741                         }
 742                 }
 743
 744                 if (!rtlpriv->dm.thermalvalue) {
 745                         rtlpriv->dm.thermalvalue =
 746                             rtlefuse->eeprom_thermalmeter;
 747                         rtlpriv->dm.thermalvalue_lck = thermalvalue;
 748                         rtlpriv->dm.thermalvalue_iqk = thermalvalue;
 749                         for (i = 0; i < rf; i++)
 750                                 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
 751                         rtlpriv->dm.cck_index = cck_index_old;
 752                 }
 753
 754                 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
 755                     (thermalvalue - rtlpriv->dm.thermalvalue) :
 756                     (rtlpriv->dm.thermalvalue - thermalvalue);
 757
 758                 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
 759                     (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
 760                     (rtlpriv->dm.thermalvalue_lck - thermalvalue);
 761
 762                 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
 763                     (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
 764                     (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
 765
 766                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 767                          "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
 768                          thermalvalue, rtlpriv->dm.thermalvalue,
 769                          rtlefuse->eeprom_thermalmeter, delta, delta_lck,
 770                          delta_iqk);
 771
 772                 if (delta_lck > 1) {
 773                         rtlpriv->dm.thermalvalue_lck = thermalvalue;
 774                         rtl92c_phy_lc_calibrate(hw);
 775                 }
 776
 777                 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
 778                         if (thermalvalue > rtlpriv->dm.thermalvalue) {
 779                                 for (i = 0; i < rf; i++)
 780                                         rtlpriv->dm.ofdm_index[i] -= delta;
 781                                 rtlpriv->dm.cck_index -= delta;
 782                         } else {
 783                                 for (i = 0; i < rf; i++)
 784                                         rtlpriv->dm.ofdm_index[i] += delta;
 785                                 rtlpriv->dm.cck_index += delta;
 786                         }
 787
 788                         if (is2t) {
 789                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 790                                          "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
 791                                          rtlpriv->dm.ofdm_index[0],
 792                                          rtlpriv->dm.ofdm_index[1],
 793                                          rtlpriv->dm.cck_index);
 794                         } else {
 795                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 796                                          "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
 797                                          rtlpriv->dm.ofdm_index[0],
 798                                          rtlpriv->dm.cck_index);
 799                         }
 800
 801                         if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
 802                                 for (i = 0; i < rf; i++)
 803                                         ofdm_index[i] =
 804                                             rtlpriv->dm.ofdm_index[i]
 805                                             + 1;
 806                                 cck_index = rtlpriv->dm.cck_index + 1;
 807                         } else {
 808                                 for (i = 0; i < rf; i++)
 809                                         ofdm_index[i] =
 810                                             rtlpriv->dm.ofdm_index[i];
 811                                 cck_index = rtlpriv->dm.cck_index;
 812                         }
 813
 814                         for (i = 0; i < rf; i++) {
 815                                 if (txpwr_level[i] >= 0 &&
 816                                     txpwr_level[i] <= 26) {
 817                                         if (thermalvalue >
 818                                             rtlefuse->eeprom_thermalmeter) {
 819                                                 if (delta < 5)
 820                                                         ofdm_index[i] -= 1;
 821
 822                                                 else
 823                                                         ofdm_index[i] -= 2;
 824                                         } else if (delta > 5 && thermalvalue <
 825                                                    rtlefuse->
 826                                                    eeprom_thermalmeter) {
 827                                                 ofdm_index[i] += 1;
 828                                         }
 829                                 } else if (txpwr_level[i] >= 27 &&
 830                                            txpwr_level[i] <= 32
 831                                            && thermalvalue >
 832                                            rtlefuse->eeprom_thermalmeter) {
 833                                         if (delta < 5)
 834                                                 ofdm_index[i] -= 1;
 835
 836                                         else
 837                                                 ofdm_index[i] -= 2;
 838                                 } else if (txpwr_level[i] >= 32 &&
 839                                            txpwr_level[i] <= 38 &&
 840                                            thermalvalue >
 841                                            rtlefuse->eeprom_thermalmeter
 842                                            && delta > 5) {
 843                                         ofdm_index[i] -= 1;
 844                                 }
 845                         }
 846
 847                         if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
 848                                 if (thermalvalue >
 849                                     rtlefuse->eeprom_thermalmeter) {
 850                                         if (delta < 5)
 851                                                 cck_index -= 1;
 852
 853                                         else
 854                                                 cck_index -= 2;
 855                                 } else if (delta > 5 && thermalvalue <
 856                                            rtlefuse->eeprom_thermalmeter) {
 857                                         cck_index += 1;
 858                                 }
 859                         } else if (txpwr_level[i] >= 27 &&
 860                                    txpwr_level[i] <= 32 &&
 861                                    thermalvalue >
 862                                    rtlefuse->eeprom_thermalmeter) {
 863                                 if (delta < 5)
 864                                         cck_index -= 1;
 865
 866                                 else
 867                                         cck_index -= 2;
 868                         } else if (txpwr_level[i] >= 32 &&
 869                                    txpwr_level[i] <= 38 &&
 870                                    thermalvalue > rtlefuse->eeprom_thermalmeter
 871                                    && delta > 5) {
 872                                 cck_index -= 1;
 873                         }
 874
 875                         for (i = 0; i < rf; i++) {
 876                                 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
 877                                         ofdm_index[i] = OFDM_TABLE_SIZE - 1;
 878
 879                                 else if (ofdm_index[i] < ofdm_min_index)
 880                                         ofdm_index[i] = ofdm_min_index;
 881                         }
 882
 883                         if (cck_index > CCK_TABLE_SIZE - 1)
 884                                 cck_index = CCK_TABLE_SIZE - 1;
 885                         else if (cck_index < 0)
 886                                 cck_index = 0;
 887
 888                         if (is2t) {
 889                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 890                                          "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
 891                                          ofdm_index[0], ofdm_index[1],
 892                                          cck_index);
 893                         } else {
 894                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 895                                          "new OFDM_A_index=0x%x, cck_index=0x%x\n",
 896                                          ofdm_index[0], cck_index);
 897                         }
 898                 }
 899
 900                 if (rtlpriv->dm.txpower_track_control && delta != 0) {
 901                         ele_d =
 902                             (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
 903                         val_x = rtlphy->reg_e94;
 904                         val_y = rtlphy->reg_e9c;
 905
 906                         if (val_x != 0) {
 907                                 if ((val_x & 0x00000200) != 0)
 908                                         val_x = val_x | 0xFFFFFC00;
 909                                 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
 910
 911                                 if ((val_y & 0x00000200) != 0)
 912                                         val_y = val_y | 0xFFFFFC00;
 913                                 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
 914
 915                                 value32 = (ele_d << 22) |
 916                                     ((ele_c & 0x3F) << 16) | ele_a;
 917
 918                                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 919                                               MASKDWORD, value32);
 920
 921                                 value32 = (ele_c & 0x000003C0) >> 6;
 922                                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
 923                                               value32);
 924
 925                                 value32 = ((val_x * ele_d) >> 7) & 0x01;
 926                                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 927                                               BIT(31), value32);
 928
 929                                 value32 = ((val_y * ele_d) >> 7) & 0x01;
 930                                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 931                                               BIT(29), value32);
 932                         } else {
 933                                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 934                                               MASKDWORD,
 935                                               ofdmswing_table[ofdm_index[0]]);
 936
 937                                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
 938                                               0x00);
 939                                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 940                                               BIT(31) | BIT(29), 0x00);
 941                         }
 942
 943                         if (!rtlpriv->dm.cck_inch14) {
 944                                 rtl_write_byte(rtlpriv, 0xa22,
 945                                                cckswing_table_ch1ch13[cck_index]
 946                                                [0]);
 947                                 rtl_write_byte(rtlpriv, 0xa23,
 948                                                cckswing_table_ch1ch13[cck_index]
 949                                                [1]);
 950                                 rtl_write_byte(rtlpriv, 0xa24,
 951                                                cckswing_table_ch1ch13[cck_index]
 952                                                [2]);
 953                                 rtl_write_byte(rtlpriv, 0xa25,
 954                                                cckswing_table_ch1ch13[cck_index]
 955                                                [3]);
 956                                 rtl_write_byte(rtlpriv, 0xa26,
 957                                                cckswing_table_ch1ch13[cck_index]
 958                                                [4]);
 959                                 rtl_write_byte(rtlpriv, 0xa27,
 960                                                cckswing_table_ch1ch13[cck_index]
 961                                                [5]);
 962                                 rtl_write_byte(rtlpriv, 0xa28,
 963                                                cckswing_table_ch1ch13[cck_index]
 964                                                [6]);
 965                                 rtl_write_byte(rtlpriv, 0xa29,
 966                                                cckswing_table_ch1ch13[cck_index]
 967                                                [7]);
 968                         } else {
 969                                 rtl_write_byte(rtlpriv, 0xa22,
 970                                                cckswing_table_ch14[cck_index]
 971                                                [0]);
 972                                 rtl_write_byte(rtlpriv, 0xa23,
 973                                                cckswing_table_ch14[cck_index]
 974                                                [1]);
 975                                 rtl_write_byte(rtlpriv, 0xa24,
 976                                                cckswing_table_ch14[cck_index]
 977                                                [2]);
 978                                 rtl_write_byte(rtlpriv, 0xa25,
 979                                                cckswing_table_ch14[cck_index]
 980                                                [3]);
 981                                 rtl_write_byte(rtlpriv, 0xa26,
 982                                                cckswing_table_ch14[cck_index]
 983                                                [4]);
 984                                 rtl_write_byte(rtlpriv, 0xa27,
 985                                                cckswing_table_ch14[cck_index]
 986                                                [5]);
 987                                 rtl_write_byte(rtlpriv, 0xa28,
 988                                                cckswing_table_ch14[cck_index]
 989                                                [6]);
 990                                 rtl_write_byte(rtlpriv, 0xa29,
 991                                                cckswing_table_ch14[cck_index]
 992                                                [7]);
 993                         }
 994
 995                         if (is2t) {
 996                                 ele_d = (ofdmswing_table[ofdm_index[1]] &
 997                                          0xFFC00000) >> 22;
 998
 999                                 val_x = rtlphy->reg_eb4;
1000                                 val_y = rtlphy->reg_ebc;
1001
1002                                 if (val_x != 0) {
1003                                         if ((val_x & 0x00000200) != 0)
1004                                                 val_x = val_x | 0xFFFFFC00;
1005                                         ele_a = ((val_x * ele_d) >> 8) &
1006                                             0x000003FF;
1007
1008                                         if ((val_y & 0x00000200) != 0)
1009                                                 val_y = val_y | 0xFFFFFC00;
1010                                         ele_c = ((val_y * ele_d) >> 8) &
1011                                             0x00003FF;
1012
1013                                         value32 = (ele_d << 22) |
1014                                             ((ele_c & 0x3F) << 16) | ele_a;
1015                                         rtl_set_bbreg(hw,
1016                                                       ROFDM0_XBTXIQIMBALANCE,
1017                                                       MASKDWORD, value32);
1018
1019                                         value32 = (ele_c & 0x000003C0) >> 6;
1020                                         rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1021                                                       MASKH4BITS, value32);
1022
1023                                         value32 = ((val_x * ele_d) >> 7) & 0x01;
1024                                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1025                                                       BIT(27), value32);
1026
1027                                         value32 = ((val_y * ele_d) >> 7) & 0x01;
1028                                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1029                                                       BIT(25), value32);
1030                                 } else {
1031                                         rtl_set_bbreg(hw,
1032                                                       ROFDM0_XBTXIQIMBALANCE,
1033                                                       MASKDWORD,
1034                                                       ofdmswing_table[ofdm_index
1035                                                                       [1]]);
1036                                         rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1037                                                       MASKH4BITS, 0x00);
1038                                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1039                                                       BIT(27) | BIT(25), 0x00);
1040                                 }
1041
1042                         }
1043                 }
1044
1045                 if (delta_iqk > 3) {
1046                         rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1047                         rtl92c_phy_iq_calibrate(hw, false);
1048                 }
1049
1050                 if (rtlpriv->dm.txpower_track_control)
1051                         rtlpriv->dm.thermalvalue = thermalvalue;
1052         }
1053
1054         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
1055
1056 }
1057
1058 static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1059                                                 struct ieee80211_hw *hw)
1060 {
1061         struct rtl_priv *rtlpriv = rtl_priv(hw);
1062
1063         rtlpriv->dm.txpower_tracking = true;
1064         rtlpriv->dm.txpower_trackinginit = false;
1065
1066         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1067                  "pMgntInfo->txpower_tracking = %d\n",
1068                  rtlpriv->dm.txpower_tracking);
1069 }
1070
1071 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1072 {
1073         rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1074 }
1075
1076 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1077 {
1078         rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1079 }
1080
1081 static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1082                                                 struct ieee80211_hw *hw)
1083 {
1084         struct rtl_priv *rtlpriv = rtl_priv(hw);
1085         static u8 tm_trigger;
1086
1087         if (!rtlpriv->dm.txpower_tracking)
1088                 return;
1089
1090         if (!tm_trigger) {
1091                 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1092                               0x60);
1093                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1094                          "Trigger 92S Thermal Meter!!\n");
1095                 tm_trigger = 1;
1096                 return;
1097         } else {
1098                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1099                          "Schedule TxPowerTracking direct call!!\n");
1100                 rtl92c_dm_txpower_tracking_directcall(hw);
1101                 tm_trigger = 0;
1102         }
1103 }
1104
1105 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1106 {
1107         rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1108 }
1109 EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
1110
1111 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1112 {
1113         struct rtl_priv *rtlpriv = rtl_priv(hw);
1114         struct rate_adaptive *p_ra = &(rtlpriv->ra);
1115
1116         p_ra->ratr_state = DM_RATR_STA_INIT;
1117         p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1118
1119         if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1120                 rtlpriv->dm.useramask = true;
1121         else
1122                 rtlpriv->dm.useramask = false;
1123
1124 }
1125 EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
1126
1127 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1128 {
1129         struct rtl_priv *rtlpriv = rtl_priv(hw);
1130         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1131
1132         dm_pstable->pre_ccastate = CCA_MAX;
1133         dm_pstable->cur_ccasate = CCA_MAX;
1134         dm_pstable->pre_rfstate = RF_MAX;
1135         dm_pstable->cur_rfstate = RF_MAX;
1136         dm_pstable->rssi_val_min = 0;
1137 }
1138
1139 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1140 {
1141         struct rtl_priv *rtlpriv = rtl_priv(hw);
1142         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1143         static u8 initialize;
1144         static u32 reg_874, reg_c70, reg_85c, reg_a74;
1145
1146         if (initialize == 0) {
1147                 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1148                                          MASKDWORD) & 0x1CC000) >> 14;
1149
1150                 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1151                                          MASKDWORD) & BIT(3)) >> 3;
1152
1153                 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1154                                          MASKDWORD) & 0xFF000000) >> 24;
1155
1156                 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1157
1158                 initialize = 1;
1159         }
1160
1161         if (!bforce_in_normal) {
1162                 if (dm_pstable->rssi_val_min != 0) {
1163                         if (dm_pstable->pre_rfstate == RF_NORMAL) {
1164                                 if (dm_pstable->rssi_val_min >= 30)
1165                                         dm_pstable->cur_rfstate = RF_SAVE;
1166                                 else
1167                                         dm_pstable->cur_rfstate = RF_NORMAL;
1168                         } else {
1169                                 if (dm_pstable->rssi_val_min <= 25)
1170                                         dm_pstable->cur_rfstate = RF_NORMAL;
1171                                 else
1172                                         dm_pstable->cur_rfstate = RF_SAVE;
1173                         }
1174                 } else {
1175                         dm_pstable->cur_rfstate = RF_MAX;
1176                 }
1177         } else {
1178                 dm_pstable->cur_rfstate = RF_NORMAL;
1179         }
1180
1181         if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
1182                 if (dm_pstable->cur_rfstate == RF_SAVE) {
1183                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1184                                       0x1C0000, 0x2);
1185                         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1186                         rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1187                                       0xFF000000, 0x63);
1188                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1189                                       0xC000, 0x2);
1190                         rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1191                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1192                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1193                 } else {
1194                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1195                                       0x1CC000, reg_874);
1196                         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1197                                       reg_c70);
1198                         rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1199                                       reg_85c);
1200                         rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1201                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1202                 }
1203
1204                 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
1205         }
1206 }
1207 EXPORT_SYMBOL(rtl92c_dm_rf_saving);
1208
1209 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1210 {
1211         struct rtl_priv *rtlpriv = rtl_priv(hw);
1212         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1213         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1214         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1215
1216         if (((mac->link_state == MAC80211_NOLINK)) &&
1217             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1218                 dm_pstable->rssi_val_min = 0;
1219                 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
1220         }
1221
1222         if (mac->link_state == MAC80211_LINKED) {
1223                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1224                         dm_pstable->rssi_val_min =
1225                             rtlpriv->dm.entry_min_undec_sm_pwdb;
1226                         RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1227                                  "AP Client PWDB = 0x%lx\n",
1228                                  dm_pstable->rssi_val_min);
1229                 } else {
1230                         dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
1231                         RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1232                                  "STA Default Port PWDB = 0x%lx\n",
1233                                  dm_pstable->rssi_val_min);
1234                 }
1235         } else {
1236                 dm_pstable->rssi_val_min =
1237                     rtlpriv->dm.entry_min_undec_sm_pwdb;
1238
1239                 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1240                          "AP Ext Port PWDB = 0x%lx\n",
1241                          dm_pstable->rssi_val_min);
1242         }
1243
1244         if (IS_92C_SERIAL(rtlhal->version))
1245                 ;/* rtl92c_dm_1r_cca(hw); */
1246         else
1247                 rtl92c_dm_rf_saving(hw, false);
1248 }
1249
1250 void rtl92c_dm_init(struct ieee80211_hw *hw)
1251 {
1252         struct rtl_priv *rtlpriv = rtl_priv(hw);
1253
1254         rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1255         rtl92c_dm_diginit(hw);
1256         rtl92c_dm_init_dynamic_txpower(hw);
1257         rtl92c_dm_init_edca_turbo(hw);
1258         rtl92c_dm_init_rate_adaptive_mask(hw);
1259         rtl92c_dm_initialize_txpower_tracking(hw);
1260         rtl92c_dm_init_dynamic_bb_powersaving(hw);
1261 }
1262 EXPORT_SYMBOL(rtl92c_dm_init);
1263
1264 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
1265 {
1266         struct rtl_priv *rtlpriv = rtl_priv(hw);
1267         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1268         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1269         long undec_sm_pwdb;
1270
1271         if (!rtlpriv->dm.dynamic_txpower_enable)
1272                 return;
1273
1274         if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
1275                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1276                 return;
1277         }
1278
1279         if ((mac->link_state < MAC80211_LINKED) &&
1280             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1281                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1282                          "Not connected to any\n");
1283
1284                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1285
1286                 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
1287                 return;
1288         }
1289
1290         if (mac->link_state >= MAC80211_LINKED) {
1291                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1292                         undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1293                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1294                                  "AP Client PWDB = 0x%lx\n",
1295                                  undec_sm_pwdb);
1296                 } else {
1297                         undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
1298                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1299                                  "STA Default Port PWDB = 0x%lx\n",
1300                                  undec_sm_pwdb);
1301                 }
1302         } else {
1303                 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1304
1305                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1306                          "AP Ext Port PWDB = 0x%lx\n",
1307                          undec_sm_pwdb);
1308         }
1309
1310         if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
1311                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1312                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1313                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
1314         } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
1315                    (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
1316
1317                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1318                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1319                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
1320         } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
1321                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1322                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1323                          "TXHIGHPWRLEVEL_NORMAL\n");
1324         }
1325
1326         if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
1327                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1328                          "PHY_SetTxPowerLevel8192S() Channel = %d\n",
1329                          rtlphy->current_channel);
1330                 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1331         }
1332
1333         rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
1334 }
1335
1336 void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1337 {
1338         struct rtl_priv *rtlpriv = rtl_priv(hw);
1339         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1340         bool fw_current_inpsmode = false;
1341         bool fw_ps_awake = true;
1342
1343         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1344                                       (u8 *) (&fw_current_inpsmode));
1345         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1346                                       (u8 *) (&fw_ps_awake));
1347
1348         if (ppsc->p2p_ps_info.p2p_ps_mode)
1349                 fw_ps_awake = false;
1350
1351         if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1352                                              fw_ps_awake)
1353             && (!ppsc->rfchange_inprogress)) {
1354                 rtl92c_dm_pwdb_monitor(hw);
1355                 rtl92c_dm_dig(hw);
1356                 rtl92c_dm_false_alarm_counter_statistics(hw);
1357                 rtl92c_dm_dynamic_bb_powersaving(hw);
1358                 rtl92c_dm_dynamic_txpower(hw);
1359                 rtl92c_dm_check_txpower_tracking(hw);
1360                 /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
1361                 rtl92c_dm_bt_coexist(hw);
1362                 rtl92c_dm_check_edca_turbo(hw);
1363         }
1364 }
1365 EXPORT_SYMBOL(rtl92c_dm_watchdog);
1366
1367 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
1368 {
1369         struct rtl_priv *rtlpriv = rtl_priv(hw);
1370         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1371         long undec_sm_pwdb;
1372         u8 curr_bt_rssi_state = 0x00;
1373
1374         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1375                 undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
1376         } else {
1377                 if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)
1378                         undec_sm_pwdb = 100;
1379                 else
1380                         undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1381         }
1382
1383         /* Check RSSI to determine HighPower/NormalPower state for
1384          * BT coexistence. */
1385         if (undec_sm_pwdb >= 67)
1386                 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
1387         else if (undec_sm_pwdb < 62)
1388                 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
1389
1390         /* Check RSSI to determine AMPDU setting for BT coexistence. */
1391         if (undec_sm_pwdb >= 40)
1392                 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
1393         else if (undec_sm_pwdb <= 32)
1394                 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
1395
1396         /* Marked RSSI state. It will be used to determine BT coexistence
1397          * setting later. */
1398         if (undec_sm_pwdb < 35)
1399                 curr_bt_rssi_state |=  BT_RSSI_STATE_SPECIAL_LOW;
1400         else
1401                 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
1402
1403         /* Set Tx Power according to BT status. */
1404         if (undec_sm_pwdb >= 30)
1405                 curr_bt_rssi_state |=  BT_RSSI_STATE_TXPOWER_LOW;
1406         else if (undec_sm_pwdb < 25)
1407                 curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
1408
1409         /* Check BT state related to BT_Idle in B/G mode. */
1410         if (undec_sm_pwdb < 15)
1411                 curr_bt_rssi_state |=  BT_RSSI_STATE_BG_EDCA_LOW;
1412         else
1413                 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
1414
1415         if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
1416                 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
1417                 return true;
1418         } else {
1419                 return false;
1420         }
1421 }
1422 EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
1423
1424 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
1425 {
1426         struct rtl_priv *rtlpriv = rtl_priv(hw);
1427         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1428
1429         u32 polling, ratio_tx, ratio_pri;
1430         u32 bt_tx, bt_pri;
1431         u8 bt_state;
1432         u8 cur_service_type;
1433
1434         if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1435                 return false;
1436
1437         bt_state = rtl_read_byte(rtlpriv, 0x4fd);
1438         bt_tx = rtl_read_dword(rtlpriv, 0x488);
1439         bt_tx = bt_tx & 0x00ffffff;
1440         bt_pri = rtl_read_dword(rtlpriv, 0x48c);
1441         bt_pri = bt_pri & 0x00ffffff;
1442         polling = rtl_read_dword(rtlpriv, 0x490);
1443
1444         if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
1445             polling == 0xffffffff && bt_state == 0xff)
1446                 return false;
1447
1448         bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
1449         if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
1450                 rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
1451
1452                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1453                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
1454
1455                         bt_state = bt_state |
1456                           ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1457                           0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1458                           BIT_OFFSET_LEN_MASK_32(2, 1);
1459                         rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1460                 }
1461                 return true;
1462         }
1463
1464         ratio_tx = bt_tx * 1000 / polling;
1465         ratio_pri = bt_pri * 1000 / polling;
1466         rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
1467         rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
1468
1469         if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1470
1471                 if ((ratio_tx < 30)  && (ratio_pri < 30))
1472                         cur_service_type = BT_IDLE;
1473                 else if ((ratio_pri > 110) && (ratio_pri < 250))
1474                         cur_service_type = BT_SCO;
1475                 else if ((ratio_tx >= 200) && (ratio_pri >= 200))
1476                         cur_service_type = BT_BUSY;
1477                 else if ((ratio_tx >= 350) && (ratio_tx < 500))
1478                         cur_service_type = BT_OTHERBUSY;
1479                 else if (ratio_tx >= 500)
1480                         cur_service_type = BT_PAN;
1481                 else
1482                         cur_service_type = BT_OTHER_ACTION;
1483
1484                 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
1485                         rtlpcipriv->bt_coexist.bt_service = cur_service_type;
1486                         bt_state = bt_state |
1487                            ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1488                            0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1489                            ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
1490                            0 : BIT_OFFSET_LEN_MASK_32(2, 1));
1491
1492                         /* Add interrupt migration when bt is not ini
1493                          * idle state (no traffic). */
1494                         if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1495                                 rtl_write_word(rtlpriv, 0x504, 0x0ccc);
1496                                 rtl_write_byte(rtlpriv, 0x506, 0x54);
1497                                 rtl_write_byte(rtlpriv, 0x507, 0x54);
1498                         } else {
1499                                 rtl_write_byte(rtlpriv, 0x506, 0x00);
1500                                 rtl_write_byte(rtlpriv, 0x507, 0x00);
1501                         }
1502
1503                         rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1504                         return true;
1505                 }
1506         }
1507
1508         return false;
1509
1510 }
1511
1512 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
1513 {
1514         struct rtl_priv *rtlpriv = rtl_priv(hw);
1515         static bool media_connect;
1516
1517         if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1518                 media_connect = false;
1519         } else {
1520                 if (!media_connect) {
1521                         media_connect = true;
1522                         return true;
1523                 }
1524                 media_connect = true;
1525         }
1526
1527         return false;
1528 }
1529
1530 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
1531 {
1532         struct rtl_priv *rtlpriv = rtl_priv(hw);
1533         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1534
1535
1536         if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
1537                 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
1538                 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
1539         } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
1540                 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
1541                 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
1542         } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
1543                 if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
1544                         rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
1545                         rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
1546                 } else {
1547                         rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
1548                         rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
1549                 }
1550         } else {
1551                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1552                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1553         }
1554
1555         if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
1556              (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
1557              (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
1558              (rtlpcipriv->bt_coexist.bt_rssi_state &
1559              BT_RSSI_STATE_BG_EDCA_LOW)) {
1560                 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
1561                 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
1562         }
1563 }
1564
1565 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte)
1566 {
1567         struct rtl_priv *rtlpriv = rtl_priv(hw);
1568         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1569
1570
1571         /* Only enable HW BT coexist when BT in "Busy" state. */
1572         if (rtlpriv->mac80211.vendor == PEER_CISCO &&
1573             rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
1574                 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1575         } else {
1576                 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
1577                     (rtlpcipriv->bt_coexist.bt_rssi_state &
1578                      BT_RSSI_STATE_NORMAL_POWER)) {
1579                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1580                 } else if ((rtlpcipriv->bt_coexist.bt_service ==
1581                             BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
1582                             WIRELESS_MODE_N_24G) &&
1583                             (rtlpcipriv->bt_coexist.bt_rssi_state &
1584                             BT_RSSI_STATE_SPECIAL_LOW)) {
1585                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1586                 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
1587                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1588                 } else {
1589                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1590                 }
1591         }
1592
1593         if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
1594                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
1595         else
1596                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
1597
1598         if (rtlpcipriv->bt_coexist.bt_rssi_state &
1599             BT_RSSI_STATE_NORMAL_POWER) {
1600                 rtl92c_bt_set_normal(hw);
1601         } else {
1602                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1603                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1604         }
1605
1606         if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1607                 rtlpriv->cfg->ops->set_rfreg(hw,
1608                                  RF90_PATH_A,
1609                                  0x1e,
1610                                  0xf0, 0xf);
1611         } else {
1612                 rtlpriv->cfg->ops->set_rfreg(hw,
1613                      RF90_PATH_A, 0x1e, 0xf0,
1614                      rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1615         }
1616
1617         if (!rtlpriv->dm.dynamic_txpower_enable) {
1618                 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1619                         if (rtlpcipriv->bt_coexist.bt_rssi_state &
1620                                 BT_RSSI_STATE_TXPOWER_LOW) {
1621                                 rtlpriv->dm.dynamic_txhighpower_lvl =
1622                                                         TXHIGHPWRLEVEL_BT2;
1623                         } else {
1624                                 rtlpriv->dm.dynamic_txhighpower_lvl =
1625                                         TXHIGHPWRLEVEL_BT1;
1626                         }
1627                 } else {
1628                         rtlpriv->dm.dynamic_txhighpower_lvl =
1629                                 TXHIGHPWRLEVEL_NORMAL;
1630                 }
1631                 rtl92c_phy_set_txpower_level(hw,
1632                         rtlpriv->phy.current_channel);
1633         }
1634 }
1635
1636 static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
1637 {
1638         struct rtl_priv *rtlpriv = rtl_priv(hw);
1639         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1640         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1641         u8 tmp1byte = 0;
1642
1643         if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version) &&
1644             rtlpcipriv->bt_coexist.bt_coexistence)
1645                 tmp1byte |= BIT(5);
1646         if (rtlpcipriv->bt_coexist.bt_cur_state) {
1647                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
1648                         rtl92c_bt_ant_isolation(hw, tmp1byte);
1649         } else {
1650                 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
1651                 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
1652                                 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1653
1654                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1655                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1656         }
1657 }
1658
1659 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
1660 {
1661         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1662
1663         bool wifi_connect_change;
1664         bool bt_state_change;
1665         bool rssi_state_change;
1666
1667         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1668              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
1669
1670                 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
1671                 bt_state_change = rtl92c_bt_state_change(hw);
1672                 rssi_state_change = rtl92c_bt_rssi_state_change(hw);
1673
1674                 if (wifi_connect_change || bt_state_change || rssi_state_change)
1675                         rtl92c_check_bt_change(hw);
1676         }
1677 }
1678 EXPORT_SYMBOL(rtl92c_dm_bt_coexist);