2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
26 * PCIe unit register offsets.
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_DEBUG_CTRL 0x1a60
61 #define PCIE_DEBUG_SOFT_RESET BIT(20)
64 * This product ID is registered by Marvell, and used when the Marvell
65 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
66 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
69 #define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
71 /* PCI configuration space of a PCI-to-PCI bridge */
72 struct mvebu_sw_pci_bridge {
87 u8 secondary_latency_timer;
104 struct mvebu_pcie_port;
106 /* Structure representing all PCIe interfaces */
108 struct platform_device *pdev;
109 struct mvebu_pcie_port *ports;
110 struct msi_chip *msi;
112 struct resource realio;
114 struct resource busn;
118 /* Structure representing one PCIe interface */
119 struct mvebu_pcie_port {
122 spinlock_t conf_lock;
126 unsigned int mem_target;
127 unsigned int mem_attr;
128 unsigned int io_target;
129 unsigned int io_attr;
132 int reset_active_low;
134 struct mvebu_sw_pci_bridge bridge;
135 struct device_node *dn;
136 struct mvebu_pcie *pcie;
137 phys_addr_t memwin_base;
139 phys_addr_t iowin_base;
143 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
145 writel(val, port->base + reg);
148 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
150 return readl(port->base + reg);
153 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
155 return port->io_target != -1 && port->io_attr != -1;
158 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
160 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
163 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
167 stat = mvebu_readl(port, PCIE_STAT_OFF);
168 stat &= ~PCIE_STAT_BUS;
170 mvebu_writel(port, stat, PCIE_STAT_OFF);
173 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
177 stat = mvebu_readl(port, PCIE_STAT_OFF);
178 stat &= ~PCIE_STAT_DEV;
180 mvebu_writel(port, stat, PCIE_STAT_OFF);
184 * Setup PCIE BARs and Address Decode Wins:
185 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
186 * WIN[0-3] -> DRAM bank[0-3]
188 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
190 const struct mbus_dram_target_info *dram;
194 dram = mv_mbus_dram_info();
196 /* First, disable and clear BARs and windows. */
197 for (i = 1; i < 3; i++) {
198 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
199 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
200 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
203 for (i = 0; i < 5; i++) {
204 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
205 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
206 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
209 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
210 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
211 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
213 /* Setup windows for DDR banks. Count total DDR size on the fly. */
215 for (i = 0; i < dram->num_cs; i++) {
216 const struct mbus_dram_window *cs = dram->cs + i;
218 mvebu_writel(port, cs->base & 0xffff0000,
219 PCIE_WIN04_BASE_OFF(i));
220 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
222 ((cs->size - 1) & 0xffff0000) |
223 (cs->mbus_attr << 8) |
224 (dram->mbus_dram_target_id << 4) | 1,
225 PCIE_WIN04_CTRL_OFF(i));
230 /* Round up 'size' to the nearest power of two. */
231 if ((size & (size - 1)) != 0)
232 size = 1 << fls(size);
234 /* Setup BAR[1] to all DRAM banks. */
235 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
236 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
237 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
238 PCIE_BAR_CTRL_OFF(1));
241 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
245 /* Point PCIe unit MBUS decode windows to DRAM space. */
246 mvebu_pcie_setup_wins(port);
248 /* Master + slave enable. */
249 cmd = mvebu_readl(port, PCIE_CMD_OFF);
250 cmd |= PCI_COMMAND_IO;
251 cmd |= PCI_COMMAND_MEMORY;
252 cmd |= PCI_COMMAND_MASTER;
253 mvebu_writel(port, cmd, PCIE_CMD_OFF);
255 /* Enable interrupt lines A-D. */
256 mask = mvebu_readl(port, PCIE_MASK_OFF);
257 mask |= PCIE_MASK_ENABLE_INTS;
258 mvebu_writel(port, mask, PCIE_MASK_OFF);
261 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
263 u32 devfn, int where, int size, u32 *val)
265 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
268 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
271 *val = (*val >> (8 * (where & 3))) & 0xff;
273 *val = (*val >> (8 * (where & 3))) & 0xffff;
275 return PCIBIOS_SUCCESSFUL;
278 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
280 u32 devfn, int where, int size, u32 val)
282 u32 _val, shift = 8 * (where & 3);
284 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
286 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
291 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
293 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
295 return PCIBIOS_BAD_REGISTER_NUMBER;
297 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
299 return PCIBIOS_SUCCESSFUL;
302 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
306 /* Are the new iobase/iolimit values invalid? */
307 if (port->bridge.iolimit <= port->bridge.iobase ||
308 port->bridge.iolimitupper < port->bridge.iobaseupper) {
310 /* If a window was configured, remove it */
311 if (port->iowin_base) {
312 mvebu_mbus_del_window(port->iowin_base,
314 port->iowin_base = 0;
315 port->iowin_size = 0;
321 if (!mvebu_has_ioport(port)) {
322 dev_WARN(&port->pcie->pdev->dev,
323 "Attempt to set IO when IO is disabled\n");
328 * We read the PCI-to-PCI bridge emulated registers, and
329 * calculate the base address and size of the address decoding
330 * window to setup, according to the PCI-to-PCI bridge
331 * specifications. iobase is the bus address, port->iowin_base
332 * is the CPU address.
334 iobase = ((port->bridge.iobase & 0xF0) << 8) |
335 (port->bridge.iobaseupper << 16);
336 port->iowin_base = port->pcie->io.start + iobase;
337 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
338 (port->bridge.iolimitupper << 16)) -
341 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
342 port->iowin_base, port->iowin_size,
345 pci_ioremap_io(iobase, port->iowin_base);
348 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
350 /* Are the new membase/memlimit values invalid? */
351 if (port->bridge.memlimit < port->bridge.membase) {
353 /* If a window was configured, remove it */
354 if (port->memwin_base) {
355 mvebu_mbus_del_window(port->memwin_base,
357 port->memwin_base = 0;
358 port->memwin_size = 0;
365 * We read the PCI-to-PCI bridge emulated registers, and
366 * calculate the base address and size of the address decoding
367 * window to setup, according to the PCI-to-PCI bridge
370 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
372 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
375 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
376 port->memwin_base, port->memwin_size);
380 * Initialize the configuration space of the PCI-to-PCI bridge
381 * associated with the given PCIe interface.
383 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
385 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
387 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
389 bridge->class = PCI_CLASS_BRIDGE_PCI;
390 bridge->vendor = PCI_VENDOR_ID_MARVELL;
391 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
392 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
393 bridge->cache_line_size = 0x10;
395 /* We support 32 bits I/O addressing */
396 bridge->iobase = PCI_IO_RANGE_TYPE_32;
397 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
401 * Read the configuration space of the PCI-to-PCI bridge associated to
402 * the given PCIe interface.
404 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
405 unsigned int where, int size, u32 *value)
407 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
409 switch (where & ~3) {
411 *value = bridge->device << 16 | bridge->vendor;
415 *value = bridge->command;
418 case PCI_CLASS_REVISION:
419 *value = bridge->class << 16 | bridge->interface << 8 |
423 case PCI_CACHE_LINE_SIZE:
424 *value = bridge->bist << 24 | bridge->header_type << 16 |
425 bridge->latency_timer << 8 | bridge->cache_line_size;
428 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
429 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
432 case PCI_PRIMARY_BUS:
433 *value = (bridge->secondary_latency_timer << 24 |
434 bridge->subordinate_bus << 16 |
435 bridge->secondary_bus << 8 |
436 bridge->primary_bus);
440 if (!mvebu_has_ioport(port))
441 *value = bridge->secondary_status << 16;
443 *value = (bridge->secondary_status << 16 |
444 bridge->iolimit << 8 |
448 case PCI_MEMORY_BASE:
449 *value = (bridge->memlimit << 16 | bridge->membase);
452 case PCI_PREF_MEMORY_BASE:
456 case PCI_IO_BASE_UPPER16:
457 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
460 case PCI_ROM_ADDRESS1:
466 return PCIBIOS_BAD_REGISTER_NUMBER;
470 *value = (*value >> (8 * (where & 3))) & 0xffff;
472 *value = (*value >> (8 * (where & 3))) & 0xff;
474 return PCIBIOS_SUCCESSFUL;
477 /* Write to the PCI-to-PCI bridge configuration space */
478 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
479 unsigned int where, int size, u32 value)
481 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
488 mask = ~(0xffff << ((where & 3) * 8));
490 mask = ~(0xff << ((where & 3) * 8));
492 return PCIBIOS_BAD_REGISTER_NUMBER;
494 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
498 value = (reg & mask) | value << ((where & 3) * 8);
500 switch (where & ~3) {
502 bridge->command = value & 0xffff;
503 if (!mvebu_has_ioport(port))
504 bridge->command &= ~PCI_COMMAND_IO;
507 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
508 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
513 * We also keep bit 1 set, it is a read-only bit that
514 * indicates we support 32 bits addressing for the
517 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
518 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
519 mvebu_pcie_handle_iobase_change(port);
522 case PCI_MEMORY_BASE:
523 bridge->membase = value & 0xffff;
524 bridge->memlimit = value >> 16;
525 mvebu_pcie_handle_membase_change(port);
528 case PCI_IO_BASE_UPPER16:
529 bridge->iobaseupper = value & 0xffff;
530 bridge->iolimitupper = value >> 16;
531 mvebu_pcie_handle_iobase_change(port);
534 case PCI_PRIMARY_BUS:
535 bridge->primary_bus = value & 0xff;
536 bridge->secondary_bus = (value >> 8) & 0xff;
537 bridge->subordinate_bus = (value >> 16) & 0xff;
538 bridge->secondary_latency_timer = (value >> 24) & 0xff;
539 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
546 return PCIBIOS_SUCCESSFUL;
549 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
551 return sys->private_data;
554 static struct mvebu_pcie_port *
555 mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
560 for (i = 0; i < pcie->nports; i++) {
561 struct mvebu_pcie_port *port = &pcie->ports[i];
562 if (bus->number == 0 && port->devfn == devfn)
564 if (bus->number != 0 &&
565 bus->number >= port->bridge.secondary_bus &&
566 bus->number <= port->bridge.subordinate_bus)
573 /* PCI configuration space write function */
574 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
575 int where, int size, u32 val)
577 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
578 struct mvebu_pcie_port *port;
582 port = mvebu_pcie_find_port(pcie, bus, devfn);
584 return PCIBIOS_DEVICE_NOT_FOUND;
586 /* Access the emulated PCI-to-PCI bridge */
587 if (bus->number == 0)
588 return mvebu_sw_pci_bridge_write(port, where, size, val);
590 if (!mvebu_pcie_link_up(port))
591 return PCIBIOS_DEVICE_NOT_FOUND;
594 * On the secondary bus, we don't want to expose any other
595 * device than the device physically connected in the PCIe
596 * slot, visible in slot 0. In slot 1, there's a special
597 * Marvell device that only makes sense when the Armada is
598 * used as a PCIe endpoint.
600 if (bus->number == port->bridge.secondary_bus &&
601 PCI_SLOT(devfn) != 0)
602 return PCIBIOS_DEVICE_NOT_FOUND;
604 /* Access the real PCIe interface */
605 spin_lock_irqsave(&port->conf_lock, flags);
606 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
608 spin_unlock_irqrestore(&port->conf_lock, flags);
613 /* PCI configuration space read function */
614 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
617 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
618 struct mvebu_pcie_port *port;
622 port = mvebu_pcie_find_port(pcie, bus, devfn);
625 return PCIBIOS_DEVICE_NOT_FOUND;
628 /* Access the emulated PCI-to-PCI bridge */
629 if (bus->number == 0)
630 return mvebu_sw_pci_bridge_read(port, where, size, val);
632 if (!mvebu_pcie_link_up(port)) {
634 return PCIBIOS_DEVICE_NOT_FOUND;
638 * On the secondary bus, we don't want to expose any other
639 * device than the device physically connected in the PCIe
640 * slot, visible in slot 0. In slot 1, there's a special
641 * Marvell device that only makes sense when the Armada is
642 * used as a PCIe endpoint.
644 if (bus->number == port->bridge.secondary_bus &&
645 PCI_SLOT(devfn) != 0) {
647 return PCIBIOS_DEVICE_NOT_FOUND;
650 /* Access the real PCIe interface */
651 spin_lock_irqsave(&port->conf_lock, flags);
652 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
654 spin_unlock_irqrestore(&port->conf_lock, flags);
659 static struct pci_ops mvebu_pcie_ops = {
660 .read = mvebu_pcie_rd_conf,
661 .write = mvebu_pcie_wr_conf,
664 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
666 struct mvebu_pcie *pcie = sys_to_pcie(sys);
669 if (resource_size(&pcie->realio) != 0)
670 pci_add_resource_offset(&sys->resources, &pcie->realio,
672 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
673 pci_add_resource(&sys->resources, &pcie->busn);
675 for (i = 0; i < pcie->nports; i++) {
676 struct mvebu_pcie_port *port = &pcie->ports[i];
679 mvebu_pcie_setup_hw(port);
685 static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
690 ret = of_irq_map_pci(dev, &oirq);
694 return irq_create_of_mapping(oirq.controller, oirq.specifier,
698 static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
700 struct mvebu_pcie *pcie = sys_to_pcie(sys);
703 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
704 &mvebu_pcie_ops, sys, &sys->resources);
708 pci_scan_child_bus(bus);
713 static void mvebu_pcie_add_bus(struct pci_bus *bus)
715 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
716 bus->msi = pcie->msi;
719 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
720 const struct resource *res,
721 resource_size_t start,
722 resource_size_t size,
723 resource_size_t align)
725 if (dev->bus->number != 0)
729 * On the PCI-to-PCI bridge side, the I/O windows must have at
730 * least a 64 KB size and be aligned on their size, and the
731 * memory windows must have at least a 1 MB size and be
732 * aligned on their size
734 if (res->flags & IORESOURCE_IO)
735 return round_up(start, max((resource_size_t)SZ_64K, size));
736 else if (res->flags & IORESOURCE_MEM)
737 return round_up(start, max((resource_size_t)SZ_1M, size));
742 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
746 memset(&hw, 0, sizeof(hw));
748 hw.nr_controllers = 1;
749 hw.private_data = (void **)&pcie;
750 hw.setup = mvebu_pcie_setup;
751 hw.scan = mvebu_pcie_scan_bus;
752 hw.map_irq = mvebu_pcie_map_irq;
753 hw.ops = &mvebu_pcie_ops;
754 hw.align_resource = mvebu_pcie_align_resource;
755 hw.add_bus = mvebu_pcie_add_bus;
757 pci_common_init(&hw);
761 * Looks up the list of register addresses encoded into the reg =
762 * <...> property for one that matches the given port/lane. Once
765 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
766 struct device_node *np, struct mvebu_pcie_port *port)
768 struct resource regs;
771 ret = of_address_to_resource(np, 0, ®s);
775 return devm_ioremap_resource(&pdev->dev, ®s);
778 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
779 #define DT_TYPE_IO 0x1
780 #define DT_TYPE_MEM32 0x2
781 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
782 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
784 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
789 const int na = 3, ns = 2;
791 int rlen, nranges, rangesz, pna, i;
796 range = of_get_property(np, "ranges", &rlen);
800 pna = of_n_addr_cells(np);
801 rangesz = pna + na + ns;
802 nranges = rlen / sizeof(__be32) / rangesz;
804 for (i = 0; i < nranges; i++) {
805 u32 flags = of_read_number(range, 1);
806 u32 slot = of_read_number(range, 2);
807 u64 cpuaddr = of_read_number(range + na, pna);
810 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
811 rtype = IORESOURCE_IO;
812 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
813 rtype = IORESOURCE_MEM;
815 if (slot == PCI_SLOT(devfn) && type == rtype) {
816 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
817 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
827 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
829 struct device_node *msi_node;
831 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
836 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
839 pcie->msi->dev = &pcie->pdev->dev;
842 static int mvebu_pcie_probe(struct platform_device *pdev)
844 struct mvebu_pcie *pcie;
845 struct device_node *np = pdev->dev.of_node;
846 struct device_node *child;
849 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
855 platform_set_drvdata(pdev, pcie);
857 /* Get the PCIe memory and I/O aperture */
858 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
859 if (resource_size(&pcie->mem) == 0) {
860 dev_err(&pdev->dev, "invalid memory aperture size\n");
864 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
866 if (resource_size(&pcie->io) != 0) {
867 pcie->realio.flags = pcie->io.flags;
868 pcie->realio.start = PCIBIOS_MIN_IO;
869 pcie->realio.end = min_t(resource_size_t,
871 resource_size(&pcie->io));
873 pcie->realio = pcie->io;
875 /* Get the bus range */
876 ret = of_pci_parse_bus_range(np, &pcie->busn);
878 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
884 for_each_child_of_node(pdev->dev.of_node, child) {
885 if (!of_device_is_available(child))
890 pcie->ports = devm_kzalloc(&pdev->dev, i *
891 sizeof(struct mvebu_pcie_port),
897 for_each_child_of_node(pdev->dev.of_node, child) {
898 struct mvebu_pcie_port *port = &pcie->ports[i];
899 enum of_gpio_flags flags;
901 if (!of_device_is_available(child))
906 if (of_property_read_u32(child, "marvell,pcie-port",
909 "ignoring PCIe DT node, missing pcie-port property\n");
913 if (of_property_read_u32(child, "marvell,pcie-lane",
917 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
918 port->port, port->lane);
920 port->devfn = of_pci_get_devfn(child);
924 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
925 &port->mem_target, &port->mem_attr);
927 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
928 port->port, port->lane);
932 if (resource_size(&pcie->io) != 0)
933 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
934 &port->io_target, &port->io_attr);
936 port->io_target = -1;
940 port->reset_gpio = of_get_named_gpio_flags(child,
941 "reset-gpios", 0, &flags);
942 if (gpio_is_valid(port->reset_gpio)) {
943 u32 reset_udelay = 20000;
945 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
946 port->reset_name = kasprintf(GFP_KERNEL,
947 "pcie%d.%d-reset", port->port, port->lane);
948 of_property_read_u32(child, "reset-delay-us",
951 ret = devm_gpio_request_one(&pdev->dev,
952 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
954 if (ret == -EPROBE_DEFER)
959 gpio_set_value(port->reset_gpio,
960 (port->reset_active_low) ? 1 : 0);
961 msleep(reset_udelay/1000);
964 port->clk = of_clk_get_by_name(child, NULL);
965 if (IS_ERR(port->clk)) {
966 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
967 port->port, port->lane);
971 ret = clk_prepare_enable(port->clk);
975 port->base = mvebu_pcie_map_registers(pdev, child, port);
977 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
978 port->port, port->lane);
979 clk_disable_unprepare(port->clk);
983 mvebu_pcie_set_local_dev_nr(port, 1);
985 port->clk = of_clk_get_by_name(child, NULL);
986 if (IS_ERR(port->clk)) {
987 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
988 port->port, port->lane);
994 spin_lock_init(&port->conf_lock);
995 mvebu_sw_pci_bridge_init(port);
1000 mvebu_pcie_msi_enable(pcie);
1001 mvebu_pcie_enable(pcie);
1006 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1007 { .compatible = "marvell,armada-xp-pcie", },
1008 { .compatible = "marvell,armada-370-pcie", },
1009 { .compatible = "marvell,dove-pcie", },
1010 { .compatible = "marvell,kirkwood-pcie", },
1013 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1015 static struct platform_driver mvebu_pcie_driver = {
1017 .owner = THIS_MODULE,
1018 .name = "mvebu-pcie",
1020 of_match_ptr(mvebu_pcie_of_match_table),
1021 /* driver unloading/unbinding currently not supported */
1022 .suppress_bind_attrs = true,
1024 .probe = mvebu_pcie_probe,
1026 module_platform_driver(mvebu_pcie_driver);
1028 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1029 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1030 MODULE_LICENSE("GPLv2");