drivers/phy/phy-twl4030-usb.c

   1 /*
   2  * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
   3  *
   4  * Copyright (C) 2004-2007 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Contact: Felipe Balbi <felipe.balbi@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Current status:
  23  *      - HS USB ULPI mode works.
  24  *      - 3-pin mode support may be added in future.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/io.h>
  34 #include <linux/delay.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/phy/phy.h>
  37 #include <linux/usb/musb-omap.h>
  38 #include <linux/usb/ulpi.h>
  39 #include <linux/i2c/twl.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/err.h>
  42 #include <linux/slab.h>
  43
  44 /* Register defines */
  45
  46 #define MCPC_CTRL                       0x30
  47 #define MCPC_CTRL_RTSOL                 (1 << 7)
  48 #define MCPC_CTRL_EXTSWR                (1 << 6)
  49 #define MCPC_CTRL_EXTSWC                (1 << 5)
  50 #define MCPC_CTRL_VOICESW               (1 << 4)
  51 #define MCPC_CTRL_OUT64K                (1 << 3)
  52 #define MCPC_CTRL_RTSCTSSW              (1 << 2)
  53 #define MCPC_CTRL_HS_UART               (1 << 0)
  54
  55 #define MCPC_IO_CTRL                    0x33
  56 #define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
  57 #define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
  58 #define MCPC_IO_CTRL_RXD_PU             (1 << 3)
  59 #define MCPC_IO_CTRL_TXDTYP             (1 << 2)
  60 #define MCPC_IO_CTRL_CTSTYP             (1 << 1)
  61 #define MCPC_IO_CTRL_RTSTYP             (1 << 0)
  62
  63 #define MCPC_CTRL2                      0x36
  64 #define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
  65
  66 #define OTHER_FUNC_CTRL                 0x80
  67 #define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
  68 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
  69
  70 #define OTHER_IFC_CTRL                  0x83
  71 #define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
  72 #define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
  73 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
  74 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
  75 #define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
  76 #define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
  77
  78 #define OTHER_INT_EN_RISE               0x86
  79 #define OTHER_INT_EN_FALL               0x89
  80 #define OTHER_INT_STS                   0x8C
  81 #define OTHER_INT_LATCH                 0x8D
  82 #define OTHER_INT_VB_SESS_VLD           (1 << 7)
  83 #define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
  84 #define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
  85 #define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
  86 #define OTHER_INT_MANU                  (1 << 1)
  87 #define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
  88
  89 #define ID_STATUS                       0x96
  90 #define ID_RES_FLOAT                    (1 << 4)
  91 #define ID_RES_440K                     (1 << 3)
  92 #define ID_RES_200K                     (1 << 2)
  93 #define ID_RES_102K                     (1 << 1)
  94 #define ID_RES_GND                      (1 << 0)
  95
  96 #define POWER_CTRL                      0xAC
  97 #define POWER_CTRL_OTG_ENAB             (1 << 5)
  98
  99 #define OTHER_IFC_CTRL2                 0xAF
 100 #define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
 101 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
 102 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
 103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
 104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
 105 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
 106
 107 #define REG_CTRL_EN                     0xB2
 108 #define REG_CTRL_ERROR                  0xB5
 109 #define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
 110
 111 #define OTHER_FUNC_CTRL2                0xB8
 112 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
 113
 114 /* following registers do not have separate _clr and _set registers */
 115 #define VBUS_DEBOUNCE                   0xC0
 116 #define ID_DEBOUNCE                     0xC1
 117 #define VBAT_TIMER                      0xD3
 118 #define PHY_PWR_CTRL                    0xFD
 119 #define PHY_PWR_PHYPWD                  (1 << 0)
 120 #define PHY_CLK_CTRL                    0xFE
 121 #define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
 122 #define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
 123 #define REQ_PHY_DPLL_CLK                (1 << 0)
 124 #define PHY_CLK_CTRL_STS                0xFF
 125 #define PHY_DPLL_CLK                    (1 << 0)
 126
 127 /* In module TWL_MODULE_PM_MASTER */
 128 #define STS_HW_CONDITIONS               0x0F
 129
 130 /* In module TWL_MODULE_PM_RECEIVER */
 131 #define VUSB_DEDICATED1                 0x7D
 132 #define VUSB_DEDICATED2                 0x7E
 133 #define VUSB1V5_DEV_GRP                 0x71
 134 #define VUSB1V5_TYPE                    0x72
 135 #define VUSB1V5_REMAP                   0x73
 136 #define VUSB1V8_DEV_GRP                 0x74
 137 #define VUSB1V8_TYPE                    0x75
 138 #define VUSB1V8_REMAP                   0x76
 139 #define VUSB3V1_DEV_GRP                 0x77
 140 #define VUSB3V1_TYPE                    0x78
 141 #define VUSB3V1_REMAP                   0x79
 142
 143 /* In module TWL4030_MODULE_INTBR */
 144 #define PMBR1                           0x0D
 145 #define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
 146
 147 struct twl4030_usb {
 148         struct usb_phy          phy;
 149         struct device           *dev;
 150
 151         /* TWL4030 internal USB regulator supplies */
 152         struct regulator        *usb1v5;
 153         struct regulator        *usb1v8;
 154         struct regulator        *usb3v1;
 155
 156         /* for vbus reporting with irqs disabled */
 157         spinlock_t              lock;
 158
 159         /* pin configuration */
 160         enum twl4030_usb_mode   usb_mode;
 161
 162         int                     irq;
 163         enum omap_musb_vbus_id_status linkstat;
 164         bool                    vbus_supplied;
 165         u8                      asleep;
 166         bool                    irq_enabled;
 167
 168         struct delayed_work     id_workaround_work;
 169 };
 170
 171 /* internal define on top of container_of */
 172 #define phy_to_twl(x)           container_of((x), struct twl4030_usb, phy)
 173
 174 /*-------------------------------------------------------------------------*/
 175
 176 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
 177                 u8 module, u8 data, u8 address)
 178 {
 179         u8 check;
 180
 181         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 182             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 183                                                 (check == data))
 184                 return 0;
 185         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 186                         1, module, address, check, data);
 187
 188         /* Failed once: Try again */
 189         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 190             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 191                                                 (check == data))
 192                 return 0;
 193         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 194                         2, module, address, check, data);
 195
 196         /* Failed again: Return error */
 197         return -EBUSY;
 198 }
 199
 200 #define twl4030_usb_write_verify(twl, address, data)    \
 201         twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
 202
 203 static inline int twl4030_usb_write(struct twl4030_usb *twl,
 204                 u8 address, u8 data)
 205 {
 206         int ret = 0;
 207
 208         ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
 209         if (ret < 0)
 210                 dev_dbg(twl->dev,
 211                         "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
 212         return ret;
 213 }
 214
 215 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
 216 {
 217         u8 data;
 218         int ret = 0;
 219
 220         ret = twl_i2c_read_u8(module, &data, address);
 221         if (ret >= 0)
 222                 ret = data;
 223         else
 224                 dev_dbg(twl->dev,
 225                         "TWL4030:readb[0x%x,0x%x] Error %d\n",
 226                                         module, address, ret);
 227
 228         return ret;
 229 }
 230
 231 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
 232 {
 233         return twl4030_readb(twl, TWL_MODULE_USB, address);
 234 }
 235
 236 /*-------------------------------------------------------------------------*/
 237
 238 static inline int
 239 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 240 {
 241         return twl4030_usb_write(twl, ULPI_SET(reg), bits);
 242 }
 243
 244 static inline int
 245 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 246 {
 247         return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
 248 }
 249
 250 /*-------------------------------------------------------------------------*/
 251
 252 static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
 253 {
 254         int ret;
 255
 256         ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
 257         if (ret < 0 || !(ret & PHY_DPLL_CLK))
 258                 /*
 259                  * if clocks are off, registers are not updated,
 260                  * but we can assume we don't drive VBUS in this case
 261                  */
 262                 return false;
 263
 264         ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
 265         if (ret < 0)
 266                 return false;
 267
 268         return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
 269 }
 270
 271 static enum omap_musb_vbus_id_status
 272         twl4030_usb_linkstat(struct twl4030_usb *twl)
 273 {
 274         int     status;
 275         enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
 276
 277         twl->vbus_supplied = false;
 278
 279         /*
 280          * For ID/VBUS sensing, see manual section 15.4.8 ...
 281          * except when using only battery backup power, two
 282          * comparators produce VBUS_PRES and ID_PRES signals,
 283          * which don't match docs elsewhere.  But ... BIT(7)
 284          * and BIT(2) of STS_HW_CONDITIONS, respectively, do
 285          * seem to match up.  If either is true the USB_PRES
 286          * signal is active, the OTG module is activated, and
 287          * its interrupt may be raised (may wake the system).
 288          */
 289         status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
 290         if (status < 0)
 291                 dev_err(twl->dev, "USB link status err %d\n", status);
 292         else if (status & (BIT(7) | BIT(2))) {
 293                 if (status & BIT(7)) {
 294                         if (twl4030_is_driving_vbus(twl))
 295                                 status &= ~BIT(7);
 296                         else
 297                                 twl->vbus_supplied = true;
 298                 }
 299
 300                 if (status & BIT(2))
 301                         linkstat = OMAP_MUSB_ID_GROUND;
 302                 else if (status & BIT(7))
 303                         linkstat = OMAP_MUSB_VBUS_VALID;
 304                 else
 305                         linkstat = OMAP_MUSB_VBUS_OFF;
 306         } else {
 307                 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
 308                         linkstat = OMAP_MUSB_VBUS_OFF;
 309         }
 310
 311         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
 312                         status, status, linkstat);
 313
 314         /* REVISIT this assumes host and peripheral controllers
 315          * are registered, and that both are active...
 316          */
 317
 318         return linkstat;
 319 }
 320
 321 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
 322 {
 323         twl->usb_mode = mode;
 324
 325         switch (mode) {
 326         case T2_USB_MODE_ULPI:
 327                 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
 328                                         ULPI_IFC_CTRL_CARKITMODE);
 329                 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 330                 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
 331                                         ULPI_FUNC_CTRL_XCVRSEL_MASK |
 332                                         ULPI_FUNC_CTRL_OPMODE_MASK);
 333                 break;
 334         case -1:
 335                 /* FIXME: power on defaults */
 336                 break;
 337         default:
 338                 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
 339                                 mode);
 340                 break;
 341         };
 342 }
 343
 344 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
 345 {
 346         unsigned long timeout;
 347         int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 348
 349         if (val >= 0) {
 350                 if (on) {
 351                         /* enable DPLL to access PHY registers over I2C */
 352                         val |= REQ_PHY_DPLL_CLK;
 353                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 354                                                 (u8)val) < 0);
 355
 356                         timeout = jiffies + HZ;
 357                         while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 358                                                         PHY_DPLL_CLK)
 359                                 && time_before(jiffies, timeout))
 360                                         udelay(10);
 361                         if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 362                                                         PHY_DPLL_CLK))
 363                                 dev_err(twl->dev, "Timeout setting T2 HSUSB "
 364                                                 "PHY DPLL clock\n");
 365                 } else {
 366                         /* let ULPI control the DPLL clock */
 367                         val &= ~REQ_PHY_DPLL_CLK;
 368                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 369                                                 (u8)val) < 0);
 370                 }
 371         }
 372 }
 373
 374 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
 375 {
 376         u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
 377
 378         if (on)
 379                 pwr &= ~PHY_PWR_PHYPWD;
 380         else
 381                 pwr |= PHY_PWR_PHYPWD;
 382
 383         WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
 384 }
 385
 386 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
 387 {
 388         int ret;
 389
 390         if (on) {
 391                 ret = regulator_enable(twl->usb3v1);
 392                 if (ret)
 393                         dev_err(twl->dev, "Failed to enable usb3v1\n");
 394
 395                 ret = regulator_enable(twl->usb1v8);
 396                 if (ret)
 397                         dev_err(twl->dev, "Failed to enable usb1v8\n");
 398
 399                 /*
 400                  * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
 401                  * in twl4030) resets the VUSB_DEDICATED2 register. This reset
 402                  * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
 403                  * SLEEP. We work around this by clearing the bit after usv3v1
 404                  * is re-activated. This ensures that VUSB3V1 is really active.
 405                  */
 406                 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
 407
 408                 ret = regulator_enable(twl->usb1v5);
 409                 if (ret)
 410                         dev_err(twl->dev, "Failed to enable usb1v5\n");
 411
 412                 __twl4030_phy_power(twl, 1);
 413                 twl4030_usb_write(twl, PHY_CLK_CTRL,
 414                                   twl4030_usb_read(twl, PHY_CLK_CTRL) |
 415                                         (PHY_CLK_CTRL_CLOCKGATING_EN |
 416                                                 PHY_CLK_CTRL_CLK32K_EN));
 417         } else {
 418                 __twl4030_phy_power(twl, 0);
 419                 regulator_disable(twl->usb1v5);
 420                 regulator_disable(twl->usb1v8);
 421                 regulator_disable(twl->usb3v1);
 422         }
 423 }
 424
 425 static int twl4030_phy_power_off(struct phy *phy)
 426 {
 427         struct twl4030_usb *twl = phy_get_drvdata(phy);
 428
 429         if (twl->asleep)
 430                 return 0;
 431
 432         twl4030_phy_power(twl, 0);
 433         twl->asleep = 1;
 434         dev_dbg(twl->dev, "%s\n", __func__);
 435         return 0;
 436 }
 437
 438 static void __twl4030_phy_power_on(struct twl4030_usb *twl)
 439 {
 440         twl4030_phy_power(twl, 1);
 441         twl4030_i2c_access(twl, 1);
 442         twl4030_usb_set_mode(twl, twl->usb_mode);
 443         if (twl->usb_mode == T2_USB_MODE_ULPI)
 444                 twl4030_i2c_access(twl, 0);
 445 }
 446
 447 static int twl4030_phy_power_on(struct phy *phy)
 448 {
 449         struct twl4030_usb *twl = phy_get_drvdata(phy);
 450
 451         if (!twl->asleep)
 452                 return 0;
 453         __twl4030_phy_power_on(twl);
 454         twl->asleep = 0;
 455         dev_dbg(twl->dev, "%s\n", __func__);
 456
 457         /*
 458          * XXX When VBUS gets driven after musb goes to A mode,
 459          * ID_PRES related interrupts no longer arrive, why?
 460          * Register itself is updated fine though, so we must poll.
 461          */
 462         if (twl->linkstat == OMAP_MUSB_ID_GROUND) {
 463                 cancel_delayed_work(&twl->id_workaround_work);
 464                 schedule_delayed_work(&twl->id_workaround_work, HZ);
 465         }
 466         return 0;
 467 }
 468
 469 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
 470 {
 471         /* Enable writing to power configuration registers */
 472         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
 473                          TWL4030_PM_MASTER_PROTECT_KEY);
 474
 475         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
 476                          TWL4030_PM_MASTER_PROTECT_KEY);
 477
 478         /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
 479         /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
 480
 481         /* input to VUSB3V1 LDO is from VBAT, not VBUS */
 482         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
 483
 484         /* Initialize 3.1V regulator */
 485         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
 486
 487         twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
 488         if (IS_ERR(twl->usb3v1))
 489                 return -ENODEV;
 490
 491         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
 492
 493         /* Initialize 1.5V regulator */
 494         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
 495
 496         twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
 497         if (IS_ERR(twl->usb1v5))
 498                 return -ENODEV;
 499
 500         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
 501
 502         /* Initialize 1.8V regulator */
 503         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
 504
 505         twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
 506         if (IS_ERR(twl->usb1v8))
 507                 return -ENODEV;
 508
 509         twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
 510
 511         /* disable access to power configuration registers */
 512         twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
 513                          TWL4030_PM_MASTER_PROTECT_KEY);
 514
 515         return 0;
 516 }
 517
 518 static ssize_t twl4030_usb_vbus_show(struct device *dev,
 519                 struct device_attribute *attr, char *buf)
 520 {
 521         struct twl4030_usb *twl = dev_get_drvdata(dev);
 522         unsigned long flags;
 523         int ret = -EINVAL;
 524
 525         spin_lock_irqsave(&twl->lock, flags);
 526         ret = sprintf(buf, "%s\n",
 527                         twl->vbus_supplied ? "on" : "off");
 528         spin_unlock_irqrestore(&twl->lock, flags);
 529
 530         return ret;
 531 }
 532 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
 533
 534 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
 535 {
 536         struct twl4030_usb *twl = _twl;
 537         enum omap_musb_vbus_id_status status;
 538         bool status_changed = false;
 539
 540         status = twl4030_usb_linkstat(twl);
 541
 542         spin_lock_irq(&twl->lock);
 543         if (status >= 0 && status != twl->linkstat) {
 544                 twl->linkstat = status;
 545                 status_changed = true;
 546         }
 547         spin_unlock_irq(&twl->lock);
 548
 549         if (status_changed) {
 550                 /* FIXME add a set_power() method so that B-devices can
 551                  * configure the charger appropriately.  It's not always
 552                  * correct to consume VBUS power, and how much current to
 553                  * consume is a function of the USB configuration chosen
 554                  * by the host.
 555                  *
 556                  * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
 557                  * its disconnect() sibling, when changing to/from the
 558                  * USB_LINK_VBUS state.  musb_hdrc won't care until it
 559                  * starts to handle softconnect right.
 560                  */
 561                 omap_musb_mailbox(status);
 562         }
 563         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 564
 565         return IRQ_HANDLED;
 566 }
 567
 568 static void twl4030_id_workaround_work(struct work_struct *work)
 569 {
 570         struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
 571                 id_workaround_work.work);
 572         enum omap_musb_vbus_id_status status;
 573         bool status_changed = false;
 574
 575         status = twl4030_usb_linkstat(twl);
 576
 577         spin_lock_irq(&twl->lock);
 578         if (status >= 0 && status != twl->linkstat) {
 579                 twl->linkstat = status;
 580                 status_changed = true;
 581         }
 582         spin_unlock_irq(&twl->lock);
 583
 584         if (status_changed) {
 585                 dev_dbg(twl->dev, "handle missing status change to %d\n",
 586                                 status);
 587                 omap_musb_mailbox(status);
 588         }
 589
 590         /* don't schedule during sleep - irq works right then */
 591         if (status == OMAP_MUSB_ID_GROUND && !twl->asleep) {
 592                 cancel_delayed_work(&twl->id_workaround_work);
 593                 schedule_delayed_work(&twl->id_workaround_work, HZ);
 594         }
 595 }
 596
 597 static int twl4030_phy_init(struct phy *phy)
 598 {
 599         struct twl4030_usb *twl = phy_get_drvdata(phy);
 600         enum omap_musb_vbus_id_status status;
 601
 602         /*
 603          * Start in sleep state, we'll get called through set_suspend()
 604          * callback when musb is runtime resumed and it's time to start.
 605          */
 606         __twl4030_phy_power(twl, 0);
 607         twl->asleep = 1;
 608
 609         status = twl4030_usb_linkstat(twl);
 610         twl->linkstat = status;
 611
 612         if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID) {
 613                 omap_musb_mailbox(twl->linkstat);
 614                 twl4030_phy_power_on(phy);
 615         }
 616
 617         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 618         return 0;
 619 }
 620
 621 static int twl4030_set_peripheral(struct usb_otg *otg,
 622                                         struct usb_gadget *gadget)
 623 {
 624         if (!otg)
 625                 return -ENODEV;
 626
 627         otg->gadget = gadget;
 628         if (!gadget)
 629                 otg->phy->state = OTG_STATE_UNDEFINED;
 630
 631         return 0;
 632 }
 633
 634 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
 635 {
 636         if (!otg)
 637                 return -ENODEV;
 638
 639         otg->host = host;
 640         if (!host)
 641                 otg->phy->state = OTG_STATE_UNDEFINED;
 642
 643         return 0;
 644 }
 645
 646 static const struct phy_ops ops = {
 647         .init           = twl4030_phy_init,
 648         .power_on       = twl4030_phy_power_on,
 649         .power_off      = twl4030_phy_power_off,
 650         .owner          = THIS_MODULE,
 651 };
 652
 653 static int twl4030_usb_probe(struct platform_device *pdev)
 654 {
 655         struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
 656         struct twl4030_usb      *twl;
 657         struct phy              *phy;
 658         int                     status, err;
 659         struct usb_otg          *otg;
 660         struct device_node      *np = pdev->dev.of_node;
 661         struct phy_provider     *phy_provider;
 662         struct phy_init_data    *init_data = NULL;
 663
 664         twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
 665         if (!twl)
 666                 return -ENOMEM;
 667
 668         if (np)
 669                 of_property_read_u32(np, "usb_mode",
 670                                 (enum twl4030_usb_mode *)&twl->usb_mode);
 671         else if (pdata) {
 672                 twl->usb_mode = pdata->usb_mode;
 673                 init_data = pdata->init_data;
 674         } else {
 675                 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
 676                 return -EINVAL;
 677         }
 678
 679         otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
 680         if (!otg)
 681                 return -ENOMEM;
 682
 683         twl->dev                = &pdev->dev;
 684         twl->irq                = platform_get_irq(pdev, 0);
 685         twl->vbus_supplied      = false;
 686         twl->asleep             = 1;
 687         twl->linkstat           = OMAP_MUSB_UNKNOWN;
 688
 689         twl->phy.dev            = twl->dev;
 690         twl->phy.label          = "twl4030";
 691         twl->phy.otg            = otg;
 692         twl->phy.type           = USB_PHY_TYPE_USB2;
 693
 694         otg->phy                = &twl->phy;
 695         otg->set_host           = twl4030_set_host;
 696         otg->set_peripheral     = twl4030_set_peripheral;
 697
 698         phy_provider = devm_of_phy_provider_register(twl->dev,
 699                 of_phy_simple_xlate);
 700         if (IS_ERR(phy_provider))
 701                 return PTR_ERR(phy_provider);
 702
 703         phy = devm_phy_create(twl->dev, &ops, init_data);
 704         if (IS_ERR(phy)) {
 705                 dev_dbg(&pdev->dev, "Failed to create PHY\n");
 706                 return PTR_ERR(phy);
 707         }
 708
 709         phy_set_drvdata(phy, twl);
 710
 711         /* init spinlock for workqueue */
 712         spin_lock_init(&twl->lock);
 713
 714         INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
 715
 716         err = twl4030_usb_ldo_init(twl);
 717         if (err) {
 718                 dev_err(&pdev->dev, "ldo init failed\n");
 719                 return err;
 720         }
 721         usb_add_phy_dev(&twl->phy);
 722
 723         platform_set_drvdata(pdev, twl);
 724         if (device_create_file(&pdev->dev, &dev_attr_vbus))
 725                 dev_warn(&pdev->dev, "could not create sysfs file\n");
 726
 727         ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
 728
 729         /* Our job is to use irqs and status from the power module
 730          * to keep the transceiver disabled when nothing's connected.
 731          *
 732          * FIXME we actually shouldn't start enabling it until the
 733          * USB controller drivers have said they're ready, by calling
 734          * set_host() and/or set_peripheral() ... OTG_capable boards
 735          * need both handles, otherwise just one suffices.
 736          */
 737         twl->irq_enabled = true;
 738         status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
 739                         twl4030_usb_irq, IRQF_TRIGGER_FALLING |
 740                         IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
 741         if (status < 0) {
 742                 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
 743                         twl->irq, status);
 744                 return status;
 745         }
 746
 747         dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
 748         return 0;
 749 }
 750
 751 static int twl4030_usb_remove(struct platform_device *pdev)
 752 {
 753         struct twl4030_usb *twl = platform_get_drvdata(pdev);
 754         int val;
 755
 756         cancel_delayed_work(&twl->id_workaround_work);
 757         device_remove_file(twl->dev, &dev_attr_vbus);
 758
 759         /* set transceiver mode to power on defaults */
 760         twl4030_usb_set_mode(twl, -1);
 761
 762         /* autogate 60MHz ULPI clock,
 763          * clear dpll clock request for i2c access,
 764          * disable 32KHz
 765          */
 766         val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 767         if (val >= 0) {
 768                 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
 769                 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
 770                 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
 771         }
 772
 773         /* disable complete OTG block */
 774         twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 775
 776         if (!twl->asleep)
 777                 twl4030_phy_power(twl, 0);
 778
 779         return 0;
 780 }
 781
 782 #ifdef CONFIG_OF
 783 static const struct of_device_id twl4030_usb_id_table[] = {
 784         { .compatible = "ti,twl4030-usb" },
 785         {}
 786 };
 787 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
 788 #endif
 789
 790 static struct platform_driver twl4030_usb_driver = {
 791         .probe          = twl4030_usb_probe,
 792         .remove         = twl4030_usb_remove,
 793         .driver         = {
 794                 .name   = "twl4030_usb",
 795                 .owner  = THIS_MODULE,
 796                 .of_match_table = of_match_ptr(twl4030_usb_id_table),
 797         },
 798 };
 799
 800 static int __init twl4030_usb_init(void)
 801 {
 802         return platform_driver_register(&twl4030_usb_driver);
 803 }
 804 subsys_initcall(twl4030_usb_init);
 805
 806 static void __exit twl4030_usb_exit(void)
 807 {
 808         platform_driver_unregister(&twl4030_usb_driver);
 809 }
 810 module_exit(twl4030_usb_exit);
 811
 812 MODULE_ALIAS("platform:twl4030_usb");
 813 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
 814 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
 815 MODULE_LICENSE("GPL");