2 * simple driver for PWM (Pulse Width Modulator) controller
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
19 #include <linux/pwm.h>
21 #include <linux/of_device.h>
23 /* i.MX1 and i.MX21 share the same PWM function block: */
25 #define MX1_PWMC 0x00 /* PWM Control Register */
26 #define MX1_PWMS 0x04 /* PWM Sample Register */
27 #define MX1_PWMP 0x08 /* PWM Period Register */
29 #define MX1_PWMC_EN (1 << 4)
31 /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
33 #define MX3_PWMCR 0x00 /* PWM Control Register */
34 #define MX3_PWMSR 0x04 /* PWM Status Register */
35 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
36 #define MX3_PWMPR 0x10 /* PWM Period Register */
37 #define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
38 #define MX3_PWMCR_DOZEEN (1 << 24)
39 #define MX3_PWMCR_WAITEN (1 << 23)
40 #define MX3_PWMCR_DBGEN (1 << 22)
41 #define MX3_PWMCR_POUTC (1 << 18)
42 #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
43 #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
44 #define MX3_PWMCR_SWR (1 << 3)
45 #define MX3_PWMCR_EN (1 << 0)
46 #define MX3_PWMSR_FIFOAV_4WORDS 0x4
47 #define MX3_PWMSR_FIFOAV_MASK 0x7
49 #define MX3_PWM_SWR_LOOP 5
55 void __iomem *mmio_base;
59 int (*config)(struct pwm_chip *chip,
60 struct pwm_device *pwm, int duty_ns, int period_ns);
61 void (*set_enable)(struct pwm_chip *chip, bool enable);
64 #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
66 static int imx_pwm_config_v1(struct pwm_chip *chip,
67 struct pwm_device *pwm, int duty_ns, int period_ns)
69 struct imx_chip *imx = to_imx_chip(chip);
72 * The PWM subsystem allows for exact frequencies. However,
73 * I cannot connect a scope on my device to the PWM line and
74 * thus cannot provide the program the PWM controller
75 * exactly. Instead, I'm relying on the fact that the
76 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
77 * function group already. So I'll just modify the PWM sample
78 * register to follow the ratio of duty_ns vs. period_ns
81 * This is good enough for programming the brightness of
84 * The real implementation would divide PERCLK[0] first by
85 * both the prescaler (/1 .. /128) and then by CLKSEL
88 u32 max = readl(imx->mmio_base + MX1_PWMP);
89 u32 p = max * duty_ns / period_ns;
90 writel(max - p, imx->mmio_base + MX1_PWMS);
95 static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
97 struct imx_chip *imx = to_imx_chip(chip);
100 val = readl(imx->mmio_base + MX1_PWMC);
107 writel(val, imx->mmio_base + MX1_PWMC);
110 static int imx_pwm_config_v2(struct pwm_chip *chip,
111 struct pwm_device *pwm, int duty_ns, int period_ns)
113 struct imx_chip *imx = to_imx_chip(chip);
114 struct device *dev = chip->dev;
115 unsigned long long c;
116 unsigned long period_cycles, duty_cycles, prescale;
117 unsigned int period_ms;
118 bool enable = pwm_is_enabled(pwm);
119 int wait_count = 0, fifoav;
123 * i.MX PWMv2 has a 4-word sample FIFO.
124 * In order to avoid FIFO overflow issue, we do software reset
125 * to clear all sample FIFO if the controller is disabled or
126 * wait for a full PWM cycle to get a relinquished FIFO slot
127 * when the controller is enabled and the FIFO is fully loaded.
130 sr = readl(imx->mmio_base + MX3_PWMSR);
131 fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
132 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
133 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
137 sr = readl(imx->mmio_base + MX3_PWMSR);
138 if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
139 dev_warn(dev, "there is no free FIFO slot\n");
142 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
144 usleep_range(200, 1000);
145 cr = readl(imx->mmio_base + MX3_PWMCR);
146 } while ((cr & MX3_PWMCR_SWR) &&
147 (wait_count++ < MX3_PWM_SWR_LOOP));
149 if (cr & MX3_PWMCR_SWR)
150 dev_warn(dev, "software reset timeout\n");
153 c = clk_get_rate(imx->clk_per);
155 do_div(c, 1000000000);
158 prescale = period_cycles / 0x10000 + 1;
160 period_cycles /= prescale;
161 c = (unsigned long long)period_cycles * duty_ns;
162 do_div(c, period_ns);
166 * according to imx pwm RM, the real period value should be
167 * PERIOD value in PWMPR plus 2.
169 if (period_cycles > 2)
174 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
175 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
177 cr = MX3_PWMCR_PRESCALER(prescale) |
178 MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
179 MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
184 if (pwm->polarity == PWM_POLARITY_INVERSED)
185 cr |= MX3_PWMCR_POUTC;
187 writel(cr, imx->mmio_base + MX3_PWMCR);
192 static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
194 struct imx_chip *imx = to_imx_chip(chip);
197 val = readl(imx->mmio_base + MX3_PWMCR);
202 val &= ~MX3_PWMCR_EN;
204 if (chip->pwms[0].polarity == PWM_POLARITY_INVERSED)
205 val |= MX3_PWMCR_POUTC;
207 val &= ~MX3_PWMCR_POUTC;
209 writel(val, imx->mmio_base + MX3_PWMCR);
212 static int imx_pwm_config(struct pwm_chip *chip,
213 struct pwm_device *pwm, int duty_ns, int period_ns)
215 struct imx_chip *imx = to_imx_chip(chip);
218 ret = clk_prepare_enable(imx->clk_ipg);
222 ret = imx->config(chip, pwm, duty_ns, period_ns);
224 clk_disable_unprepare(imx->clk_ipg);
229 static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
231 struct imx_chip *imx = to_imx_chip(chip);
234 ret = clk_prepare_enable(imx->clk_per);
238 imx->set_enable(chip, true);
243 static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
245 struct imx_chip *imx = to_imx_chip(chip);
247 imx->set_enable(chip, false);
249 clk_disable_unprepare(imx->clk_per);
252 static int imx_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
253 enum pwm_polarity polarity)
255 struct imx_chip *imx = to_imx_chip(chip);
257 dev_dbg(imx->chip.dev, "%s: polarity set to %s\n", __func__,
258 polarity == PWM_POLARITY_INVERSED ? "inverted" : "normal");
263 static struct pwm_ops imx_pwm_ops_v1 = {
264 .enable = imx_pwm_enable,
265 .disable = imx_pwm_disable,
266 .config = imx_pwm_config,
267 .owner = THIS_MODULE,
270 static struct pwm_ops imx_pwm_ops_v2 = {
271 .enable = imx_pwm_enable,
272 .disable = imx_pwm_disable,
273 .set_polarity = imx_pwm_set_polarity,
274 .config = imx_pwm_config,
275 .owner = THIS_MODULE,
278 struct imx_pwm_data {
279 int (*config)(struct pwm_chip *chip,
280 struct pwm_device *pwm, int duty_ns, int period_ns);
281 void (*set_enable)(struct pwm_chip *chip, bool enable);
282 struct pwm_ops *pwm_ops;
285 static struct imx_pwm_data imx_pwm_data_v1 = {
286 .config = imx_pwm_config_v1,
287 .set_enable = imx_pwm_set_enable_v1,
288 .pwm_ops = &imx_pwm_ops_v1,
291 static struct imx_pwm_data imx_pwm_data_v2 = {
292 .config = imx_pwm_config_v2,
293 .set_enable = imx_pwm_set_enable_v2,
294 .pwm_ops = &imx_pwm_ops_v2,
297 static const struct of_device_id imx_pwm_dt_ids[] = {
298 { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
299 { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
302 MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
304 static int imx_pwm_probe(struct platform_device *pdev)
306 const struct of_device_id *of_id =
307 of_match_device(imx_pwm_dt_ids, &pdev->dev);
308 const struct imx_pwm_data *data;
309 struct imx_chip *imx;
318 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
322 imx->clk_per = devm_clk_get(&pdev->dev, "per");
323 if (IS_ERR(imx->clk_per)) {
324 dev_err(&pdev->dev, "getting per clock failed with %ld\n",
325 PTR_ERR(imx->clk_per));
326 return PTR_ERR(imx->clk_per);
329 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
330 if (IS_ERR(imx->clk_ipg)) {
331 dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
332 PTR_ERR(imx->clk_ipg));
333 return PTR_ERR(imx->clk_ipg);
336 imx->chip.ops = data->pwm_ops;
337 imx->chip.dev = &pdev->dev;
340 imx->chip.can_sleep = true;
341 if (data->pwm_ops->set_polarity) {
342 dev_dbg(&pdev->dev, "PWM supports output inversion\n");
343 imx->chip.of_xlate = of_pwm_xlate_with_flags;
344 imx->chip.of_pwm_n_cells = 3;
347 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
349 if (IS_ERR(imx->mmio_base))
350 return PTR_ERR(imx->mmio_base);
352 imx->config = data->config;
353 imx->set_enable = data->set_enable;
355 ret = pwmchip_add(&imx->chip);
359 platform_set_drvdata(pdev, imx);
363 static int imx_pwm_remove(struct platform_device *pdev)
365 struct imx_chip *imx;
367 imx = platform_get_drvdata(pdev);
371 return pwmchip_remove(&imx->chip);
374 static struct platform_driver imx_pwm_driver = {
377 .of_match_table = imx_pwm_dt_ids,
379 .probe = imx_pwm_probe,
380 .remove = imx_pwm_remove,
383 module_platform_driver(imx_pwm_driver);
385 MODULE_LICENSE("GPL v2");
386 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");