drivers/remoteproc/qcom_q6v5_pil.c

   1 /*
   2  * Qualcomm Peripheral Image Loader
   3  *
   4  * Copyright (C) 2016 Linaro Ltd.
   5  * Copyright (C) 2014 Sony Mobile Communications AB
   6  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/module.h>
  26 #include <linux/of_address.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regmap.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/remoteproc.h>
  31 #include <linux/reset.h>
  32 #include <linux/soc/qcom/smem.h>
  33 #include <linux/soc/qcom/smem_state.h>
  34
  35 #include "remoteproc_internal.h"
  36 #include "qcom_mdt_loader.h"
  37
  38 #include <linux/qcom_scm.h>
  39
  40 #define MBA_FIRMWARE_NAME               "mba.mbn"
  41 #define MPSS_FIRMWARE_NAME              "modem.mdt"
  42
  43 #define MPSS_CRASH_REASON_SMEM          421
  44
  45 /* RMB Status Register Values */
  46 #define RMB_PBL_SUCCESS                 0x1
  47
  48 #define RMB_MBA_XPU_UNLOCKED            0x1
  49 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  50 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  51 #define RMB_MBA_AUTH_COMPLETE           0x4
  52
  53 /* PBL/MBA interface registers */
  54 #define RMB_MBA_IMAGE_REG               0x00
  55 #define RMB_PBL_STATUS_REG              0x04
  56 #define RMB_MBA_COMMAND_REG             0x08
  57 #define RMB_MBA_STATUS_REG              0x0C
  58 #define RMB_PMI_META_DATA_REG           0x10
  59 #define RMB_PMI_CODE_START_REG          0x14
  60 #define RMB_PMI_CODE_LENGTH_REG         0x18
  61
  62 #define RMB_CMD_META_DATA_READY         0x1
  63 #define RMB_CMD_LOAD_READY              0x2
  64
  65 /* QDSP6SS Register Offsets */
  66 #define QDSP6SS_RESET_REG               0x014
  67 #define QDSP6SS_GFMUX_CTL_REG           0x020
  68 #define QDSP6SS_PWR_CTL_REG             0x030
  69
  70 /* AXI Halt Register Offsets */
  71 #define AXI_HALTREQ_REG                 0x0
  72 #define AXI_HALTACK_REG                 0x4
  73 #define AXI_IDLE_REG                    0x8
  74
  75 #define HALT_ACK_TIMEOUT_MS             100
  76
  77 /* QDSP6SS_RESET */
  78 #define Q6SS_STOP_CORE                  BIT(0)
  79 #define Q6SS_CORE_ARES                  BIT(1)
  80 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  81
  82 /* QDSP6SS_GFMUX_CTL */
  83 #define Q6SS_CLK_ENABLE                 BIT(1)
  84
  85 /* QDSP6SS_PWR_CTL */
  86 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
  87 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
  88 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
  89 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
  90 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
  91 #define Q6SS_L2DATA_STBY_N              BIT(18)
  92 #define Q6SS_SLP_RET_N                  BIT(19)
  93 #define Q6SS_CLAMP_IO                   BIT(20)
  94 #define QDSS_BHS_ON                     BIT(21)
  95 #define QDSS_LDO_BYP                    BIT(22)
  96
  97 struct q6v5 {
  98         struct device *dev;
  99         struct rproc *rproc;
 100
 101         void __iomem *reg_base;
 102         void __iomem *rmb_base;
 103
 104         struct regmap *halt_map;
 105         u32 halt_q6;
 106         u32 halt_modem;
 107         u32 halt_nc;
 108
 109         struct reset_control *mss_restart;
 110
 111         struct qcom_smem_state *state;
 112         unsigned stop_bit;
 113
 114         struct regulator_bulk_data supply[4];
 115
 116         struct clk *ahb_clk;
 117         struct clk *axi_clk;
 118         struct clk *rom_clk;
 119
 120         struct completion start_done;
 121         struct completion stop_done;
 122         bool running;
 123
 124         phys_addr_t mba_phys;
 125         void *mba_region;
 126         size_t mba_size;
 127
 128         phys_addr_t mpss_phys;
 129         phys_addr_t mpss_reloc;
 130         void *mpss_region;
 131         size_t mpss_size;
 132 };
 133
 134 enum {
 135         Q6V5_SUPPLY_CX,
 136         Q6V5_SUPPLY_MX,
 137         Q6V5_SUPPLY_MSS,
 138         Q6V5_SUPPLY_PLL,
 139 };
 140
 141 static int q6v5_regulator_init(struct q6v5 *qproc)
 142 {
 143         int ret;
 144
 145         qproc->supply[Q6V5_SUPPLY_CX].supply = "cx";
 146         qproc->supply[Q6V5_SUPPLY_MX].supply = "mx";
 147         qproc->supply[Q6V5_SUPPLY_MSS].supply = "mss";
 148         qproc->supply[Q6V5_SUPPLY_PLL].supply = "pll";
 149
 150         ret = devm_regulator_bulk_get(qproc->dev,
 151                                       ARRAY_SIZE(qproc->supply), qproc->supply);
 152         if (ret < 0) {
 153                 dev_err(qproc->dev, "failed to get supplies\n");
 154                 return ret;
 155         }
 156
 157         regulator_set_load(qproc->supply[Q6V5_SUPPLY_CX].consumer, 100000);
 158         regulator_set_load(qproc->supply[Q6V5_SUPPLY_MSS].consumer, 100000);
 159         regulator_set_load(qproc->supply[Q6V5_SUPPLY_PLL].consumer, 10000);
 160
 161         return 0;
 162 }
 163
 164 static int q6v5_regulator_enable(struct q6v5 *qproc)
 165 {
 166         int ret;
 167
 168         /* TODO: Q6V5_SUPPLY_CX is supposed to be set to super-turbo here */
 169         ret = regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MX].consumer,
 170                                     1050000, INT_MAX);
 171         if (ret)
 172                 return ret;
 173
 174         regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MSS].consumer,
 175                               1000000, 1150000);
 176
 177         return regulator_bulk_enable(ARRAY_SIZE(qproc->supply), qproc->supply);
 178 }
 179
 180 static void q6v5_regulator_disable(struct q6v5 *qproc)
 181 {
 182         regulator_bulk_disable(ARRAY_SIZE(qproc->supply), qproc->supply);
 183         regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_CX].consumer, 0, INT_MAX);
 184         regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MX].consumer, 0, INT_MAX);
 185         regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MSS].consumer, 0, 1150000);
 186 }
 187
 188 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 189 {
 190         struct q6v5 *qproc = rproc->priv;
 191
 192         memcpy(qproc->mba_region, fw->data, fw->size);
 193
 194         return 0;
 195 }
 196
 197 static const struct rproc_fw_ops q6v5_fw_ops = {
 198         .find_rsc_table = qcom_mdt_find_rsc_table,
 199         .load = q6v5_load,
 200 };
 201
 202 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 203 {
 204         unsigned long timeout;
 205         s32 val;
 206
 207         timeout = jiffies + msecs_to_jiffies(ms);
 208         for (;;) {
 209                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 210                 if (val)
 211                         break;
 212
 213                 if (time_after(jiffies, timeout))
 214                         return -ETIMEDOUT;
 215
 216                 msleep(1);
 217         }
 218
 219         return val;
 220 }
 221
 222 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 223 {
 224
 225         unsigned long timeout;
 226         s32 val;
 227
 228         timeout = jiffies + msecs_to_jiffies(ms);
 229         for (;;) {
 230                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 231                 if (val < 0)
 232                         break;
 233
 234                 if (!status && val)
 235                         break;
 236                 else if (status && val == status)
 237                         break;
 238
 239                 if (time_after(jiffies, timeout))
 240                         return -ETIMEDOUT;
 241
 242                 msleep(1);
 243         }
 244
 245         return val;
 246 }
 247
 248 static void q6v5proc_reset(struct q6v5 *qproc)
 249 {
 250         u32 val;
 251
 252         /* Assert resets, stop core */
 253         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 254         val |= (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE);
 255         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 256
 257         /* Enable power block headswitch, and wait for it to stabilize */
 258         val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 259         val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 260         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 261         mb();
 262         udelay(1);
 263
 264         /*
 265          * Turn on memories. L2 banks should be done individually
 266          * to minimize inrush current.
 267          */
 268         val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 269         val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 270                 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 271         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 272         val |= Q6SS_L2DATA_SLP_NRET_N_2;
 273         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 274         val |= Q6SS_L2DATA_SLP_NRET_N_1;
 275         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 276         val |= Q6SS_L2DATA_SLP_NRET_N_0;
 277         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 278
 279         /* Remove IO clamp */
 280         val &= ~Q6SS_CLAMP_IO;
 281         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 282
 283         /* Bring core out of reset */
 284         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 285         val &= ~Q6SS_CORE_ARES;
 286         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 287
 288         /* Turn on core clock */
 289         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 290         val |= Q6SS_CLK_ENABLE;
 291         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 292
 293         /* Start core execution */
 294         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 295         val &= ~Q6SS_STOP_CORE;
 296         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 297 }
 298
 299 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 300                                    struct regmap *halt_map,
 301                                    u32 offset)
 302 {
 303         unsigned long timeout;
 304         unsigned int val;
 305         int ret;
 306
 307         /* Check if we're already idle */
 308         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 309         if (!ret && val)
 310                 return;
 311
 312         /* Assert halt request */
 313         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 314
 315         /* Wait for halt */
 316         timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
 317         for (;;) {
 318                 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
 319                 if (ret || val || time_after(jiffies, timeout))
 320                         break;
 321
 322                 msleep(1);
 323         }
 324
 325         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 326         if (ret || !val)
 327                 dev_err(qproc->dev, "port failed halt\n");
 328
 329         /* Clear halt request (port will remain halted until reset) */
 330         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 331 }
 332
 333 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 334 {
 335         DEFINE_DMA_ATTRS(attrs);
 336         dma_addr_t phys;
 337         void *ptr;
 338         int ret;
 339
 340         dma_set_attr(DMA_ATTR_FORCE_CONTIGUOUS, &attrs);
 341         ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, &attrs);
 342         if (!ptr) {
 343                 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 344                 return -ENOMEM;
 345         }
 346
 347         memcpy(ptr, fw->data, fw->size);
 348
 349         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 350         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 351
 352         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 353         if (ret == -ETIMEDOUT)
 354                 dev_err(qproc->dev, "MBA header authentication timed out\n");
 355         else if (ret < 0)
 356                 dev_err(qproc->dev, "MBA returned error %d for MDT header\n", ret);
 357
 358         dma_free_attrs(qproc->dev, fw->size, ptr, phys, &attrs);
 359
 360         return ret < 0 ? ret : 0;
 361 }
 362
 363 static int q6v5_mpss_validate(struct q6v5 *qproc, const struct firmware *fw)
 364 {
 365         const struct elf32_phdr *phdrs;
 366         const struct elf32_phdr *phdr;
 367         struct elf32_hdr *ehdr;
 368         phys_addr_t boot_addr;
 369         phys_addr_t fw_addr;
 370         bool relocate;
 371         size_t size;
 372         u32 val;
 373         int ret;
 374         int i;
 375
 376         ret = qcom_mdt_parse(fw, &fw_addr, NULL, &relocate);
 377         if (ret) {
 378                 dev_err(qproc->dev, "failed to parse mdt header\n");
 379                 return ret;
 380         }
 381
 382         if (relocate)
 383                 boot_addr = qproc->mpss_phys;
 384         else
 385                 boot_addr = fw_addr;
 386
 387         ehdr = (struct elf32_hdr *)fw->data;
 388         phdrs = (struct elf32_phdr *)(ehdr + 1);
 389         for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
 390                 phdr = &phdrs[i];
 391
 392                 if (phdr->p_type != PT_LOAD)
 393                         continue;
 394
 395                 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
 396                         continue;
 397
 398                 if (!phdr->p_memsz)
 399                         continue;
 400
 401                 size = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 402                 if (!size) {
 403                         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
 404                         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 405                 }
 406
 407                 size += phdr->p_memsz;
 408                 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 409         }
 410
 411         val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 412         return val < 0 ? val : 0;
 413 }
 414
 415 static int q6v5_mpss_load(struct q6v5 *qproc)
 416 {
 417         const struct firmware *fw;
 418         phys_addr_t fw_addr;
 419         bool relocate;
 420         int ret;
 421
 422         ret = request_firmware(&fw, MPSS_FIRMWARE_NAME, qproc->dev);
 423         if (ret < 0) {
 424                 dev_err(qproc->dev, "unable to load " MPSS_FIRMWARE_NAME "\n");
 425                 return ret;
 426         }
 427
 428         ret = qcom_mdt_parse(fw, &fw_addr, NULL, &relocate);
 429         if (ret) {
 430                 dev_err(qproc->dev, "failed to parse mdt header\n");
 431                 goto release_firmware;
 432         }
 433
 434         if (relocate)
 435                 qproc->mpss_reloc = fw_addr;
 436
 437         /* Initialize the RMB validator */
 438         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
 439
 440         ret = q6v5_mpss_init_image(qproc, fw);
 441         if (ret)
 442                 goto release_firmware;
 443
 444         ret = qcom_mdt_load(qproc->rproc, fw, MPSS_FIRMWARE_NAME);
 445         if (ret)
 446                 goto release_firmware;
 447
 448         ret = q6v5_mpss_validate(qproc, fw);
 449         if (ret)
 450                 goto release_firmware;
 451
 452         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
 453         if (ret == -ETIMEDOUT)
 454                 dev_err(qproc->dev, "MBA authentication timed out\n");
 455         else if (ret < 0)
 456                 dev_err(qproc->dev, "MBA returned error %d\n", ret);
 457
 458 release_firmware:
 459         release_firmware(fw);
 460
 461         return ret < 0 ? ret : 0;
 462 }
 463
 464 static int q6v5_start(struct rproc *rproc)
 465 {
 466         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
 467         int ret;
 468
 469         ret = q6v5_regulator_enable(qproc);
 470         if (ret) {
 471                 dev_err(qproc->dev, "failed to enable supplies\n");
 472                 return ret;
 473         }
 474
 475         ret = reset_control_deassert(qproc->mss_restart);
 476         if (ret) {
 477                 dev_err(qproc->dev, "failed to deassert mss restart\n");
 478                 goto disable_vdd;
 479         }
 480
 481         ret = clk_prepare_enable(qproc->ahb_clk);
 482         if (ret)
 483                 goto assert_reset;
 484
 485         ret = clk_prepare_enable(qproc->axi_clk);
 486         if (ret)
 487                 goto disable_ahb_clk;
 488
 489         ret = clk_prepare_enable(qproc->rom_clk);
 490         if (ret)
 491                 goto disable_axi_clk;
 492
 493         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
 494
 495         q6v5proc_reset(qproc);
 496
 497         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 498         if (ret == -ETIMEDOUT) {
 499                 dev_err(qproc->dev, "PBL boot timed out\n");
 500                 goto halt_axi_ports;
 501         } else if (ret != RMB_PBL_SUCCESS) {
 502                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 503                 ret = -EINVAL;
 504                 goto halt_axi_ports;
 505         }
 506
 507         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
 508         if (ret == -ETIMEDOUT) {
 509                 dev_err(qproc->dev, "MBA boot timed out\n");
 510                 goto halt_axi_ports;
 511         } else if (ret != RMB_MBA_XPU_UNLOCKED && ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
 512                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
 513                 ret = -EINVAL;
 514                 goto halt_axi_ports;
 515         }
 516
 517         dev_info(qproc->dev, "MBA booted, loading mpss\n");
 518
 519         ret = q6v5_mpss_load(qproc);
 520         if (ret)
 521                 goto halt_axi_ports;
 522
 523         ret = wait_for_completion_timeout(&qproc->start_done,
 524                                           msecs_to_jiffies(5000));
 525         if (ret == 0) {
 526                 dev_err(qproc->dev, "start timed out\n");
 527                 ret = -ETIMEDOUT;
 528                 goto halt_axi_ports;
 529         }
 530
 531         qproc->running = true;
 532
 533         /* All done, release the handover resources */
 534
 535         return 0;
 536
 537 halt_axi_ports:
 538         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 539         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 540         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 541 disable_axi_clk:
 542         clk_disable_unprepare(qproc->axi_clk);
 543 disable_ahb_clk:
 544         clk_disable_unprepare(qproc->ahb_clk);
 545 assert_reset:
 546         reset_control_assert(qproc->mss_restart);
 547 disable_vdd:
 548         q6v5_regulator_disable(qproc);
 549
 550         return ret;
 551 }
 552
 553 static int q6v5_stop(struct rproc *rproc)
 554 {
 555         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
 556         int ret;
 557
 558         qproc->running = false;
 559
 560         qcom_smem_state_update_bits(qproc->state,
 561                                     BIT(qproc->stop_bit), BIT(qproc->stop_bit));
 562
 563         ret = wait_for_completion_timeout(&qproc->stop_done,
 564                                           msecs_to_jiffies(5000));
 565         if (ret == 0)
 566                 dev_err(qproc->dev, "timed out on wait\n");
 567
 568         qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
 569
 570         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
 571         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
 572         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
 573
 574         reset_control_assert(qproc->mss_restart);
 575         clk_disable_unprepare(qproc->axi_clk);
 576         clk_disable_unprepare(qproc->ahb_clk);
 577         q6v5_regulator_disable(qproc);
 578
 579         return 0;
 580 }
 581
 582 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
 583 {
 584         struct q6v5 *qproc = rproc->priv;
 585         int offset;
 586
 587         offset = da - qproc->mpss_reloc;
 588         if (offset < 0 || offset + len > qproc->mpss_size)
 589                 return NULL;
 590
 591         return qproc->mpss_region + offset;
 592 }
 593
 594 static const struct rproc_ops q6v5_ops = {
 595         .start = q6v5_start,
 596         .stop = q6v5_stop,
 597         .da_to_va = q6v5_da_to_va,
 598 };
 599
 600 static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
 601 {
 602         struct q6v5 *qproc = dev;
 603         size_t len;
 604         char *msg;
 605
 606         /* Sometimes the stop triggers a watchdog rather than a stop-ack */
 607         if (!qproc->running) {
 608                 complete(&qproc->stop_done);
 609                 return IRQ_HANDLED;
 610         }
 611
 612         msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
 613         if (!IS_ERR(msg) && len > 0 && msg[0])
 614                 dev_err(qproc->dev, "watchdog received: %s\n", msg);
 615         else
 616                 dev_err(qproc->dev, "watchdog without message\n");
 617
 618         rproc_report_crash(qproc->rproc, RPROC_WATCHDOG);
 619
 620         if (!IS_ERR(msg))
 621                 msg[0] = '\0';
 622
 623         return IRQ_HANDLED;
 624 }
 625
 626 static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
 627 {
 628         struct q6v5 *qproc = dev;
 629         size_t len;
 630         char *msg;
 631
 632         msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
 633         if (!IS_ERR(msg) && len > 0 && msg[0])
 634                 dev_err(qproc->dev, "fatal error received: %s\n", msg);
 635         else
 636                 dev_err(qproc->dev, "fatal error without message\n");
 637
 638         rproc_report_crash(qproc->rproc, RPROC_FATAL_ERROR);
 639
 640         if (!IS_ERR(msg))
 641                 msg[0] = '\0';
 642
 643         return IRQ_HANDLED;
 644 }
 645
 646 static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
 647 {
 648         struct q6v5 *qproc = dev;
 649
 650         complete(&qproc->start_done);
 651         return IRQ_HANDLED;
 652 }
 653
 654 static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
 655 {
 656         struct q6v5 *qproc = dev;
 657
 658         complete(&qproc->stop_done);
 659         return IRQ_HANDLED;
 660 }
 661
 662 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
 663 {
 664         struct device_node *halt_np;
 665         struct resource *res;
 666         int ret;
 667
 668         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
 669         qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
 670         if (IS_ERR(qproc->reg_base)) {
 671                 dev_err(qproc->dev, "failed to get qdsp6_base\n");
 672                 return PTR_ERR(qproc->reg_base);
 673         }
 674
 675         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
 676         qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
 677         if (IS_ERR(qproc->rmb_base)) {
 678                 dev_err(qproc->dev, "failed to get rmb_base\n");
 679                 return PTR_ERR(qproc->rmb_base);
 680         }
 681
 682         halt_np = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
 683         if (!halt_np) {
 684                 dev_err(&pdev->dev, "no qcom,halt-regs node\n");
 685                 return -ENODEV;
 686         }
 687
 688         qproc->halt_map = syscon_node_to_regmap(halt_np);
 689         if (IS_ERR(qproc->halt_map))
 690                 return PTR_ERR(qproc->halt_map);
 691
 692         ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
 693                                          1, &qproc->halt_q6);
 694         if (ret < 0) {
 695                 dev_err(&pdev->dev, "no q6 halt offset\n");
 696                 return -EINVAL;
 697         }
 698
 699         ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
 700                                          2, &qproc->halt_modem);
 701         if (ret < 0) {
 702                 dev_err(&pdev->dev, "no modem halt offset\n");
 703                 return -EINVAL;
 704         }
 705
 706         ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
 707                                          3, &qproc->halt_nc);
 708         if (ret < 0) {
 709                 dev_err(&pdev->dev, "no nc halt offset\n");
 710                 return -EINVAL;
 711         }
 712
 713         return 0;
 714 }
 715
 716 static int q6v5_init_clocks(struct q6v5 *qproc)
 717 {
 718         qproc->ahb_clk = devm_clk_get(qproc->dev, "iface");
 719         if (IS_ERR(qproc->ahb_clk)) {
 720                 dev_err(qproc->dev, "failed to get iface clock\n");
 721                 return PTR_ERR(qproc->ahb_clk);
 722         }
 723
 724         qproc->axi_clk = devm_clk_get(qproc->dev, "bus");
 725         if (IS_ERR(qproc->axi_clk)) {
 726                 dev_err(qproc->dev, "failed to get bus clock\n");
 727                 return PTR_ERR(qproc->axi_clk);
 728         }
 729
 730         qproc->rom_clk = devm_clk_get(qproc->dev, "mem");
 731         if (IS_ERR(qproc->rom_clk)) {
 732                 dev_err(qproc->dev, "failed to get mem clock\n");
 733                 return PTR_ERR(qproc->rom_clk);
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int q6v5_init_reset(struct q6v5 *qproc)
 740 {
 741         qproc->mss_restart = devm_reset_control_get(qproc->dev, NULL);
 742         if (IS_ERR(qproc->mss_restart)) {
 743                 dev_err(qproc->dev, "failed to acquire mss restart\n");
 744                 return PTR_ERR(qproc->mss_restart);
 745         }
 746
 747         return 0;
 748 }
 749
 750 static int q6v5_request_irq(struct q6v5 *qproc,
 751                              struct platform_device *pdev,
 752                              const char *name,
 753                              irq_handler_t thread_fn)
 754 {
 755         int ret;
 756
 757         ret = platform_get_irq_byname(pdev, name);
 758         if (ret < 0) {
 759                 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
 760                 return ret;
 761         }
 762
 763         ret = devm_request_threaded_irq(&pdev->dev, ret,
 764                                         NULL, thread_fn,
 765                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 766                                         "q6v5", qproc);
 767         if (ret)
 768                 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
 769         return ret;
 770 }
 771
 772 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
 773 {
 774         struct device_node *child;
 775         struct device_node *node;
 776         struct resource r;
 777         int ret;
 778
 779         child = of_get_child_by_name(qproc->dev->of_node, "mba");
 780         node = of_parse_phandle(child, "memory-region", 0);
 781         ret = of_address_to_resource(node, 0, &r);
 782         if (ret) {
 783                 dev_err(qproc->dev, "unable to resolve mba region\n");
 784                 return ret;
 785         }
 786
 787         qproc->mba_phys = r.start;
 788         qproc->mba_size = resource_size(&r);
 789         qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
 790         if (!qproc->mba_region) {
 791                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 792                         &r.start, qproc->mba_size);
 793                 return -EBUSY;
 794         }
 795
 796         child = of_get_child_by_name(qproc->dev->of_node, "mpss");
 797         node = of_parse_phandle(child, "memory-region", 0);
 798         ret = of_address_to_resource(node, 0, &r);
 799         if (ret) {
 800                 dev_err(qproc->dev, "unable to resolve mpss region\n");
 801                 return ret;
 802         }
 803
 804         qproc->mpss_phys = qproc->mpss_reloc = r.start;
 805         qproc->mpss_size = resource_size(&r);
 806         qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
 807         if (!qproc->mpss_region) {
 808                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 809                         &r.start, qproc->mpss_size);
 810                 return -EBUSY;
 811         }
 812
 813         return 0;
 814 }
 815
 816 static int q6v5_probe(struct platform_device *pdev)
 817 {
 818         struct q6v5 *qproc;
 819         struct rproc *rproc;
 820         int ret;
 821
 822         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
 823                             MBA_FIRMWARE_NAME, sizeof(*qproc));
 824         if (!rproc) {
 825                 dev_err(&pdev->dev, "failed to allocate rproc\n");
 826                 return -ENOMEM;
 827         }
 828
 829         rproc->fw_ops = &q6v5_fw_ops;
 830
 831         qproc = (struct q6v5 *)rproc->priv;
 832         qproc->dev = &pdev->dev;
 833         qproc->rproc = rproc;
 834         platform_set_drvdata(pdev, qproc);
 835
 836         init_completion(&qproc->start_done);
 837         init_completion(&qproc->stop_done);
 838
 839         ret = q6v5_init_mem(qproc, pdev);
 840         if (ret)
 841                 goto free_rproc;
 842
 843         ret = q6v5_alloc_memory_region(qproc);
 844         if (ret)
 845                 goto free_rproc;
 846
 847         ret = q6v5_init_clocks(qproc);
 848         if (ret)
 849                 goto free_rproc;
 850
 851         ret = q6v5_regulator_init(qproc);
 852         if (ret)
 853                 goto free_rproc;
 854
 855         ret = q6v5_init_reset(qproc);
 856         if (ret)
 857                 goto free_rproc;
 858
 859         ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
 860         if (ret < 0)
 861                 goto free_rproc;
 862
 863         ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt);
 864         if (ret < 0)
 865                 goto free_rproc;
 866
 867         ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
 868         if (ret < 0)
 869                 goto free_rproc;
 870
 871         ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
 872         if (ret < 0)
 873                 goto free_rproc;
 874
 875         qproc->state = qcom_smem_state_get(&pdev->dev, "stop", &qproc->stop_bit);
 876         if (IS_ERR(qproc->state))
 877                 goto free_rproc;
 878
 879         ret = rproc_add(rproc);
 880         if (ret)
 881                 goto free_rproc;
 882
 883         return 0;
 884
 885 free_rproc:
 886         rproc_put(rproc);
 887
 888         return ret;
 889 }
 890
 891 static int q6v5_remove(struct platform_device *pdev)
 892 {
 893         struct q6v5 *qproc = platform_get_drvdata(pdev);
 894
 895         rproc_del(qproc->rproc);
 896         rproc_put(qproc->rproc);
 897
 898         return 0;
 899 }
 900
 901 static const struct of_device_id q6v5_of_match[] = {
 902         { .compatible = "qcom,q6v5-pil", },
 903         { },
 904 };
 905
 906 static struct platform_driver q6v5_driver = {
 907         .probe = q6v5_probe,
 908         .remove = q6v5_remove,
 909         .driver = {
 910                 .name = "qcom-q6v5-pil",
 911                 .of_match_table = q6v5_of_match,
 912         },
 913 };
 914
 915 module_platform_driver(q6v5_driver);