drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44
  45 static struct scsi_transport_template *pm8001_stt;
  46
  47 /**
  48  * chip info structure to identify chip key functionality as
  49  * encryption available/not, no of ports, hw specific function ref
  50  */
  51 static const struct pm8001_chip_info pm8001_chips[] = {
  52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  60 };
  61 static int pm8001_id;
  62
  63 LIST_HEAD(hba_list);
  64
  65 struct workqueue_struct *pm8001_wq;
  66
  67 /**
  68  * The main structure which LLDD must register for scsi core.
  69  */
  70 static struct scsi_host_template pm8001_sht = {
  71         .module                 = THIS_MODULE,
  72         .name                   = DRV_NAME,
  73         .queuecommand           = sas_queuecommand,
  74         .target_alloc           = sas_target_alloc,
  75         .slave_configure        = sas_slave_configure,
  76         .scan_finished          = pm8001_scan_finished,
  77         .scan_start             = pm8001_scan_start,
  78         .change_queue_depth     = sas_change_queue_depth,
  79         .change_queue_type      = sas_change_queue_type,
  80         .bios_param             = sas_bios_param,
  81         .can_queue              = 1,
  82         .cmd_per_lun            = 1,
  83         .this_id                = -1,
  84         .sg_tablesize           = SG_ALL,
  85         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  86         .use_clustering         = ENABLE_CLUSTERING,
  87         .eh_device_reset_handler = sas_eh_device_reset_handler,
  88         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
  89         .target_destroy         = sas_target_destroy,
  90         .ioctl                  = sas_ioctl,
  91         .shost_attrs            = pm8001_host_attrs,
  92 };
  93
  94 /**
  95  * Sas layer call this function to execute specific task.
  96  */
  97 static struct sas_domain_function_template pm8001_transport_ops = {
  98         .lldd_dev_found         = pm8001_dev_found,
  99         .lldd_dev_gone          = pm8001_dev_gone,
 100
 101         .lldd_execute_task      = pm8001_queue_command,
 102         .lldd_control_phy       = pm8001_phy_control,
 103
 104         .lldd_abort_task        = pm8001_abort_task,
 105         .lldd_abort_task_set    = pm8001_abort_task_set,
 106         .lldd_clear_aca         = pm8001_clear_aca,
 107         .lldd_clear_task_set    = pm8001_clear_task_set,
 108         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 109         .lldd_lu_reset          = pm8001_lu_reset,
 110         .lldd_query_task        = pm8001_query_task,
 111 };
 112
 113 /**
 114  *pm8001_phy_init - initiate our adapter phys
 115  *@pm8001_ha: our hba structure.
 116  *@phy_id: phy id.
 117  */
 118 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 119 {
 120         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 121         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 122         phy->phy_state = 0;
 123         phy->pm8001_ha = pm8001_ha;
 124         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 125         sas_phy->class = SAS;
 126         sas_phy->iproto = SAS_PROTOCOL_ALL;
 127         sas_phy->tproto = 0;
 128         sas_phy->type = PHY_TYPE_PHYSICAL;
 129         sas_phy->role = PHY_ROLE_INITIATOR;
 130         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 131         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 132         sas_phy->id = phy_id;
 133         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
 134         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 135         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 136         sas_phy->lldd_phy = phy;
 137 }
 138
 139 /**
 140  *pm8001_free - free hba
 141  *@pm8001_ha:   our hba structure.
 142  *
 143  */
 144 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 145 {
 146         int i;
 147
 148         if (!pm8001_ha)
 149                 return;
 150
 151         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 152                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 153                         pci_free_consistent(pm8001_ha->pdev,
 154                                 (pm8001_ha->memoryMap.region[i].total_len +
 155                                 pm8001_ha->memoryMap.region[i].alignment),
 156                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 157                                 pm8001_ha->memoryMap.region[i].phys_addr);
 158                         }
 159         }
 160         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 161         if (pm8001_ha->shost)
 162                 scsi_host_put(pm8001_ha->shost);
 163         flush_workqueue(pm8001_wq);
 164         kfree(pm8001_ha->tags);
 165         kfree(pm8001_ha);
 166 }
 167
 168 #ifdef PM8001_USE_TASKLET
 169
 170 /**
 171  * tasklet for 64 msi-x interrupt handler
 172  * @opaque: the passed general host adapter struct
 173  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 174  */
 175 static void pm8001_tasklet(unsigned long opaque)
 176 {
 177         struct pm8001_hba_info *pm8001_ha;
 178         u32 vec;
 179         pm8001_ha = (struct pm8001_hba_info *)opaque;
 180         if (unlikely(!pm8001_ha))
 181                 BUG_ON(1);
 182         vec = pm8001_ha->int_vector;
 183         PM8001_CHIP_DISP->isr(pm8001_ha, vec);
 184 }
 185 #endif
 186
 187 static struct  pm8001_hba_info *outq_to_hba(u8 *outq)
 188 {
 189         return container_of((outq - *outq), struct pm8001_hba_info, outq[0]);
 190 }
 191
 192 /**
 193  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 194  * It obtains the vector number and calls the equivalent bottom
 195  * half or services directly.
 196  * @opaque: the passed outbound queue/vector. Host structure is
 197  * retrieved from the same.
 198  */
 199 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 200 {
 201         struct pm8001_hba_info *pm8001_ha = outq_to_hba(opaque);
 202         u8 outq = *(u8 *)opaque;
 203         irqreturn_t ret = IRQ_HANDLED;
 204         if (unlikely(!pm8001_ha))
 205                 return IRQ_NONE;
 206         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 207                 return IRQ_NONE;
 208         pm8001_ha->int_vector = outq;
 209 #ifdef PM8001_USE_TASKLET
 210         tasklet_schedule(&pm8001_ha->tasklet);
 211 #else
 212         ret = PM8001_CHIP_DISP->isr(pm8001_ha, outq);
 213 #endif
 214         return ret;
 215 }
 216
 217 /**
 218  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 219  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 220  */
 221
 222 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 223 {
 224         struct pm8001_hba_info *pm8001_ha;
 225         irqreturn_t ret = IRQ_HANDLED;
 226         struct sas_ha_struct *sha = dev_id;
 227         pm8001_ha = sha->lldd_ha;
 228         if (unlikely(!pm8001_ha))
 229                 return IRQ_NONE;
 230         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 231                 return IRQ_NONE;
 232
 233         pm8001_ha->int_vector = 0;
 234 #ifdef PM8001_USE_TASKLET
 235         tasklet_schedule(&pm8001_ha->tasklet);
 236 #else
 237         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 238 #endif
 239         return ret;
 240 }
 241
 242 /**
 243  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 244  * @pm8001_ha:our hba structure.
 245  *
 246  */
 247 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 248                         const struct pci_device_id *ent)
 249 {
 250         int i;
 251         spin_lock_init(&pm8001_ha->lock);
 252         PM8001_INIT_DBG(pm8001_ha,
 253                 pm8001_printk("pm8001_alloc: PHY:%x\n",
 254                                 pm8001_ha->chip->n_phy));
 255         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 256                 pm8001_phy_init(pm8001_ha, i);
 257                 pm8001_ha->port[i].wide_port_phymap = 0;
 258                 pm8001_ha->port[i].port_attached = 0;
 259                 pm8001_ha->port[i].port_state = 0;
 260                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 261         }
 262
 263         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
 264         if (!pm8001_ha->tags)
 265                 goto err_out;
 266         /* MPI Memory region 1 for AAP Event Log for fw */
 267         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 268         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 269         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 270         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 271
 272         /* MPI Memory region 2 for IOP Event Log for fw */
 273         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 274         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 275         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 276         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 277
 278         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 279                 /* MPI Memory region 3 for consumer Index of inbound queues */
 280                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
 281                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
 282                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
 283                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
 284
 285                 if ((ent->driver_data) != chip_8001) {
 286                         /* MPI Memory region 5 inbound queues */
 287                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 288                                                 PM8001_MPI_QUEUE;
 289                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
 290                         pm8001_ha->memoryMap.region[IB+i].total_len =
 291                                                 PM8001_MPI_QUEUE * 128;
 292                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
 293                 } else {
 294                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 295                                                 PM8001_MPI_QUEUE;
 296                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
 297                         pm8001_ha->memoryMap.region[IB+i].total_len =
 298                                                 PM8001_MPI_QUEUE * 64;
 299                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
 300                 }
 301         }
 302
 303         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 304                 /* MPI Memory region 4 for producer Index of outbound queues */
 305                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
 306                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
 307                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
 308                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
 309
 310                 if (ent->driver_data != chip_8001) {
 311                         /* MPI Memory region 6 Outbound queues */
 312                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 313                                                 PM8001_MPI_QUEUE;
 314                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
 315                         pm8001_ha->memoryMap.region[OB+i].total_len =
 316                                                 PM8001_MPI_QUEUE * 128;
 317                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
 318                 } else {
 319                         /* MPI Memory region 6 Outbound queues */
 320                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 321                                                 PM8001_MPI_QUEUE;
 322                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
 323                         pm8001_ha->memoryMap.region[OB+i].total_len =
 324                                                 PM8001_MPI_QUEUE * 64;
 325                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
 326                 }
 327
 328         }
 329         /* Memory region write DMA*/
 330         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 331         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 332         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 333         /* Memory region for devices*/
 334         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
 335         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
 336                 sizeof(struct pm8001_device);
 337         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
 338                 sizeof(struct pm8001_device);
 339
 340         /* Memory region for ccb_info*/
 341         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
 342         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
 343                 sizeof(struct pm8001_ccb_info);
 344         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
 345                 sizeof(struct pm8001_ccb_info);
 346
 347         /* Memory region for fw flash */
 348         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 349
 350         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 351                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 352                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 353                         &pm8001_ha->memoryMap.region[i].phys_addr,
 354                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 355                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 356                         pm8001_ha->memoryMap.region[i].total_len,
 357                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 358                                 PM8001_FAIL_DBG(pm8001_ha,
 359                                         pm8001_printk("Mem%d alloc failed\n",
 360                                         i));
 361                                 goto err_out;
 362                 }
 363         }
 364
 365         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
 366         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 367                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 368                 pm8001_ha->devices[i].id = i;
 369                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 370                 pm8001_ha->devices[i].running_req = 0;
 371         }
 372         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
 373         for (i = 0; i < PM8001_MAX_CCB; i++) {
 374                 pm8001_ha->ccb_info[i].ccb_dma_handle =
 375                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
 376                         i * sizeof(struct pm8001_ccb_info);
 377                 pm8001_ha->ccb_info[i].task = NULL;
 378                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
 379                 pm8001_ha->ccb_info[i].device = NULL;
 380                 ++pm8001_ha->tags_num;
 381         }
 382         pm8001_ha->flags = PM8001F_INIT_TIME;
 383         /* Initialize tags */
 384         pm8001_tag_init(pm8001_ha);
 385         return 0;
 386 err_out:
 387         return 1;
 388 }
 389
 390 /**
 391  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 392  * address so that we can access them.
 393  * @pm8001_ha:our hba structure.
 394  */
 395 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 396 {
 397         u32 bar;
 398         u32 logicalBar = 0;
 399         struct pci_dev *pdev;
 400
 401         pdev = pm8001_ha->pdev;
 402         /* map pci mem (PMC pci base 0-3)*/
 403         for (bar = 0; bar < 6; bar++) {
 404                 /*
 405                 ** logical BARs for SPC:
 406                 ** bar 0 and 1 - logical BAR0
 407                 ** bar 2 and 3 - logical BAR1
 408                 ** bar4 - logical BAR2
 409                 ** bar5 - logical BAR3
 410                 ** Skip the appropriate assignments:
 411                 */
 412                 if ((bar == 1) || (bar == 3))
 413                         continue;
 414                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 415                         pm8001_ha->io_mem[logicalBar].membase =
 416                                 pci_resource_start(pdev, bar);
 417                         pm8001_ha->io_mem[logicalBar].membase &=
 418                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
 419                         pm8001_ha->io_mem[logicalBar].memsize =
 420                                 pci_resource_len(pdev, bar);
 421                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 422                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 423                                 pm8001_ha->io_mem[logicalBar].memsize);
 424                         PM8001_INIT_DBG(pm8001_ha,
 425                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
 426                                 bar, logicalBar));
 427                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 428                                 "base addr %llx virt_addr=%llx len=%d\n",
 429                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
 430                                 (u64)(unsigned long)
 431                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
 432                                 pm8001_ha->io_mem[logicalBar].memsize));
 433                 } else {
 434                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 435                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 436                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
 437                 }
 438                 logicalBar++;
 439         }
 440         return 0;
 441 }
 442
 443 /**
 444  * pm8001_pci_alloc - initialize our ha card structure
 445  * @pdev: pci device.
 446  * @ent: ent
 447  * @shost: scsi host struct which has been initialized before.
 448  */
 449 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 450                                  const struct pci_device_id *ent,
 451                                 struct Scsi_Host *shost)
 452
 453 {
 454         struct pm8001_hba_info *pm8001_ha;
 455         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 456
 457
 458         pm8001_ha = sha->lldd_ha;
 459         if (!pm8001_ha)
 460                 return NULL;
 461
 462         pm8001_ha->pdev = pdev;
 463         pm8001_ha->dev = &pdev->dev;
 464         pm8001_ha->chip_id = ent->driver_data;
 465         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 466         pm8001_ha->irq = pdev->irq;
 467         pm8001_ha->sas = sha;
 468         pm8001_ha->shost = shost;
 469         pm8001_ha->id = pm8001_id++;
 470         pm8001_ha->logging_level = 0x01;
 471         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 472         /* IOMB size is 128 for 8088/89 controllers */
 473         if (pm8001_ha->chip_id != chip_8001)
 474                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 475         else
 476                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 477
 478 #ifdef PM8001_USE_TASKLET
 479         /**
 480         * default tasklet for non msi-x interrupt handler/first msi-x
 481         * interrupt handler
 482         **/
 483         tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
 484                         (unsigned long)pm8001_ha);
 485 #endif
 486         pm8001_ioremap(pm8001_ha);
 487         if (!pm8001_alloc(pm8001_ha, ent))
 488                 return pm8001_ha;
 489         pm8001_free(pm8001_ha);
 490         return NULL;
 491 }
 492
 493 /**
 494  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 495  * @pdev: pci device.
 496  */
 497 static int pci_go_44(struct pci_dev *pdev)
 498 {
 499         int rc;
 500
 501         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
 502                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
 503                 if (rc) {
 504                         rc = pci_set_consistent_dma_mask(pdev,
 505                                 DMA_BIT_MASK(32));
 506                         if (rc) {
 507                                 dev_printk(KERN_ERR, &pdev->dev,
 508                                         "44-bit DMA enable failed\n");
 509                                 return rc;
 510                         }
 511                 }
 512         } else {
 513                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 514                 if (rc) {
 515                         dev_printk(KERN_ERR, &pdev->dev,
 516                                 "32-bit DMA enable failed\n");
 517                         return rc;
 518                 }
 519                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 520                 if (rc) {
 521                         dev_printk(KERN_ERR, &pdev->dev,
 522                                 "32-bit consistent DMA enable failed\n");
 523                         return rc;
 524                 }
 525         }
 526         return rc;
 527 }
 528
 529 /**
 530  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 531  * @shost: scsi host which has been allocated outside.
 532  * @chip_info: our ha struct.
 533  */
 534 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 535                                    const struct pm8001_chip_info *chip_info)
 536 {
 537         int phy_nr, port_nr;
 538         struct asd_sas_phy **arr_phy;
 539         struct asd_sas_port **arr_port;
 540         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 541
 542         phy_nr = chip_info->n_phy;
 543         port_nr = phy_nr;
 544         memset(sha, 0x00, sizeof(*sha));
 545         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 546         if (!arr_phy)
 547                 goto exit;
 548         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 549         if (!arr_port)
 550                 goto exit_free2;
 551
 552         sha->sas_phy = arr_phy;
 553         sha->sas_port = arr_port;
 554         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 555         if (!sha->lldd_ha)
 556                 goto exit_free1;
 557
 558         shost->transportt = pm8001_stt;
 559         shost->max_id = PM8001_MAX_DEVICES;
 560         shost->max_lun = 8;
 561         shost->max_channel = 0;
 562         shost->unique_id = pm8001_id;
 563         shost->max_cmd_len = 16;
 564         shost->can_queue = PM8001_CAN_QUEUE;
 565         shost->cmd_per_lun = 32;
 566         return 0;
 567 exit_free1:
 568         kfree(arr_port);
 569 exit_free2:
 570         kfree(arr_phy);
 571 exit:
 572         return -1;
 573 }
 574
 575 /**
 576  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 577  * @shost: scsi host which has been allocated outside
 578  * @chip_info: our ha struct.
 579  */
 580 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 581                                      const struct pm8001_chip_info *chip_info)
 582 {
 583         int i = 0;
 584         struct pm8001_hba_info *pm8001_ha;
 585         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 586
 587         pm8001_ha = sha->lldd_ha;
 588         for (i = 0; i < chip_info->n_phy; i++) {
 589                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 590                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 591         }
 592         sha->sas_ha_name = DRV_NAME;
 593         sha->dev = pm8001_ha->dev;
 594
 595         sha->lldd_module = THIS_MODULE;
 596         sha->sas_addr = &pm8001_ha->sas_addr[0];
 597         sha->num_phys = chip_info->n_phy;
 598         sha->lldd_max_execute_num = 1;
 599         sha->lldd_queue_size = PM8001_CAN_QUEUE;
 600         sha->core.shost = shost;
 601 }
 602
 603 /**
 604  * pm8001_init_sas_add - initialize sas address
 605  * @chip_info: our ha struct.
 606  *
 607  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 608  * it should read from the EEPROM
 609  */
 610 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 611 {
 612         u8 i, j;
 613 #ifdef PM8001_READ_VPD
 614         /* For new SPC controllers WWN is stored in flash vpd
 615         *  For SPC/SPCve controllers WWN is stored in EEPROM
 616         *  For Older SPC WWN is stored in NVMD
 617         */
 618         DECLARE_COMPLETION_ONSTACK(completion);
 619         struct pm8001_ioctl_payload payload;
 620         u16 deviceid;
 621         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 622         pm8001_ha->nvmd_completion = &completion;
 623
 624         if (pm8001_ha->chip_id == chip_8001) {
 625                 if (deviceid == 0x8081) {
 626                         payload.minor_function = 4;
 627                         payload.length = 4096;
 628                 } else {
 629                         payload.minor_function = 0;
 630                         payload.length = 128;
 631                 }
 632         } else {
 633                 payload.minor_function = 1;
 634                 payload.length = 4096;
 635         }
 636         payload.offset = 0;
 637         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
 638         PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 639         wait_for_completion(&completion);
 640
 641         for (i = 0, j = 0; i <= 7; i++, j++) {
 642                 if (pm8001_ha->chip_id == chip_8001) {
 643                         if (deviceid == 0x8081)
 644                                 pm8001_ha->sas_addr[j] =
 645                                         payload.func_specific[0x704 + i];
 646                 } else
 647                         pm8001_ha->sas_addr[j] =
 648                                         payload.func_specific[0x804 + i];
 649         }
 650
 651         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 652                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 653                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 654                 PM8001_INIT_DBG(pm8001_ha,
 655                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
 656                         pm8001_ha->phy[i].dev_sas_addr));
 657         }
 658 #else
 659         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 660                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 661                 pm8001_ha->phy[i].dev_sas_addr =
 662                         cpu_to_be64((u64)
 663                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 664         }
 665         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 666                 SAS_ADDR_SIZE);
 667 #endif
 668 }
 669
 670 /*
 671  * pm8001_get_phy_settings_info : Read phy setting values.
 672  * @pm8001_ha : our hba.
 673  */
 674 void pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 675 {
 676
 677 #ifdef PM8001_READ_VPD
 678         /*OPTION ROM FLASH read for the SPC cards */
 679         DECLARE_COMPLETION_ONSTACK(completion);
 680         struct pm8001_ioctl_payload payload;
 681
 682         pm8001_ha->nvmd_completion = &completion;
 683         /* SAS ADDRESS read from flash / EEPROM */
 684         payload.minor_function = 6;
 685         payload.offset = 0;
 686         payload.length = 4096;
 687         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 688         /* Read phy setting values from flash */
 689         PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 690         wait_for_completion(&completion);
 691         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 692 #endif
 693 }
 694
 695 #ifdef PM8001_USE_MSIX
 696 /**
 697  * pm8001_setup_msix - enable MSI-X interrupt
 698  * @chip_info: our ha struct.
 699  * @irq_handler: irq_handler
 700  */
 701 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 702 {
 703         u32 i = 0, j = 0;
 704         u32 number_of_intr;
 705         int flag = 0;
 706         u32 max_entry;
 707         int rc;
 708         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
 709
 710         /* SPCv controllers supports 64 msi-x */
 711         if (pm8001_ha->chip_id == chip_8001) {
 712                 number_of_intr = 1;
 713                 flag |= IRQF_DISABLED;
 714         } else {
 715                 number_of_intr = PM8001_MAX_MSIX_VEC;
 716                 flag &= ~IRQF_SHARED;
 717                 flag |= IRQF_DISABLED;
 718         }
 719
 720         max_entry = sizeof(pm8001_ha->msix_entries) /
 721                 sizeof(pm8001_ha->msix_entries[0]);
 722         for (i = 0; i < max_entry ; i++)
 723                 pm8001_ha->msix_entries[i].entry = i;
 724         rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries,
 725                 number_of_intr);
 726         pm8001_ha->number_of_intr = number_of_intr;
 727         if (!rc) {
 728                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 729                         "pci_enable_msix request ret:%d no of intr %d\n",
 730                                         rc, pm8001_ha->number_of_intr));
 731
 732                 for (i = 0; i < number_of_intr; i++)
 733                         pm8001_ha->outq[i] = i;
 734
 735                 for (i = 0; i < number_of_intr; i++) {
 736                         snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
 737                                         DRV_NAME"%d", i);
 738                         if (request_irq(pm8001_ha->msix_entries[i].vector,
 739                                 pm8001_interrupt_handler_msix, flag,
 740                                 intr_drvname[i], &pm8001_ha->outq[i])) {
 741                                 for (j = 0; j < i; j++)
 742                                         free_irq(
 743                                         pm8001_ha->msix_entries[j].vector,
 744                                         &pm8001_ha->outq[j]);
 745                                 pci_disable_msix(pm8001_ha->pdev);
 746                                 break;
 747                         }
 748                 }
 749         }
 750         return rc;
 751 }
 752 #endif
 753
 754 /**
 755  * pm8001_request_irq - register interrupt
 756  * @chip_info: our ha struct.
 757  */
 758 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
 759 {
 760         struct pci_dev *pdev;
 761         int rc;
 762
 763         pdev = pm8001_ha->pdev;
 764
 765 #ifdef PM8001_USE_MSIX
 766         if (pdev->msix_cap)
 767                 return pm8001_setup_msix(pm8001_ha);
 768         else {
 769                 PM8001_INIT_DBG(pm8001_ha,
 770                         pm8001_printk("MSIX not supported!!!\n"));
 771                 goto intx;
 772         }
 773 #endif
 774
 775 intx:
 776         /* initialize the INT-X interrupt */
 777         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
 778                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
 779         return rc;
 780 }
 781
 782 /**
 783  * pm8001_pci_probe - probe supported device
 784  * @pdev: pci device which kernel has been prepared for.
 785  * @ent: pci device id
 786  *
 787  * This function is the main initialization function, when register a new
 788  * pci driver it is invoked, all struct an hardware initilization should be done
 789  * here, also, register interrupt
 790  */
 791 static int pm8001_pci_probe(struct pci_dev *pdev,
 792                             const struct pci_device_id *ent)
 793 {
 794         unsigned int rc;
 795         u32     pci_reg;
 796         u8      i = 0;
 797         struct pm8001_hba_info *pm8001_ha;
 798         struct Scsi_Host *shost = NULL;
 799         const struct pm8001_chip_info *chip;
 800
 801         dev_printk(KERN_INFO, &pdev->dev,
 802                 "pm80xx: driver version %s\n", DRV_VERSION);
 803         rc = pci_enable_device(pdev);
 804         if (rc)
 805                 goto err_out_enable;
 806         pci_set_master(pdev);
 807         /*
 808          * Enable pci slot busmaster by setting pci command register.
 809          * This is required by FW for Cyclone card.
 810          */
 811
 812         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
 813         pci_reg |= 0x157;
 814         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
 815         rc = pci_request_regions(pdev, DRV_NAME);
 816         if (rc)
 817                 goto err_out_disable;
 818         rc = pci_go_44(pdev);
 819         if (rc)
 820                 goto err_out_regions;
 821
 822         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
 823         if (!shost) {
 824                 rc = -ENOMEM;
 825                 goto err_out_regions;
 826         }
 827         chip = &pm8001_chips[ent->driver_data];
 828         SHOST_TO_SAS_HA(shost) =
 829                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
 830         if (!SHOST_TO_SAS_HA(shost)) {
 831                 rc = -ENOMEM;
 832                 goto err_out_free_host;
 833         }
 834
 835         rc = pm8001_prep_sas_ha_init(shost, chip);
 836         if (rc) {
 837                 rc = -ENOMEM;
 838                 goto err_out_free;
 839         }
 840         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 841         /* ent->driver variable is used to differentiate between controllers */
 842         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
 843         if (!pm8001_ha) {
 844                 rc = -ENOMEM;
 845                 goto err_out_free;
 846         }
 847         list_add_tail(&pm8001_ha->list, &hba_list);
 848         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 849         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
 850         if (rc) {
 851                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 852                         "chip_init failed [ret: %d]\n", rc));
 853                 goto err_out_ha_free;
 854         }
 855
 856         rc = scsi_add_host(shost, &pdev->dev);
 857         if (rc)
 858                 goto err_out_ha_free;
 859         rc = pm8001_request_irq(pm8001_ha);
 860         if (rc) {
 861                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 862                         "pm8001_request_irq failed [ret: %d]\n", rc));
 863                 goto err_out_shost;
 864         }
 865
 866         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
 867         if (pm8001_ha->chip_id != chip_8001) {
 868                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
 869                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
 870                 /* setup thermal configuration. */
 871                 pm80xx_set_thermal_config(pm8001_ha);
 872         }
 873
 874         pm8001_init_sas_add(pm8001_ha);
 875         /* phy setting support for motherboard controller */
 876         if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
 877                 pdev->subsystem_vendor != 0)
 878                 pm8001_get_phy_settings_info(pm8001_ha);
 879         pm8001_post_sas_ha_init(shost, chip);
 880         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 881         if (rc)
 882                 goto err_out_shost;
 883         scsi_scan_host(pm8001_ha->shost);
 884         return 0;
 885
 886 err_out_shost:
 887         scsi_remove_host(pm8001_ha->shost);
 888 err_out_ha_free:
 889         pm8001_free(pm8001_ha);
 890 err_out_free:
 891         kfree(SHOST_TO_SAS_HA(shost));
 892 err_out_free_host:
 893         kfree(shost);
 894 err_out_regions:
 895         pci_release_regions(pdev);
 896 err_out_disable:
 897         pci_disable_device(pdev);
 898 err_out_enable:
 899         return rc;
 900 }
 901
 902 static void pm8001_pci_remove(struct pci_dev *pdev)
 903 {
 904         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 905         struct pm8001_hba_info *pm8001_ha;
 906         int i;
 907         pm8001_ha = sha->lldd_ha;
 908         pci_set_drvdata(pdev, NULL);
 909         sas_unregister_ha(sha);
 910         sas_remove_host(pm8001_ha->shost);
 911         list_del(&pm8001_ha->list);
 912         scsi_remove_host(pm8001_ha->shost);
 913         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
 914         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 915
 916 #ifdef PM8001_USE_MSIX
 917         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 918                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
 919         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 920                 free_irq(pm8001_ha->msix_entries[i].vector,
 921                                 &pm8001_ha->outq[i]);
 922         pci_disable_msix(pdev);
 923 #else
 924         free_irq(pm8001_ha->irq, sha);
 925 #endif
 926 #ifdef PM8001_USE_TASKLET
 927         tasklet_kill(&pm8001_ha->tasklet);
 928 #endif
 929         pm8001_free(pm8001_ha);
 930         kfree(sha->sas_phy);
 931         kfree(sha->sas_port);
 932         kfree(sha);
 933         pci_release_regions(pdev);
 934         pci_disable_device(pdev);
 935 }
 936
 937 /**
 938  * pm8001_pci_suspend - power management suspend main entry point
 939  * @pdev: PCI device struct
 940  * @state: PM state change to (usually PCI_D3)
 941  *
 942  * Returns 0 success, anything else error.
 943  */
 944 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 945 {
 946         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 947         struct pm8001_hba_info *pm8001_ha;
 948         int i;
 949         u32 device_state;
 950         pm8001_ha = sha->lldd_ha;
 951         flush_workqueue(pm8001_wq);
 952         scsi_block_requests(pm8001_ha->shost);
 953         if (!pdev->pm_cap) {
 954                 dev_err(&pdev->dev, " PCI PM not supported\n");
 955                 return -ENODEV;
 956         }
 957         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
 958         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 959 #ifdef PM8001_USE_MSIX
 960         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 961                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
 962         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 963                 free_irq(pm8001_ha->msix_entries[i].vector,
 964                                 &pm8001_ha->outq[i]);
 965         pci_disable_msix(pdev);
 966 #else
 967         free_irq(pm8001_ha->irq, sha);
 968 #endif
 969 #ifdef PM8001_USE_TASKLET
 970         tasklet_kill(&pm8001_ha->tasklet);
 971 #endif
 972         device_state = pci_choose_state(pdev, state);
 973         pm8001_printk("pdev=0x%p, slot=%s, entering "
 974                       "operating state [D%d]\n", pdev,
 975                       pm8001_ha->name, device_state);
 976         pci_save_state(pdev);
 977         pci_disable_device(pdev);
 978         pci_set_power_state(pdev, device_state);
 979         return 0;
 980 }
 981
 982 /**
 983  * pm8001_pci_resume - power management resume main entry point
 984  * @pdev: PCI device struct
 985  *
 986  * Returns 0 success, anything else error.
 987  */
 988 static int pm8001_pci_resume(struct pci_dev *pdev)
 989 {
 990         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 991         struct pm8001_hba_info *pm8001_ha;
 992         int rc;
 993         u8 i = 0;
 994         u32 device_state;
 995         pm8001_ha = sha->lldd_ha;
 996         device_state = pdev->current_state;
 997
 998         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
 999                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1000
1001         pci_set_power_state(pdev, PCI_D0);
1002         pci_enable_wake(pdev, PCI_D0, 0);
1003         pci_restore_state(pdev);
1004         rc = pci_enable_device(pdev);
1005         if (rc) {
1006                 pm8001_printk("slot=%s Enable device failed during resume\n",
1007                               pm8001_ha->name);
1008                 goto err_out_enable;
1009         }
1010
1011         pci_set_master(pdev);
1012         rc = pci_go_44(pdev);
1013         if (rc)
1014                 goto err_out_disable;
1015
1016         /* chip soft rst only for spc */
1017         if (pm8001_ha->chip_id == chip_8001) {
1018                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1019                 PM8001_INIT_DBG(pm8001_ha,
1020                         pm8001_printk("chip soft reset successful\n"));
1021         }
1022         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1023         if (rc)
1024                 goto err_out_disable;
1025
1026         /* disable all the interrupt bits */
1027         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1028
1029         rc = pm8001_request_irq(pm8001_ha);
1030         if (rc)
1031                 goto err_out_disable;
1032 #ifdef PM8001_USE_TASKLET
1033         /* default tasklet for non msi-x interrupt handler/first msi-x
1034         * interrupt handler */
1035         tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet,
1036                         (unsigned long)pm8001_ha);
1037 #endif
1038         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1039         if (pm8001_ha->chip_id != chip_8001) {
1040                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1041                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1042         }
1043         scsi_unblock_requests(pm8001_ha->shost);
1044         return 0;
1045
1046 err_out_disable:
1047         scsi_remove_host(pm8001_ha->shost);
1048         pci_disable_device(pdev);
1049 err_out_enable:
1050         return rc;
1051 }
1052
1053 /* update of pci device, vendor id and driver data with
1054  * unique value for each of the controller
1055  */
1056 static struct pci_device_id pm8001_pci_table[] = {
1057         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1058         {
1059                 PCI_DEVICE(0x117c, 0x0042),
1060                 .driver_data = chip_8001
1061         },
1062         /* Support for SPC/SPCv/SPCve controllers */
1063         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1064         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1065         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1066         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1067         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1068         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1069         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1070         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1071         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1072         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1073         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1074         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1075         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1076         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1077         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1078         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1079                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1080         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1081                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1082         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1083                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1084         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1085                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1086         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1087                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1088         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1089                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1090         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1091                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1092         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1093                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1094         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1095                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1096         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1097                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1098         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1099                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1100         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1101                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1102         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1103                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1104         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1105                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1106         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1107                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1108         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1109                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1110         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1111                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1112         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1113                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1114         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1115                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1116         {} /* terminate list */
1117 };
1118
1119 static struct pci_driver pm8001_pci_driver = {
1120         .name           = DRV_NAME,
1121         .id_table       = pm8001_pci_table,
1122         .probe          = pm8001_pci_probe,
1123         .remove         = pm8001_pci_remove,
1124         .suspend        = pm8001_pci_suspend,
1125         .resume         = pm8001_pci_resume,
1126 };
1127
1128 /**
1129  *      pm8001_init - initialize scsi transport template
1130  */
1131 static int __init pm8001_init(void)
1132 {
1133         int rc = -ENOMEM;
1134
1135         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1136         if (!pm8001_wq)
1137                 goto err;
1138
1139         pm8001_id = 0;
1140         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1141         if (!pm8001_stt)
1142                 goto err_wq;
1143         rc = pci_register_driver(&pm8001_pci_driver);
1144         if (rc)
1145                 goto err_tp;
1146         return 0;
1147
1148 err_tp:
1149         sas_release_transport(pm8001_stt);
1150 err_wq:
1151         destroy_workqueue(pm8001_wq);
1152 err:
1153         return rc;
1154 }
1155
1156 static void __exit pm8001_exit(void)
1157 {
1158         pci_unregister_driver(&pm8001_pci_driver);
1159         sas_release_transport(pm8001_stt);
1160         destroy_workqueue(pm8001_wq);
1161 }
1162
1163 module_init(pm8001_init);
1164 module_exit(pm8001_exit);
1165
1166 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1167 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1168 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1169 MODULE_DESCRIPTION(
1170                 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1171                 "SAS/SATA controller driver");
1172 MODULE_VERSION(DRV_VERSION);
1173 MODULE_LICENSE("GPL");
1174 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1175