drivers/staging/dgnc/dgnc_cls.c

   1 /*
   2  * Copyright 2003 Digi International (www.digi.com)
   3  *      Scott H Kilau <Scott_Kilau at digi dot com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2, or (at your option)
   8  * any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  12  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  13  * PURPOSE.  See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *
  20  *      NOTE TO LINUX KERNEL HACKERS:  DO NOT REFORMAT THIS CODE!
  21  *
  22  *      This is shared code between Digi's CVS archive and the
  23  *      Linux Kernel sources.
  24  *      Changing the source just for reformatting needlessly breaks
  25  *      our CVS diff history.
  26  *
  27  *      Send any bug fixes/changes to:  Eng.Linux at digi dot com.
  28  *      Thank you.
  29  *
  30  */
  31
  32 #include <linux/kernel.h>
  33 #include <linux/sched.h>        /* For jiffies, task states */
  34 #include <linux/interrupt.h>    /* For tasklet and interrupt structs/defines */
  35 #include <linux/delay.h>        /* For udelay */
  36 #include <linux/io.h>           /* For read[bwl]/write[bwl] */
  37 #include <linux/serial.h>       /* For struct async_serial */
  38 #include <linux/serial_reg.h>   /* For the various UART offsets */
  39 #include <linux/pci.h>
  40
  41 #include "dgnc_driver.h"        /* Driver main header file */
  42 #include "dgnc_cls.h"
  43 #include "dgnc_tty.h"
  44 #include "dgnc_trace.h"
  45
  46 static inline void cls_parse_isr(struct dgnc_board *brd, uint port);
  47 static inline void cls_clear_break(struct channel_t *ch, int force);
  48 static inline void cls_set_cts_flow_control(struct channel_t *ch);
  49 static inline void cls_set_rts_flow_control(struct channel_t *ch);
  50 static inline void cls_set_ixon_flow_control(struct channel_t *ch);
  51 static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
  52 static inline void cls_set_no_output_flow_control(struct channel_t *ch);
  53 static inline void cls_set_no_input_flow_control(struct channel_t *ch);
  54 static void cls_parse_modem(struct channel_t *ch, uchar signals);
  55 static void cls_tasklet(unsigned long data);
  56 static void cls_vpd(struct dgnc_board *brd);
  57 static void cls_uart_init(struct channel_t *ch);
  58 static void cls_uart_off(struct channel_t *ch);
  59 static int cls_drain(struct tty_struct *tty, uint seconds);
  60 static void cls_param(struct tty_struct *tty);
  61 static void cls_assert_modem_signals(struct channel_t *ch);
  62 static void cls_flush_uart_write(struct channel_t *ch);
  63 static void cls_flush_uart_read(struct channel_t *ch);
  64 static void cls_disable_receiver(struct channel_t *ch);
  65 static void cls_enable_receiver(struct channel_t *ch);
  66 static void cls_send_break(struct channel_t *ch, int msecs);
  67 static void cls_send_start_character(struct channel_t *ch);
  68 static void cls_send_stop_character(struct channel_t *ch);
  69 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
  70 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
  71 static uint cls_get_uart_bytes_left(struct channel_t *ch);
  72 static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
  73 static irqreturn_t cls_intr(int irq, void *voidbrd);
  74
  75 struct board_ops dgnc_cls_ops = {
  76         .tasklet =                      cls_tasklet,
  77         .intr =                         cls_intr,
  78         .uart_init =                    cls_uart_init,
  79         .uart_off =                     cls_uart_off,
  80         .drain =                        cls_drain,
  81         .param =                        cls_param,
  82         .vpd =                          cls_vpd,
  83         .assert_modem_signals =         cls_assert_modem_signals,
  84         .flush_uart_write =             cls_flush_uart_write,
  85         .flush_uart_read =              cls_flush_uart_read,
  86         .disable_receiver =             cls_disable_receiver,
  87         .enable_receiver =              cls_enable_receiver,
  88         .send_break =                   cls_send_break,
  89         .send_start_character =         cls_send_start_character,
  90         .send_stop_character =          cls_send_stop_character,
  91         .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
  92         .get_uart_bytes_left =          cls_get_uart_bytes_left,
  93         .send_immediate_char =          cls_send_immediate_char
  94 };
  95
  96
  97 static inline void cls_set_cts_flow_control(struct channel_t *ch)
  98 {
  99         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 100         uchar ier = readb(&ch->ch_cls_uart->ier);
 101         uchar isr_fcr = 0;
 102
 103         DPR_PARAM(("Setting CTSFLOW\n"));
 104
 105         /*
 106          * The Enhanced Register Set may only be accessed when
 107          * the Line Control Register is set to 0xBFh.
 108          */
 109         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 110
 111         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 112
 113         /* Turn on CTS flow control, turn off IXON flow control */
 114         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
 115         isr_fcr &= ~(UART_EXAR654_EFR_IXON);
 116
 117         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 118
 119         /* Write old LCR value back out, which turns enhanced access off */
 120         writeb(lcrb, &ch->ch_cls_uart->lcr);
 121
 122         /* Enable interrupts for CTS flow, turn off interrupts for received XOFF chars */
 123         ier |= (UART_EXAR654_IER_CTSDSR);
 124         ier &= ~(UART_EXAR654_IER_XOFF);
 125         writeb(ier, &ch->ch_cls_uart->ier);
 126
 127         /* Set the usual FIFO values */
 128         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 129
 130         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 131                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 132                 &ch->ch_cls_uart->isr_fcr);
 133
 134         ch->ch_t_tlevel = 16;
 135
 136 }
 137
 138
 139 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
 140 {
 141         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 142         uchar ier = readb(&ch->ch_cls_uart->ier);
 143         uchar isr_fcr = 0;
 144
 145         DPR_PARAM(("Setting IXON FLOW\n"));
 146
 147         /*
 148          * The Enhanced Register Set may only be accessed when
 149          * the Line Control Register is set to 0xBFh.
 150          */
 151         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 152
 153         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 154
 155         /* Turn on IXON flow control, turn off CTS flow control */
 156         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
 157         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
 158
 159         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 160
 161         /* Now set our current start/stop chars while in enhanced mode */
 162         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 163         writeb(0, &ch->ch_cls_uart->lsr);
 164         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 165         writeb(0, &ch->ch_cls_uart->spr);
 166
 167         /* Write old LCR value back out, which turns enhanced access off */
 168         writeb(lcrb, &ch->ch_cls_uart->lcr);
 169
 170         /* Disable interrupts for CTS flow, turn on interrupts for received XOFF chars */
 171         ier &= ~(UART_EXAR654_IER_CTSDSR);
 172         ier |= (UART_EXAR654_IER_XOFF);
 173         writeb(ier, &ch->ch_cls_uart->ier);
 174
 175         /* Set the usual FIFO values */
 176         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 177
 178         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 179                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 180                 &ch->ch_cls_uart->isr_fcr);
 181
 182 }
 183
 184
 185 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
 186 {
 187         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 188         uchar ier = readb(&ch->ch_cls_uart->ier);
 189         uchar isr_fcr = 0;
 190
 191         DPR_PARAM(("Unsetting Output FLOW\n"));
 192
 193         /*
 194          * The Enhanced Register Set may only be accessed when
 195          * the Line Control Register is set to 0xBFh.
 196          */
 197         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 198
 199         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 200
 201         /* Turn off IXON flow control, turn off CTS flow control */
 202         isr_fcr |= (UART_EXAR654_EFR_ECB);
 203         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
 204
 205         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 206
 207         /* Write old LCR value back out, which turns enhanced access off */
 208         writeb(lcrb, &ch->ch_cls_uart->lcr);
 209
 210         /* Disable interrupts for CTS flow, turn off interrupts for received XOFF chars */
 211         ier &= ~(UART_EXAR654_IER_CTSDSR);
 212         ier &= ~(UART_EXAR654_IER_XOFF);
 213         writeb(ier, &ch->ch_cls_uart->ier);
 214
 215         /* Set the usual FIFO values */
 216         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 217
 218         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 219                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 220                 &ch->ch_cls_uart->isr_fcr);
 221
 222         ch->ch_r_watermark = 0;
 223         ch->ch_t_tlevel = 16;
 224         ch->ch_r_tlevel = 16;
 225
 226 }
 227
 228
 229 static inline void cls_set_rts_flow_control(struct channel_t *ch)
 230 {
 231         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 232         uchar ier = readb(&ch->ch_cls_uart->ier);
 233         uchar isr_fcr = 0;
 234
 235         DPR_PARAM(("Setting RTSFLOW\n"));
 236
 237         /*
 238          * The Enhanced Register Set may only be accessed when
 239          * the Line Control Register is set to 0xBFh.
 240          */
 241         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 242
 243         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 244
 245         /* Turn on RTS flow control, turn off IXOFF flow control */
 246         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
 247         isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
 248
 249         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 250
 251         /* Write old LCR value back out, which turns enhanced access off */
 252         writeb(lcrb, &ch->ch_cls_uart->lcr);
 253
 254         /* Enable interrupts for RTS flow */
 255         ier |= (UART_EXAR654_IER_RTSDTR);
 256         writeb(ier, &ch->ch_cls_uart->ier);
 257
 258         /* Set the usual FIFO values */
 259         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 260
 261         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 262                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 263                 &ch->ch_cls_uart->isr_fcr);
 264
 265
 266         ch->ch_r_watermark = 4;
 267         ch->ch_r_tlevel = 8;
 268
 269 }
 270
 271
 272 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
 273 {
 274         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 275         uchar ier = readb(&ch->ch_cls_uart->ier);
 276         uchar isr_fcr = 0;
 277
 278         DPR_PARAM(("Setting IXOFF FLOW\n"));
 279
 280         /*
 281          * The Enhanced Register Set may only be accessed when
 282          * the Line Control Register is set to 0xBFh.
 283          */
 284         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 285
 286         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 287
 288         /* Turn on IXOFF flow control, turn off RTS flow control */
 289         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
 290         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
 291
 292         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 293
 294         /* Now set our current start/stop chars while in enhanced mode */
 295         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 296         writeb(0, &ch->ch_cls_uart->lsr);
 297         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 298         writeb(0, &ch->ch_cls_uart->spr);
 299
 300         /* Write old LCR value back out, which turns enhanced access off */
 301         writeb(lcrb, &ch->ch_cls_uart->lcr);
 302
 303         /* Disable interrupts for RTS flow */
 304         ier &= ~(UART_EXAR654_IER_RTSDTR);
 305         writeb(ier, &ch->ch_cls_uart->ier);
 306
 307         /* Set the usual FIFO values */
 308         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 309
 310         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 311                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 312                 &ch->ch_cls_uart->isr_fcr);
 313
 314 }
 315
 316
 317 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
 318 {
 319         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 320         uchar ier = readb(&ch->ch_cls_uart->ier);
 321         uchar isr_fcr = 0;
 322
 323         DPR_PARAM(("Unsetting Input FLOW\n"));
 324
 325         /*
 326          * The Enhanced Register Set may only be accessed when
 327          * the Line Control Register is set to 0xBFh.
 328          */
 329         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 330
 331         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 332
 333         /* Turn off IXOFF flow control, turn off RTS flow control */
 334         isr_fcr |= (UART_EXAR654_EFR_ECB);
 335         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
 336
 337         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 338
 339         /* Write old LCR value back out, which turns enhanced access off */
 340         writeb(lcrb, &ch->ch_cls_uart->lcr);
 341
 342         /* Disable interrupts for RTS flow */
 343         ier &= ~(UART_EXAR654_IER_RTSDTR);
 344         writeb(ier, &ch->ch_cls_uart->ier);
 345
 346         /* Set the usual FIFO values */
 347         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 348
 349         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 350                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 351                 &ch->ch_cls_uart->isr_fcr);
 352
 353         ch->ch_t_tlevel = 16;
 354         ch->ch_r_tlevel = 16;
 355
 356 }
 357
 358
 359 /*
 360  * cls_clear_break.
 361  * Determines whether its time to shut off break condition.
 362  *
 363  * No locks are assumed to be held when calling this function.
 364  * channel lock is held and released in this function.
 365  */
 366 static inline void cls_clear_break(struct channel_t *ch, int force)
 367 {
 368         ulong lock_flags;
 369
 370         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 371                 return;
 372
 373         DGNC_LOCK(ch->ch_lock, lock_flags);
 374
 375         /* Bail if we aren't currently sending a break. */
 376         if (!ch->ch_stop_sending_break) {
 377                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
 378                 return;
 379         }
 380
 381         /* Turn break off, and unset some variables */
 382         if (ch->ch_flags & CH_BREAK_SENDING) {
 383                 if ((jiffies >= ch->ch_stop_sending_break) || force) {
 384                         uchar temp = readb(&ch->ch_cls_uart->lcr);
 385                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
 386                         ch->ch_flags &= ~(CH_BREAK_SENDING);
 387                         ch->ch_stop_sending_break = 0;
 388                         DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
 389                 }
 390         }
 391         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 392 }
 393
 394
 395 /* Parse the ISR register for the specific port */
 396 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
 397 {
 398         struct channel_t *ch;
 399         uchar isr = 0;
 400         ulong lock_flags;
 401
 402         /*
 403          * No need to verify board pointer, it was already
 404          * verified in the interrupt routine.
 405          */
 406
 407         if (port > brd->nasync)
 408                 return;
 409
 410         ch = brd->channels[port];
 411         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 412                 return;
 413
 414         /* Here we try to figure out what caused the interrupt to happen */
 415         while (1) {
 416
 417                 isr = readb(&ch->ch_cls_uart->isr_fcr);
 418
 419                 /* Bail if no pending interrupt on port */
 420                 if (isr & UART_IIR_NO_INT)
 421                         break;
 422
 423                 DPR_INTR(("%s:%d port: %x isr: %x\n", __FILE__, __LINE__, port, isr));
 424
 425                 /* Receive Interrupt pending */
 426                 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
 427                         /* Read data from uart -> queue */
 428                         brd->intr_rx++;
 429                         ch->ch_intr_rx++;
 430                         cls_copy_data_from_uart_to_queue(ch);
 431                         dgnc_check_queue_flow_control(ch);
 432                 }
 433
 434                 /* Transmit Hold register empty pending */
 435                 if (isr & UART_IIR_THRI) {
 436                         /* Transfer data (if any) from Write Queue -> UART. */
 437                         DGNC_LOCK(ch->ch_lock, lock_flags);
 438                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 439                         brd->intr_tx++;
 440                         ch->ch_intr_tx++;
 441                         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 442                         cls_copy_data_from_queue_to_uart(ch);
 443                 }
 444
 445                 /* Received Xoff signal/Special character */
 446                 if (isr & UART_IIR_XOFF)
 447                         /* Empty */
 448
 449                 /* CTS/RTS change of state */
 450                 if (isr & UART_IIR_CTSRTS) {
 451                         brd->intr_modem++;
 452                         ch->ch_intr_modem++;
 453                         /*
 454                          * Don't need to do anything, the cls_parse_modem
 455                          * below will grab the updated modem signals.
 456                          */
 457                 }
 458
 459                 /* Parse any modem signal changes */
 460                 DPR_INTR(("MOD_STAT: sending to parse_modem_sigs\n"));
 461                 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 462         }
 463 }
 464
 465
 466 /*
 467  * cls_param()
 468  * Send any/all changes to the line to the UART.
 469  */
 470 static void cls_param(struct tty_struct *tty)
 471 {
 472         uchar lcr = 0;
 473         uchar uart_lcr = 0;
 474         uchar ier = 0;
 475         uchar uart_ier = 0;
 476         uint baud = 9600;
 477         int quot = 0;
 478         struct dgnc_board *bd;
 479         struct channel_t *ch;
 480         struct un_t   *un;
 481
 482         if (!tty || tty->magic != TTY_MAGIC)
 483                 return;
 484
 485         un = (struct un_t *) tty->driver_data;
 486         if (!un || un->magic != DGNC_UNIT_MAGIC)
 487                 return;
 488
 489         ch = un->un_ch;
 490         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 491                 return;
 492
 493         bd = ch->ch_bd;
 494         if (!bd || bd->magic != DGNC_BOARD_MAGIC)
 495                 return;
 496
 497         DPR_PARAM(("param start: tdev: %x cflags: %x oflags: %x iflags: %x\n",
 498                 ch->ch_tun.un_dev, ch->ch_c_cflag, ch->ch_c_oflag, ch->ch_c_iflag));
 499
 500         /*
 501          * If baud rate is zero, flush queues, and set mval to drop DTR.
 502          */
 503         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
 504                 ch->ch_r_head = ch->ch_r_tail = 0;
 505                 ch->ch_e_head = ch->ch_e_tail = 0;
 506                 ch->ch_w_head = ch->ch_w_tail = 0;
 507
 508                 cls_flush_uart_write(ch);
 509                 cls_flush_uart_read(ch);
 510
 511                 /* The baudrate is B0 so all modem lines are to be dropped. */
 512                 ch->ch_flags |= (CH_BAUD0);
 513                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
 514                 cls_assert_modem_signals(ch);
 515                 ch->ch_old_baud = 0;
 516                 return;
 517         } else if (ch->ch_custom_speed) {
 518
 519                 baud = ch->ch_custom_speed;
 520                 /* Handle transition from B0 */
 521                 if (ch->ch_flags & CH_BAUD0) {
 522                         ch->ch_flags &= ~(CH_BAUD0);
 523
 524                         /*
 525                          * Bring back up RTS and DTR...
 526                          * Also handle RTS or DTR toggle if set.
 527                          */
 528                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 529                                 ch->ch_mostat |= (UART_MCR_RTS);
 530                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 531                                 ch->ch_mostat |= (UART_MCR_DTR);
 532                 }
 533
 534         } else {
 535                 int iindex = 0;
 536                 int jindex = 0;
 537
 538                 ulong bauds[4][16] = {
 539                         { /* slowbaud */
 540                                 0,      50,     75,     110,
 541                                 134,    150,    200,    300,
 542                                 600,    1200,   1800,   2400,
 543                                 4800,   9600,   19200,  38400 },
 544                         { /* slowbaud & CBAUDEX */
 545                                 0,      57600,  115200, 230400,
 546                                 460800, 150,    200,    921600,
 547                                 600,    1200,   1800,   2400,
 548                                 4800,   9600,   19200,  38400 },
 549                         { /* fastbaud */
 550                                 0,      57600,   76800, 115200,
 551                                 131657, 153600, 230400, 460800,
 552                                 921600, 1200,   1800,   2400,
 553                                 4800,   9600,   19200,  38400 },
 554                         { /* fastbaud & CBAUDEX */
 555                                 0,      57600,  115200, 230400,
 556                                 460800, 150,    200,    921600,
 557                                 600,    1200,   1800,   2400,
 558                                 4800,   9600,   19200,  38400 }
 559                 };
 560
 561                 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
 562                 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
 563                         baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
 564                 else
 565                         baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
 566
 567                 if (ch->ch_c_cflag & CBAUDEX)
 568                         iindex = 1;
 569
 570                 if (ch->ch_digi.digi_flags & DIGI_FAST)
 571                         iindex += 2;
 572
 573                 jindex = baud;
 574
 575                 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) {
 576                         baud = bauds[iindex][jindex];
 577                 } else {
 578                         DPR_IOCTL(("baud indices were out of range (%d)(%d)",
 579                                 iindex, jindex));
 580                         baud = 0;
 581                 }
 582
 583                 if (baud == 0)
 584                         baud = 9600;
 585
 586                 /* Handle transition from B0 */
 587                 if (ch->ch_flags & CH_BAUD0) {
 588                         ch->ch_flags &= ~(CH_BAUD0);
 589
 590                         /*
 591                          * Bring back up RTS and DTR...
 592                          * Also handle RTS or DTR toggle if set.
 593                          */
 594                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 595                                 ch->ch_mostat |= (UART_MCR_RTS);
 596                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 597                                 ch->ch_mostat |= (UART_MCR_DTR);
 598                 }
 599         }
 600
 601         if (ch->ch_c_cflag & PARENB) {
 602                 lcr |= UART_LCR_PARITY;
 603         }
 604
 605         if (!(ch->ch_c_cflag & PARODD)) {
 606                 lcr |= UART_LCR_EPAR;
 607         }
 608
 609         /*
 610          * Not all platforms support mark/space parity,
 611          * so this will hide behind an ifdef.
 612          */
 613 #ifdef CMSPAR
 614         if (ch->ch_c_cflag & CMSPAR)
 615                 lcr |= UART_LCR_SPAR;
 616 #endif
 617
 618         if (ch->ch_c_cflag & CSTOPB)
 619                 lcr |= UART_LCR_STOP;
 620
 621         switch (ch->ch_c_cflag & CSIZE) {
 622         case CS5:
 623                 lcr |= UART_LCR_WLEN5;
 624                 break;
 625         case CS6:
 626                 lcr |= UART_LCR_WLEN6;
 627                 break;
 628         case CS7:
 629                 lcr |= UART_LCR_WLEN7;
 630                 break;
 631         case CS8:
 632         default:
 633                 lcr |= UART_LCR_WLEN8;
 634                 break;
 635         }
 636
 637         ier = uart_ier = readb(&ch->ch_cls_uart->ier);
 638         uart_lcr = readb(&ch->ch_cls_uart->lcr);
 639
 640         if (baud == 0)
 641                 baud = 9600;
 642
 643         quot = ch->ch_bd->bd_dividend / baud;
 644
 645         if (quot != 0 && ch->ch_old_baud != baud) {
 646                 ch->ch_old_baud = baud;
 647                 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
 648                 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
 649                 writeb((quot >> 8), &ch->ch_cls_uart->ier);
 650                 writeb(lcr, &ch->ch_cls_uart->lcr);
 651         }
 652
 653         if (uart_lcr != lcr)
 654                 writeb(lcr, &ch->ch_cls_uart->lcr);
 655
 656         if (ch->ch_c_cflag & CREAD) {
 657                 ier |= (UART_IER_RDI | UART_IER_RLSI);
 658         }
 659         else {
 660                 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
 661         }
 662
 663         /*
 664          * Have the UART interrupt on modem signal changes ONLY when
 665          * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
 666          */
 667         if ((ch->ch_digi.digi_flags & CTSPACE) || (ch->ch_digi.digi_flags & RTSPACE) ||
 668                 (ch->ch_c_cflag & CRTSCTS) || !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
 669                 !(ch->ch_c_cflag & CLOCAL))
 670         {
 671                 ier |= UART_IER_MSI;
 672         }
 673         else {
 674                 ier &= ~UART_IER_MSI;
 675         }
 676
 677         ier |= UART_IER_THRI;
 678
 679         if (ier != uart_ier)
 680                 writeb(ier, &ch->ch_cls_uart->ier);
 681
 682         if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
 683                 cls_set_cts_flow_control(ch);
 684         }
 685         else if (ch->ch_c_iflag & IXON) {
 686                 /* If start/stop is set to disable, then we should disable flow control */
 687                 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
 688                         cls_set_no_output_flow_control(ch);
 689                 else
 690                         cls_set_ixon_flow_control(ch);
 691         }
 692         else {
 693                 cls_set_no_output_flow_control(ch);
 694         }
 695
 696         if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
 697                 cls_set_rts_flow_control(ch);
 698         }
 699         else if (ch->ch_c_iflag & IXOFF) {
 700                 /* If start/stop is set to disable, then we should disable flow control */
 701                 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
 702                         cls_set_no_input_flow_control(ch);
 703                 else
 704                         cls_set_ixoff_flow_control(ch);
 705         }
 706         else {
 707                 cls_set_no_input_flow_control(ch);
 708         }
 709
 710         cls_assert_modem_signals(ch);
 711
 712         /* Get current status of the modem signals now */
 713         cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 714 }
 715
 716
 717 /*
 718  * Our board poller function.
 719  */
 720 static void cls_tasklet(unsigned long data)
 721 {
 722         struct dgnc_board *bd = (struct dgnc_board *) data;
 723         struct channel_t *ch;
 724         ulong  lock_flags;
 725         int i;
 726         int state = 0;
 727         int ports = 0;
 728
 729         if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
 730                 APR(("poll_tasklet() - NULL or bad bd.\n"));
 731                 return;
 732         }
 733
 734         /* Cache a couple board values */
 735         DGNC_LOCK(bd->bd_lock, lock_flags);
 736         state = bd->state;
 737         ports = bd->nasync;
 738         DGNC_UNLOCK(bd->bd_lock, lock_flags);
 739
 740         /*
 741          * Do NOT allow the interrupt routine to read the intr registers
 742          * Until we release this lock.
 743          */
 744         DGNC_LOCK(bd->bd_intr_lock, lock_flags);
 745
 746         /*
 747          * If board is ready, parse deeper to see if there is anything to do.
 748          */
 749         if ((state == BOARD_READY) && (ports > 0)) {
 750
 751                 /* Loop on each port */
 752                 for (i = 0; i < ports; i++) {
 753                         ch = bd->channels[i];
 754                         if (!ch)
 755                                 continue;
 756
 757                         /*
 758                          * NOTE: Remember you CANNOT hold any channel
 759                          * locks when calling input.
 760                          * During input processing, its possible we
 761                          * will call ld, which might do callbacks back
 762                          * into us.
 763                          */
 764                         dgnc_input(ch);
 765
 766                         /*
 767                          * Channel lock is grabbed and then released
 768                          * inside this routine.
 769                          */
 770                         cls_copy_data_from_queue_to_uart(ch);
 771                         dgnc_wakeup_writes(ch);
 772
 773                         /*
 774                          * Check carrier function.
 775                          */
 776                         dgnc_carrier(ch);
 777
 778                         /*
 779                          * The timing check of turning off the break is done
 780                          * inside clear_break()
 781                          */
 782                         if (ch->ch_stop_sending_break)
 783                                 cls_clear_break(ch, 0);
 784                 }
 785         }
 786
 787         DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
 788
 789 }
 790
 791
 792 /*
 793  * cls_intr()
 794  *
 795  * Classic specific interrupt handler.
 796  */
 797 static irqreturn_t cls_intr(int irq, void *voidbrd)
 798 {
 799         struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
 800         uint i = 0;
 801         uchar poll_reg;
 802         unsigned long lock_flags;
 803
 804         if (!brd) {
 805                 APR(("Received interrupt (%d) with null board associated\n", irq));
 806                 return IRQ_NONE;
 807         }
 808
 809         /*
 810          * Check to make sure its for us.
 811          */
 812         if (brd->magic != DGNC_BOARD_MAGIC) {
 813                 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n", irq));
 814                 return IRQ_NONE;
 815         }
 816
 817         DGNC_LOCK(brd->bd_intr_lock, lock_flags);
 818
 819         brd->intr_count++;
 820
 821         /*
 822          * Check the board's global interrupt offset to see if we
 823          * we actually do have an interrupt pending for us.
 824          */
 825         poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
 826
 827         /* If 0, no interrupts pending */
 828         if (!poll_reg) {
 829                 DPR_INTR(("Kernel interrupted to me, but no pending interrupts...\n"));
 830                 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
 831                 return IRQ_NONE;
 832         }
 833
 834         DPR_INTR(("%s:%d poll_reg: %x\n", __FILE__, __LINE__, poll_reg));
 835
 836         /* Parse each port to find out what caused the interrupt */
 837         for (i = 0; i < brd->nasync; i++) {
 838                 cls_parse_isr(brd, i);
 839         }
 840
 841         /*
 842          * Schedule tasklet to more in-depth servicing at a better time.
 843          */
 844         tasklet_schedule(&brd->helper_tasklet);
 845
 846         DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
 847
 848         DPR_INTR(("dgnc_intr finish.\n"));
 849         return IRQ_HANDLED;
 850 }
 851
 852
 853 static void cls_disable_receiver(struct channel_t *ch)
 854 {
 855         uchar tmp = readb(&ch->ch_cls_uart->ier);
 856         tmp &= ~(UART_IER_RDI);
 857         writeb(tmp, &ch->ch_cls_uart->ier);
 858 }
 859
 860
 861 static void cls_enable_receiver(struct channel_t *ch)
 862 {
 863         uchar tmp = readb(&ch->ch_cls_uart->ier);
 864         tmp |= (UART_IER_RDI);
 865         writeb(tmp, &ch->ch_cls_uart->ier);
 866 }
 867
 868
 869 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
 870 {
 871         int qleft = 0;
 872         uchar linestatus = 0;
 873         uchar error_mask = 0;
 874         ushort head;
 875         ushort tail;
 876         ulong lock_flags;
 877
 878         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 879                 return;
 880
 881         DGNC_LOCK(ch->ch_lock, lock_flags);
 882
 883         /* cache head and tail of queue */
 884         head = ch->ch_r_head;
 885         tail = ch->ch_r_tail;
 886
 887         /* Store how much space we have left in the queue */
 888         if ((qleft = tail - head - 1) < 0)
 889                 qleft += RQUEUEMASK + 1;
 890
 891         /*
 892          * Create a mask to determine whether we should
 893          * insert the character (if any) into our queue.
 894          */
 895         if (ch->ch_c_iflag & IGNBRK)
 896                 error_mask |= UART_LSR_BI;
 897
 898         while (1) {
 899                 linestatus = readb(&ch->ch_cls_uart->lsr);
 900
 901                 if (!(linestatus & (UART_LSR_DR)))
 902                         break;
 903
 904                 /*
 905                  * Discard character if we are ignoring the error mask.
 906                 */
 907                 if (linestatus & error_mask)  {
 908                         uchar discard;
 909                         linestatus = 0;
 910                         discard = readb(&ch->ch_cls_uart->txrx);
 911                         continue;
 912                 }
 913
 914                 /*
 915                  * If our queue is full, we have no choice but to drop some data.
 916                  * The assumption is that HWFLOW or SWFLOW should have stopped
 917                  * things way way before we got to this point.
 918                  *
 919                  * I decided that I wanted to ditch the oldest data first,
 920                  * I hope thats okay with everyone? Yes? Good.
 921                  */
 922                 while (qleft < 1) {
 923                         DPR_READ(("Queue full, dropping DATA:%x LSR:%x\n",
 924                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]));
 925
 926                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
 927                         ch->ch_err_overrun++;
 928                         qleft++;
 929                 }
 930
 931                 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE | UART_LSR_FE);
 932                 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
 933                 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, 1);
 934
 935                 qleft--;
 936
 937                 DPR_READ(("DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]));
 938
 939                 if (ch->ch_equeue[head] & UART_LSR_PE)
 940                         ch->ch_err_parity++;
 941                 if (ch->ch_equeue[head] & UART_LSR_BI)
 942                         ch->ch_err_break++;
 943                 if (ch->ch_equeue[head] & UART_LSR_FE)
 944                         ch->ch_err_frame++;
 945
 946                 /* Add to, and flip head if needed */
 947                 head = (head + 1) & RQUEUEMASK;
 948                 ch->ch_rxcount++;
 949         }
 950
 951         /*
 952          * Write new final heads to channel structure.
 953          */
 954         ch->ch_r_head = head & RQUEUEMASK;
 955         ch->ch_e_head = head & EQUEUEMASK;
 956
 957         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 958 }
 959
 960
 961 /*
 962  * This function basically goes to sleep for secs, or until
 963  * it gets signalled that the port has fully drained.
 964  */
 965 static int cls_drain(struct tty_struct *tty, uint seconds)
 966 {
 967         ulong lock_flags;
 968         struct channel_t *ch;
 969         struct un_t *un;
 970         int rc = 0;
 971
 972         if (!tty || tty->magic != TTY_MAGIC) {
 973                 return -ENXIO;
 974         }
 975
 976         un = (struct un_t *) tty->driver_data;
 977         if (!un || un->magic != DGNC_UNIT_MAGIC) {
 978                 return -ENXIO;
 979         }
 980
 981         ch = un->un_ch;
 982         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
 983                 return -ENXIO;
 984         }
 985
 986         DGNC_LOCK(ch->ch_lock, lock_flags);
 987         un->un_flags |= UN_EMPTY;
 988         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 989
 990         /*
 991          * NOTE: Do something with time passed in.
 992          */
 993         rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
 994
 995         /* If ret is non-zero, user ctrl-c'ed us */
 996         if (rc)
 997                 DPR_IOCTL(("%d Drain - User ctrl c'ed\n", __LINE__));
 998
 999         return rc;
1000 }
1001
1002
1003 /* Channel lock MUST be held before calling this function! */
1004 static void cls_flush_uart_write(struct channel_t *ch)
1005 {
1006         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1007                 return;
1008         }
1009
1010         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_cls_uart->isr_fcr);
1011         udelay(10);
1012
1013         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1014 }
1015
1016
1017 /* Channel lock MUST be held before calling this function! */
1018 static void cls_flush_uart_read(struct channel_t *ch)
1019 {
1020         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1021                 return;
1022         }
1023
1024         /*
1025          * For complete POSIX compatibility, we should be purging the
1026          * read FIFO in the UART here.
1027          *
1028          * However, doing the statement below also incorrectly flushes
1029          * write data as well as just basically trashing the FIFO.
1030          *
1031          * I believe this is a BUG in this UART.
1032          * So for now, we will leave the code #ifdef'ed out...
1033          */
1034 #if 0
1035         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_cls_uart->isr_fcr);
1036 #endif
1037         udelay(10);
1038 }
1039
1040
1041 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
1042 {
1043         ushort head;
1044         ushort tail;
1045         int n;
1046         int qlen;
1047         uint len_written = 0;
1048         ulong lock_flags;
1049
1050         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1051                 return;
1052
1053         DGNC_LOCK(ch->ch_lock, lock_flags);
1054
1055         /* No data to write to the UART */
1056         if (ch->ch_w_tail == ch->ch_w_head) {
1057                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1058                 return;
1059         }
1060
1061         /* If port is "stopped", don't send any data to the UART */
1062         if ((ch->ch_flags & CH_FORCED_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) {
1063                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1064                 return;
1065         }
1066
1067         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1068                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1069                 return;
1070         }
1071
1072         n = 32;
1073
1074         /* cache head and tail of queue */
1075         head = ch->ch_w_head & WQUEUEMASK;
1076         tail = ch->ch_w_tail & WQUEUEMASK;
1077         qlen = (head - tail) & WQUEUEMASK;
1078
1079         /* Find minimum of the FIFO space, versus queue length */
1080         n = min(n, qlen);
1081
1082         while (n > 0) {
1083
1084                 /*
1085                  * If RTS Toggle mode is on, turn on RTS now if not already set,
1086                  * and make sure we get an event when the data transfer has completed.
1087                  */
1088                 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1089                         if (!(ch->ch_mostat & UART_MCR_RTS)) {
1090                                 ch->ch_mostat |= (UART_MCR_RTS);
1091                                 cls_assert_modem_signals(ch);
1092                         }
1093                         ch->ch_tun.un_flags |= (UN_EMPTY);
1094                 }
1095
1096                 /*
1097                  * If DTR Toggle mode is on, turn on DTR now if not already set,
1098                  * and make sure we get an event when the data transfer has completed.
1099                  */
1100                 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1101                         if (!(ch->ch_mostat & UART_MCR_DTR)) {
1102                                 ch->ch_mostat |= (UART_MCR_DTR);
1103                                 cls_assert_modem_signals(ch);
1104                         }
1105                         ch->ch_tun.un_flags |= (UN_EMPTY);
1106                 }
1107                 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
1108                 dgnc_sniff_nowait_nolock(ch, "UART WRITE", ch->ch_wqueue + ch->ch_w_tail, 1);
1109                 DPR_WRITE(("Tx data: %x\n", ch->ch_wqueue[ch->ch_w_tail]));
1110                 ch->ch_w_tail++;
1111                 ch->ch_w_tail &= WQUEUEMASK;
1112                 ch->ch_txcount++;
1113                 len_written++;
1114                 n--;
1115         }
1116
1117         if (len_written > 0)
1118                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1119
1120         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1121
1122         return;
1123 }
1124
1125
1126 static void cls_parse_modem(struct channel_t *ch, uchar signals)
1127 {
1128         volatile uchar msignals = signals;
1129
1130         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1131                 return;
1132
1133         DPR_MSIGS(("cls_parse_modem: port: %d signals: %d\n", ch->ch_portnum, msignals));
1134
1135         /*
1136          * Do altpin switching. Altpin switches DCD and DSR.
1137          * This prolly breaks DSRPACE, so we should be more clever here.
1138          */
1139         if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1140                 uchar mswap = signals;
1141                 if (mswap & UART_MSR_DDCD) {
1142                         msignals &= ~UART_MSR_DDCD;
1143                         msignals |= UART_MSR_DDSR;
1144                 }
1145                 if (mswap & UART_MSR_DDSR) {
1146                         msignals &= ~UART_MSR_DDSR;
1147                         msignals |= UART_MSR_DDCD;
1148                 }
1149                 if (mswap & UART_MSR_DCD) {
1150                         msignals &= ~UART_MSR_DCD;
1151                         msignals |= UART_MSR_DSR;
1152                 }
1153                 if (mswap & UART_MSR_DSR) {
1154                         msignals &= ~UART_MSR_DSR;
1155                         msignals |= UART_MSR_DCD;
1156                 }
1157         }
1158
1159         /* Scrub off lower bits. They signify delta's, which I don't care about */
1160         signals &= 0xf0;
1161
1162         if (msignals & UART_MSR_DCD)
1163                 ch->ch_mistat |= UART_MSR_DCD;
1164         else
1165                 ch->ch_mistat &= ~UART_MSR_DCD;
1166
1167         if (msignals & UART_MSR_DSR)
1168                 ch->ch_mistat |= UART_MSR_DSR;
1169         else
1170                 ch->ch_mistat &= ~UART_MSR_DSR;
1171
1172         if (msignals & UART_MSR_RI)
1173                 ch->ch_mistat |= UART_MSR_RI;
1174         else
1175                 ch->ch_mistat &= ~UART_MSR_RI;
1176
1177         if (msignals & UART_MSR_CTS)
1178                 ch->ch_mistat |= UART_MSR_CTS;
1179         else
1180                 ch->ch_mistat &= ~UART_MSR_CTS;
1181
1182
1183         DPR_MSIGS(("Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
1184                 ch->ch_portnum,
1185                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
1186                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
1187                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
1188                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
1189                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
1190                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
1191 }
1192
1193
1194 /* Make the UART raise any of the output signals we want up */
1195 static void cls_assert_modem_signals(struct channel_t *ch)
1196 {
1197         uchar out;
1198
1199         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1200                 return;
1201
1202         out = ch->ch_mostat;
1203
1204         if (ch->ch_flags & CH_LOOPBACK)
1205                 out |= UART_MCR_LOOP;
1206
1207         writeb(out, &ch->ch_cls_uart->mcr);
1208
1209         /* Give time for the UART to actually drop the signals */
1210         udelay(10);
1211 }
1212
1213
1214 static void cls_send_start_character(struct channel_t *ch)
1215 {
1216         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1217                 return;
1218
1219         if (ch->ch_startc != _POSIX_VDISABLE) {
1220                 ch->ch_xon_sends++;
1221                 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1222         }
1223 }
1224
1225
1226 static void cls_send_stop_character(struct channel_t *ch)
1227 {
1228         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1229                 return;
1230
1231         if (ch->ch_stopc != _POSIX_VDISABLE) {
1232                 ch->ch_xoff_sends++;
1233                 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1234         }
1235 }
1236
1237
1238 /* Inits UART */
1239 static void cls_uart_init(struct channel_t *ch)
1240 {
1241         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
1242         uchar isr_fcr = 0;
1243
1244         writeb(0, &ch->ch_cls_uart->ier);
1245
1246         /*
1247          * The Enhanced Register Set may only be accessed when
1248          * the Line Control Register is set to 0xBFh.
1249          */
1250         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1251
1252         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1253
1254         /* Turn on Enhanced/Extended controls */
1255         isr_fcr |= (UART_EXAR654_EFR_ECB);
1256
1257         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1258
1259         /* Write old LCR value back out, which turns enhanced access off */
1260         writeb(lcrb, &ch->ch_cls_uart->lcr);
1261
1262         /* Clear out UART and FIFO */
1263         readb(&ch->ch_cls_uart->txrx);
1264
1265         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_cls_uart->isr_fcr);
1266         udelay(10);
1267
1268         ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1269
1270         readb(&ch->ch_cls_uart->lsr);
1271         readb(&ch->ch_cls_uart->msr);
1272 }
1273
1274
1275 /*
1276  * Turns off UART.
1277  */
1278 static void cls_uart_off(struct channel_t *ch)
1279 {
1280         writeb(0, &ch->ch_cls_uart->ier);
1281 }
1282
1283
1284 /*
1285  * cls_get_uarts_bytes_left.
1286  * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1287  *
1288  * The channel lock MUST be held by the calling function.
1289  */
1290 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1291 {
1292         uchar left = 0;
1293         uchar lsr = 0;
1294
1295         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1296                 return 0;
1297
1298         lsr = readb(&ch->ch_cls_uart->lsr);
1299
1300         /* Determine whether the Transmitter is empty or not */
1301         if (!(lsr & UART_LSR_TEMT)) {
1302                 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1303                         tasklet_schedule(&ch->ch_bd->helper_tasklet);
1304                 left = 1;
1305         }
1306         else {
1307                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1308                 left = 0;
1309         }
1310
1311         return left;
1312 }
1313
1314
1315 /*
1316  * cls_send_break.
1317  * Starts sending a break thru the UART.
1318  *
1319  * The channel lock MUST be held by the calling function.
1320  */
1321 static void cls_send_break(struct channel_t *ch, int msecs)
1322 {
1323         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1324                 return;
1325
1326         /*
1327          * If we receive a time of 0, this means turn off the break.
1328          */
1329         if (msecs == 0) {
1330                 /* Turn break off, and unset some variables */
1331                 if (ch->ch_flags & CH_BREAK_SENDING) {
1332                         uchar temp = readb(&ch->ch_cls_uart->lcr);
1333                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1334                         ch->ch_flags &= ~(CH_BREAK_SENDING);
1335                         ch->ch_stop_sending_break = 0;
1336                         DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
1337                 }
1338                 return;
1339         }
1340
1341         /*
1342          * Set the time we should stop sending the break.
1343          * If we are already sending a break, toss away the existing
1344          * time to stop, and use this new value instead.
1345          */
1346         ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1347
1348         /* Tell the UART to start sending the break */
1349         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1350                 uchar temp = readb(&ch->ch_cls_uart->lcr);
1351                 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1352                 ch->ch_flags |= (CH_BREAK_SENDING);
1353                 DPR_IOCTL(("Port %d. Starting UART_LCR_SBC! start: %lx should end: %lx\n",
1354                         ch->ch_portnum, jiffies, ch->ch_stop_sending_break));
1355         }
1356 }
1357
1358
1359 /*
1360  * cls_send_immediate_char.
1361  * Sends a specific character as soon as possible to the UART,
1362  * jumping over any bytes that might be in the write queue.
1363  *
1364  * The channel lock MUST be held by the calling function.
1365  */
1366 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1367 {
1368         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1369                 return;
1370
1371         writeb(c, &ch->ch_cls_uart->txrx);
1372 }
1373
1374 static void cls_vpd(struct dgnc_board *brd)
1375 {
1376         ulong           vpdbase;        /* Start of io base of the card */
1377         u8 __iomem           *re_map_vpdbase;/* Remapped memory of the card */
1378         int i = 0;
1379
1380
1381         vpdbase = pci_resource_start(brd->pdev, 3);
1382
1383         /* No VPD */
1384         if (!vpdbase)
1385                 return;
1386
1387         re_map_vpdbase = ioremap(vpdbase, 0x400);
1388
1389         if (!re_map_vpdbase)
1390                 return;
1391
1392         /* Store the VPD into our buffer */
1393         for (i = 0; i < 0x40; i++) {
1394                 brd->vpd[i] = readb(re_map_vpdbase + i);
1395                 printk("%x ", brd->vpd[i]);
1396         }
1397         printk("\n");
1398
1399         if (re_map_vpdbase)
1400                 iounmap(re_map_vpdbase);
1401 }
1402