drivers/staging/dwc2/hcd_intr.c

   1 /*
   2  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the interrupt handlers for Host mode
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/io.h>
  46 #include <linux/slab.h>
  47 #include <linux/usb.h>
  48
  49 #include <linux/usb/hcd.h>
  50 #include <linux/usb/ch11.h>
  51
  52 #include "core.h"
  53 #include "hcd.h"
  54
  55 /* This function is for debug only */
  56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57 {
  58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  59         u16 curr_frame_number = hsotg->frame_number;
  60
  61         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  62                 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
  63                     curr_frame_number) {
  64                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  65                                         curr_frame_number;
  66                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  67                                         hsotg->last_frame_num;
  68                         hsotg->frame_num_idx++;
  69                 }
  70         } else if (!hsotg->dumped_frame_num_array) {
  71                 int i;
  72
  73                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  74                 dev_info(hsotg->dev, "-----     ----------\n");
  75                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  76                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  77                                  hsotg->frame_num_array[i],
  78                                  hsotg->last_frame_num_array[i]);
  79                 }
  80                 hsotg->dumped_frame_num_array = 1;
  81         }
  82         hsotg->last_frame_num = curr_frame_number;
  83 #endif
  84 }
  85
  86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  87                                     struct dwc2_host_chan *chan,
  88                                     struct dwc2_qtd *qtd)
  89 {
  90         struct urb *usb_urb;
  91
  92         if (!chan->qh)
  93                 return;
  94
  95         if (chan->qh->dev_speed == USB_SPEED_HIGH)
  96                 return;
  97
  98         if (!qtd->urb)
  99                 return;
 100
 101         usb_urb = qtd->urb->priv;
 102         if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
 103                 return;
 104
 105         if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 106                 chan->qh->tt_buffer_dirty = 1;
 107                 if (usb_hub_clear_tt_buffer(usb_urb))
 108                         /* Clear failed; let's hope things work anyway */
 109                         chan->qh->tt_buffer_dirty = 0;
 110         }
 111 }
 112
 113 /*
 114  * Handles the start-of-frame interrupt in host mode. Non-periodic
 115  * transactions may be queued to the DWC_otg controller for the current
 116  * (micro)frame. Periodic transactions may be queued to the controller
 117  * for the next (micro)frame.
 118  */
 119 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 120 {
 121         struct list_head *qh_entry;
 122         struct dwc2_qh *qh;
 123         enum dwc2_transaction_type tr_type;
 124
 125 #ifdef DEBUG_SOF
 126         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 127 #endif
 128
 129         hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 130
 131         dwc2_track_missed_sofs(hsotg);
 132
 133         /* Determine whether any periodic QHs should be executed */
 134         qh_entry = hsotg->periodic_sched_inactive.next;
 135         while (qh_entry != &hsotg->periodic_sched_inactive) {
 136                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 137                 qh_entry = qh_entry->next;
 138                 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
 139                         /*
 140                          * Move QH to the ready list to be executed next
 141                          * (micro)frame
 142                          */
 143                         list_move(&qh->qh_list_entry,
 144                                   &hsotg->periodic_sched_ready);
 145         }
 146         tr_type = dwc2_hcd_select_transactions(hsotg);
 147         if (tr_type != DWC2_TRANSACTION_NONE)
 148                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 149
 150         /* Clear interrupt */
 151         writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 152 }
 153
 154 /*
 155  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 156  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 157  * memory if the DWC_otg controller is operating in Slave mode.
 158  */
 159 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 160 {
 161         u32 grxsts, chnum, bcnt, dpid, pktsts;
 162         struct dwc2_host_chan *chan;
 163
 164         if (dbg_perio())
 165                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 166
 167         grxsts = readl(hsotg->regs + GRXSTSP);
 168         chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
 169         chan = hsotg->hc_ptr_array[chnum];
 170         if (!chan) {
 171                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 172                 return;
 173         }
 174
 175         bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
 176         dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
 177         pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
 178
 179         /* Packet Status */
 180         if (dbg_perio()) {
 181                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 182                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 183                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 184                          chan->data_pid_start);
 185                 dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);
 186         }
 187
 188         switch (pktsts) {
 189         case GRXSTS_PKTSTS_HCHIN:
 190                 /* Read the data into the host buffer */
 191                 if (bcnt > 0) {
 192                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 193
 194                         /* Update the HC fields for the next packet received */
 195                         chan->xfer_count += bcnt;
 196                         chan->xfer_buf += bcnt;
 197                 }
 198                 break;
 199         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 200         case GRXSTS_PKTSTS_DATATOGGLEERR:
 201         case GRXSTS_PKTSTS_HCHHALTED:
 202                 /* Handled in interrupt, just ignore data */
 203                 break;
 204         default:
 205                 dev_err(hsotg->dev,
 206                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 207                 break;
 208         }
 209 }
 210
 211 /*
 212  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 213  * data packets may be written to the FIFO for OUT transfers. More requests
 214  * may be written to the non-periodic request queue for IN transfers. This
 215  * interrupt is enabled only in Slave mode.
 216  */
 217 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 218 {
 219         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 220         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 221 }
 222
 223 /*
 224  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 225  * packets may be written to the FIFO for OUT transfers. More requests may be
 226  * written to the periodic request queue for IN transfers. This interrupt is
 227  * enabled only in Slave mode.
 228  */
 229 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 230 {
 231         if (dbg_perio())
 232                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 233         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 234 }
 235
 236 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 237                               u32 *hprt0_modify)
 238 {
 239         struct dwc2_core_params *params = hsotg->core_params;
 240         int do_reset = 0;
 241         u32 usbcfg;
 242         u32 prtspd;
 243         u32 hcfg;
 244         u32 fslspclksel;
 245         u32 hfir;
 246
 247         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 248
 249         /* Every time when port enables calculate HFIR.FrInterval */
 250         hfir = readl(hsotg->regs + HFIR);
 251         hfir &= ~HFIR_FRINT_MASK;
 252         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 253                 HFIR_FRINT_MASK;
 254         writel(hfir, hsotg->regs + HFIR);
 255
 256         /* Check if we need to adjust the PHY clock speed for low power */
 257         if (!params->host_support_fs_ls_low_power) {
 258                 /* Port has been enabled, set the reset change flag */
 259                 hsotg->flags.b.port_reset_change = 1;
 260                 return;
 261         }
 262
 263         usbcfg = readl(hsotg->regs + GUSBCFG);
 264         prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 265
 266         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 267                 /* Low power */
 268                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 269                         /* Set PHY low power clock select for FS/LS devices */
 270                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 271                         writel(usbcfg, hsotg->regs + GUSBCFG);
 272                         do_reset = 1;
 273                 }
 274
 275                 hcfg = readl(hsotg->regs + HCFG);
 276                 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
 277                               HCFG_FSLSPCLKSEL_SHIFT;
 278
 279                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 280                     params->host_ls_low_power_phy_clk ==
 281                     DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 282                         /* 6 MHZ */
 283                         dev_vdbg(hsotg->dev,
 284                                  "FS_PHY programming HCFG to 6 MHz\n");
 285                         if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 286                                 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
 287                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 288                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 289                                 writel(hcfg, hsotg->regs + HCFG);
 290                                 do_reset = 1;
 291                         }
 292                 } else {
 293                         /* 48 MHZ */
 294                         dev_vdbg(hsotg->dev,
 295                                  "FS_PHY programming HCFG to 48 MHz\n");
 296                         if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 297                                 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
 298                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 299                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 300                                 writel(hcfg, hsotg->regs + HCFG);
 301                                 do_reset = 1;
 302                         }
 303                 }
 304         } else {
 305                 /* Not low power */
 306                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 307                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 308                         writel(usbcfg, hsotg->regs + GUSBCFG);
 309                         do_reset = 1;
 310                 }
 311         }
 312
 313         if (do_reset) {
 314                 *hprt0_modify |= HPRT0_RST;
 315                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 316                                    msecs_to_jiffies(60));
 317         } else {
 318                 /* Port has been enabled, set the reset change flag */
 319                 hsotg->flags.b.port_reset_change = 1;
 320         }
 321 }
 322
 323 /*
 324  * There are multiple conditions that can cause a port interrupt. This function
 325  * determines which interrupt conditions have occurred and handles them
 326  * appropriately.
 327  */
 328 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 329 {
 330         u32 hprt0;
 331         u32 hprt0_modify;
 332
 333         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 334
 335         hprt0 = readl(hsotg->regs + HPRT0);
 336         hprt0_modify = hprt0;
 337
 338         /*
 339          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 340          * GINTSTS
 341          */
 342         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 343                           HPRT0_OVRCURRCHG);
 344
 345         /*
 346          * Port Connect Detected
 347          * Set flag and clear if detected
 348          */
 349         if (hprt0 & HPRT0_CONNDET) {
 350                 dev_vdbg(hsotg->dev,
 351                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 352                          hprt0);
 353                 hsotg->flags.b.port_connect_status_change = 1;
 354                 hsotg->flags.b.port_connect_status = 1;
 355                 hprt0_modify |= HPRT0_CONNDET;
 356
 357                 /*
 358                  * The Hub driver asserts a reset when it sees port connect
 359                  * status change flag
 360                  */
 361         }
 362
 363         /*
 364          * Port Enable Changed
 365          * Clear if detected - Set internal flag if disabled
 366          */
 367         if (hprt0 & HPRT0_ENACHG) {
 368                 dev_vdbg(hsotg->dev,
 369                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 370                          hprt0, !!(hprt0 & HPRT0_ENA));
 371                 hprt0_modify |= HPRT0_ENACHG;
 372                 if (hprt0 & HPRT0_ENA)
 373                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 374                 else
 375                         hsotg->flags.b.port_enable_change = 1;
 376         }
 377
 378         /* Overcurrent Change Interrupt */
 379         if (hprt0 & HPRT0_OVRCURRCHG) {
 380                 dev_vdbg(hsotg->dev,
 381                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 382                          hprt0);
 383                 hsotg->flags.b.port_over_current_change = 1;
 384                 hprt0_modify |= HPRT0_OVRCURRCHG;
 385         }
 386
 387         /* Clear Port Interrupts */
 388         writel(hprt0_modify, hsotg->regs + HPRT0);
 389 }
 390
 391 /*
 392  * Gets the actual length of a transfer after the transfer halts. halt_status
 393  * holds the reason for the halt.
 394  *
 395  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 396  * is set to 1 upon return if less than the requested number of bytes were
 397  * transferred. short_read may also be NULL on entry, in which case it remains
 398  * unchanged.
 399  */
 400 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 401                                        struct dwc2_host_chan *chan, int chnum,
 402                                        struct dwc2_qtd *qtd,
 403                                        enum dwc2_halt_status halt_status,
 404                                        int *short_read)
 405 {
 406         u32 hctsiz, count, length;
 407
 408         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 409
 410         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 411                 if (chan->ep_is_in) {
 412                         count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
 413                                 TSIZ_XFERSIZE_SHIFT;
 414                         length = chan->xfer_len - count;
 415                         if (short_read != NULL)
 416                                 *short_read = (count != 0);
 417                 } else if (chan->qh->do_split) {
 418                         length = qtd->ssplit_out_xfer_count;
 419                 } else {
 420                         length = chan->xfer_len;
 421                 }
 422         } else {
 423                 /*
 424                  * Must use the hctsiz.pktcnt field to determine how much data
 425                  * has been transferred. This field reflects the number of
 426                  * packets that have been transferred via the USB. This is
 427                  * always an integral number of packets if the transfer was
 428                  * halted before its normal completion. (Can't use the
 429                  * hctsiz.xfersize field because that reflects the number of
 430                  * bytes transferred via the AHB, not the USB).
 431                  */
 432                 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
 433                 length = (chan->start_pkt_count - count) * chan->max_packet;
 434         }
 435
 436         return length;
 437 }
 438
 439 /**
 440  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 441  * Complete interrupt on the host channel. Updates the actual_length field
 442  * of the URB based on the number of bytes transferred via the host channel.
 443  * Sets the URB status if the data transfer is finished.
 444  *
 445  * Return: 1 if the data transfer specified by the URB is completely finished,
 446  * 0 otherwise
 447  */
 448 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 449                                  struct dwc2_host_chan *chan, int chnum,
 450                                  struct dwc2_hcd_urb *urb,
 451                                  struct dwc2_qtd *qtd)
 452 {
 453         u32 hctsiz;
 454         int xfer_done = 0;
 455         int short_read = 0;
 456         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 457                                                       DWC2_HC_XFER_COMPLETE,
 458                                                       &short_read);
 459
 460         if (urb->actual_length + xfer_length > urb->length) {
 461                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 462                 xfer_length = urb->length - urb->actual_length;
 463         }
 464
 465         /* Non DWORD-aligned buffer case handling */
 466         if (chan->align_buf && xfer_length && chan->ep_is_in) {
 467                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 468                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
 469                                         DMA_FROM_DEVICE);
 470                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
 471                        xfer_length);
 472                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
 473                                            DMA_FROM_DEVICE);
 474         }
 475
 476         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 477                  urb->actual_length, xfer_length);
 478         urb->actual_length += xfer_length;
 479
 480         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 481             (urb->flags & URB_SEND_ZERO_PACKET) &&
 482             urb->actual_length >= urb->length &&
 483             !(urb->length % chan->max_packet)) {
 484                 xfer_done = 0;
 485         } else if (short_read || urb->actual_length >= urb->length) {
 486                 xfer_done = 1;
 487                 urb->status = 0;
 488         }
 489
 490         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 491         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 492                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 493         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 494         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 495                  (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
 496         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 497         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 498         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 499                  xfer_done);
 500
 501         return xfer_done;
 502 }
 503
 504 /*
 505  * Save the starting data toggle for the next transfer. The data toggle is
 506  * saved in the QH for non-control transfers and it's saved in the QTD for
 507  * control transfers.
 508  */
 509 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 510                                struct dwc2_host_chan *chan, int chnum,
 511                                struct dwc2_qtd *qtd)
 512 {
 513         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 514         u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 515
 516         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 517                 if (pid == TSIZ_SC_MC_PID_DATA0)
 518                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 519                 else
 520                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 521         } else {
 522                 if (pid == TSIZ_SC_MC_PID_DATA0)
 523                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 524                 else
 525                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 526         }
 527 }
 528
 529 /**
 530  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 531  * the transfer is stopped for any reason. The fields of the current entry in
 532  * the frame descriptor array are set based on the transfer state and the input
 533  * halt_status. Completes the Isochronous URB if all the URB frames have been
 534  * completed.
 535  *
 536  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 537  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 538  */
 539 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 540                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 541                 int chnum, struct dwc2_qtd *qtd,
 542                 enum dwc2_halt_status halt_status)
 543 {
 544         struct dwc2_hcd_iso_packet_desc *frame_desc;
 545         struct dwc2_hcd_urb *urb = qtd->urb;
 546
 547         if (!urb)
 548                 return DWC2_HC_XFER_NO_HALT_STATUS;
 549
 550         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 551
 552         switch (halt_status) {
 553         case DWC2_HC_XFER_COMPLETE:
 554                 frame_desc->status = 0;
 555                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 556                                         chan, chnum, qtd, halt_status, NULL);
 557
 558                 /* Non DWORD-aligned buffer case handling */
 559                 if (chan->align_buf && frame_desc->actual_length &&
 560                     chan->ep_is_in) {
 561                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 562                                  __func__);
 563                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 564                                                 urb->length, DMA_FROM_DEVICE);
 565                         memcpy(urb->buf + frame_desc->offset +
 566                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 567                                frame_desc->actual_length);
 568                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 569                                                    urb->length,
 570                                                    DMA_FROM_DEVICE);
 571                 }
 572                 break;
 573         case DWC2_HC_XFER_FRAME_OVERRUN:
 574                 urb->error_count++;
 575                 if (chan->ep_is_in)
 576                         frame_desc->status = -ENOSR;
 577                 else
 578                         frame_desc->status = -ECOMM;
 579                 frame_desc->actual_length = 0;
 580                 break;
 581         case DWC2_HC_XFER_BABBLE_ERR:
 582                 urb->error_count++;
 583                 frame_desc->status = -EOVERFLOW;
 584                 /* Don't need to update actual_length in this case */
 585                 break;
 586         case DWC2_HC_XFER_XACT_ERR:
 587                 urb->error_count++;
 588                 frame_desc->status = -EPROTO;
 589                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 590                                         chan, chnum, qtd, halt_status, NULL);
 591
 592                 /* Non DWORD-aligned buffer case handling */
 593                 if (chan->align_buf && frame_desc->actual_length &&
 594                     chan->ep_is_in) {
 595                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 596                                  __func__);
 597                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 598                                                 urb->length, DMA_FROM_DEVICE);
 599                         memcpy(urb->buf + frame_desc->offset +
 600                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 601                                frame_desc->actual_length);
 602                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 603                                                    urb->length,
 604                                                    DMA_FROM_DEVICE);
 605                 }
 606
 607                 /* Skip whole frame */
 608                 if (chan->qh->do_split &&
 609                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 610                     hsotg->core_params->dma_enable > 0) {
 611                         qtd->complete_split = 0;
 612                         qtd->isoc_split_offset = 0;
 613                 }
 614
 615                 break;
 616         default:
 617                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 618                         halt_status);
 619                 break;
 620         }
 621
 622         if (++qtd->isoc_frame_index == urb->packet_count) {
 623                 /*
 624                  * urb->status is not used for isoc transfers. The individual
 625                  * frame_desc statuses are used instead.
 626                  */
 627                 dwc2_host_complete(hsotg, qtd, 0);
 628                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 629         } else {
 630                 halt_status = DWC2_HC_XFER_COMPLETE;
 631         }
 632
 633         return halt_status;
 634 }
 635
 636 /*
 637  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 638  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 639  * still linked to the QH, the QH is added to the end of the inactive
 640  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 641  * schedule if no more QTDs are linked to the QH.
 642  */
 643 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 644                                int free_qtd)
 645 {
 646         int continue_split = 0;
 647         struct dwc2_qtd *qtd;
 648
 649         if (dbg_qh(qh))
 650                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 651                          hsotg, qh, free_qtd);
 652
 653         if (list_empty(&qh->qtd_list)) {
 654                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 655                 goto no_qtd;
 656         }
 657
 658         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 659
 660         if (qtd->complete_split)
 661                 continue_split = 1;
 662         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 663                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 664                 continue_split = 1;
 665
 666         if (free_qtd) {
 667                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 668                 continue_split = 0;
 669         }
 670
 671 no_qtd:
 672         if (qh->channel)
 673                 qh->channel->align_buf = 0;
 674         qh->channel = NULL;
 675         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 676 }
 677
 678 /**
 679  * dwc2_release_channel() - Releases a host channel for use by other transfers
 680  *
 681  * @hsotg:       The HCD state structure
 682  * @chan:        The host channel to release
 683  * @qtd:         The QTD associated with the host channel. This QTD may be
 684  *               freed if the transfer is complete or an error has occurred.
 685  * @halt_status: Reason the channel is being released. This status
 686  *               determines the actions taken by this function.
 687  *
 688  * Also attempts to select and queue more transactions since at least one host
 689  * channel is available.
 690  */
 691 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 692                                  struct dwc2_host_chan *chan,
 693                                  struct dwc2_qtd *qtd,
 694                                  enum dwc2_halt_status halt_status)
 695 {
 696         enum dwc2_transaction_type tr_type;
 697         u32 haintmsk;
 698         int free_qtd = 0;
 699
 700         if (dbg_hc(chan))
 701                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 702                          __func__, chan->hc_num, halt_status);
 703
 704         switch (halt_status) {
 705         case DWC2_HC_XFER_URB_COMPLETE:
 706                 free_qtd = 1;
 707                 break;
 708         case DWC2_HC_XFER_AHB_ERR:
 709         case DWC2_HC_XFER_STALL:
 710         case DWC2_HC_XFER_BABBLE_ERR:
 711                 free_qtd = 1;
 712                 break;
 713         case DWC2_HC_XFER_XACT_ERR:
 714                 if (qtd && qtd->error_count >= 3) {
 715                         dev_vdbg(hsotg->dev,
 716                                  "  Complete URB with transaction error\n");
 717                         free_qtd = 1;
 718                         dwc2_host_complete(hsotg, qtd, -EPROTO);
 719                 }
 720                 break;
 721         case DWC2_HC_XFER_URB_DEQUEUE:
 722                 /*
 723                  * The QTD has already been removed and the QH has been
 724                  * deactivated. Don't want to do anything except release the
 725                  * host channel and try to queue more transfers.
 726                  */
 727                 goto cleanup;
 728         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 729                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 730                 free_qtd = 1;
 731                 dwc2_host_complete(hsotg, qtd, -EIO);
 732                 break;
 733         case DWC2_HC_XFER_NO_HALT_STATUS:
 734         default:
 735                 break;
 736         }
 737
 738         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 739
 740 cleanup:
 741         /*
 742          * Release the host channel for use by other transfers. The cleanup
 743          * function clears the channel interrupt enables and conditions, so
 744          * there's no need to clear the Channel Halted interrupt separately.
 745          */
 746         if (!list_empty(&chan->hc_list_entry))
 747                 list_del(&chan->hc_list_entry);
 748         dwc2_hc_cleanup(hsotg, chan);
 749         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 750
 751         if (hsotg->core_params->uframe_sched > 0) {
 752                 hsotg->available_host_channels++;
 753         } else {
 754                 switch (chan->ep_type) {
 755                 case USB_ENDPOINT_XFER_CONTROL:
 756                 case USB_ENDPOINT_XFER_BULK:
 757                         hsotg->non_periodic_channels--;
 758                         break;
 759                 default:
 760                         /*
 761                          * Don't release reservations for periodic channels
 762                          * here. That's done when a periodic transfer is
 763                          * descheduled (i.e. when the QH is removed from the
 764                          * periodic schedule).
 765                          */
 766                         break;
 767                 }
 768         }
 769
 770         haintmsk = readl(hsotg->regs + HAINTMSK);
 771         haintmsk &= ~(1 << chan->hc_num);
 772         writel(haintmsk, hsotg->regs + HAINTMSK);
 773
 774         /* Try to queue more transfers now that there's a free channel */
 775         tr_type = dwc2_hcd_select_transactions(hsotg);
 776         if (tr_type != DWC2_TRANSACTION_NONE)
 777                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 778 }
 779
 780 /*
 781  * Halts a host channel. If the channel cannot be halted immediately because
 782  * the request queue is full, this function ensures that the FIFO empty
 783  * interrupt for the appropriate queue is enabled so that the halt request can
 784  * be queued when there is space in the request queue.
 785  *
 786  * This function may also be called in DMA mode. In that case, the channel is
 787  * simply released since the core always halts the channel automatically in
 788  * DMA mode.
 789  */
 790 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 791                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 792                               enum dwc2_halt_status halt_status)
 793 {
 794         if (dbg_hc(chan))
 795                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 796
 797         if (hsotg->core_params->dma_enable > 0) {
 798                 if (dbg_hc(chan))
 799                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 800                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 801                 return;
 802         }
 803
 804         /* Slave mode processing */
 805         dwc2_hc_halt(hsotg, chan, halt_status);
 806
 807         if (chan->halt_on_queue) {
 808                 u32 gintmsk;
 809
 810                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 811                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 812                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 813                         dev_vdbg(hsotg->dev, "control/bulk\n");
 814                         /*
 815                          * Make sure the Non-periodic Tx FIFO empty interrupt
 816                          * is enabled so that the non-periodic schedule will
 817                          * be processed
 818                          */
 819                         gintmsk = readl(hsotg->regs + GINTMSK);
 820                         gintmsk |= GINTSTS_NPTXFEMP;
 821                         writel(gintmsk, hsotg->regs + GINTMSK);
 822                 } else {
 823                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 824                         /*
 825                          * Move the QH from the periodic queued schedule to
 826                          * the periodic assigned schedule. This allows the
 827                          * halt to be queued when the periodic schedule is
 828                          * processed.
 829                          */
 830                         list_move(&chan->qh->qh_list_entry,
 831                                   &hsotg->periodic_sched_assigned);
 832
 833                         /*
 834                          * Make sure the Periodic Tx FIFO Empty interrupt is
 835                          * enabled so that the periodic schedule will be
 836                          * processed
 837                          */
 838                         gintmsk = readl(hsotg->regs + GINTMSK);
 839                         gintmsk |= GINTSTS_PTXFEMP;
 840                         writel(gintmsk, hsotg->regs + GINTMSK);
 841                 }
 842         }
 843 }
 844
 845 /*
 846  * Performs common cleanup for non-periodic transfers after a Transfer
 847  * Complete interrupt. This function should be called after any endpoint type
 848  * specific handling is finished to release the host channel.
 849  */
 850 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 851                                             struct dwc2_host_chan *chan,
 852                                             int chnum, struct dwc2_qtd *qtd,
 853                                             enum dwc2_halt_status halt_status)
 854 {
 855         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 856
 857         qtd->error_count = 0;
 858
 859         if (chan->hcint & HCINTMSK_NYET) {
 860                 /*
 861                  * Got a NYET on the last transaction of the transfer. This
 862                  * means that the endpoint should be in the PING state at the
 863                  * beginning of the next transfer.
 864                  */
 865                 dev_vdbg(hsotg->dev, "got NYET\n");
 866                 chan->qh->ping_state = 1;
 867         }
 868
 869         /*
 870          * Always halt and release the host channel to make it available for
 871          * more transfers. There may still be more phases for a control
 872          * transfer or more data packets for a bulk transfer at this point,
 873          * but the host channel is still halted. A channel will be reassigned
 874          * to the transfer when the non-periodic schedule is processed after
 875          * the channel is released. This allows transactions to be queued
 876          * properly via dwc2_hcd_queue_transactions, which also enables the
 877          * Tx FIFO Empty interrupt if necessary.
 878          */
 879         if (chan->ep_is_in) {
 880                 /*
 881                  * IN transfers in Slave mode require an explicit disable to
 882                  * halt the channel. (In DMA mode, this call simply releases
 883                  * the channel.)
 884                  */
 885                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 886         } else {
 887                 /*
 888                  * The channel is automatically disabled by the core for OUT
 889                  * transfers in Slave mode
 890                  */
 891                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 892         }
 893 }
 894
 895 /*
 896  * Performs common cleanup for periodic transfers after a Transfer Complete
 897  * interrupt. This function should be called after any endpoint type specific
 898  * handling is finished to release the host channel.
 899  */
 900 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 901                                         struct dwc2_host_chan *chan, int chnum,
 902                                         struct dwc2_qtd *qtd,
 903                                         enum dwc2_halt_status halt_status)
 904 {
 905         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 906
 907         qtd->error_count = 0;
 908
 909         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 910                 /* Core halts channel in these cases */
 911                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 912         else
 913                 /* Flush any outstanding requests from the Tx queue */
 914                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 915 }
 916
 917 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 918                                        struct dwc2_host_chan *chan, int chnum,
 919                                        struct dwc2_qtd *qtd)
 920 {
 921         struct dwc2_hcd_iso_packet_desc *frame_desc;
 922         u32 len;
 923
 924         if (!qtd->urb)
 925                 return 0;
 926
 927         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 928         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 929                                           DWC2_HC_XFER_COMPLETE, NULL);
 930         if (!len) {
 931                 qtd->complete_split = 0;
 932                 qtd->isoc_split_offset = 0;
 933                 return 0;
 934         }
 935
 936         frame_desc->actual_length += len;
 937
 938         if (chan->align_buf && len) {
 939                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 940                 dma_sync_single_for_cpu(hsotg->dev, qtd->urb->dma,
 941                                         qtd->urb->length, DMA_FROM_DEVICE);
 942                 memcpy(qtd->urb->buf + frame_desc->offset +
 943                        qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
 944                 dma_sync_single_for_device(hsotg->dev, qtd->urb->dma,
 945                                            qtd->urb->length, DMA_FROM_DEVICE);
 946         }
 947
 948         qtd->isoc_split_offset += len;
 949
 950         if (frame_desc->actual_length >= frame_desc->length) {
 951                 frame_desc->status = 0;
 952                 qtd->isoc_frame_index++;
 953                 qtd->complete_split = 0;
 954                 qtd->isoc_split_offset = 0;
 955         }
 956
 957         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 958                 dwc2_host_complete(hsotg, qtd, 0);
 959                 dwc2_release_channel(hsotg, chan, qtd,
 960                                      DWC2_HC_XFER_URB_COMPLETE);
 961         } else {
 962                 dwc2_release_channel(hsotg, chan, qtd,
 963                                      DWC2_HC_XFER_NO_HALT_STATUS);
 964         }
 965
 966         return 1;       /* Indicates that channel released */
 967 }
 968
 969 /*
 970  * Handles a host channel Transfer Complete interrupt. This handler may be
 971  * called in either DMA mode or Slave mode.
 972  */
 973 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 974                                   struct dwc2_host_chan *chan, int chnum,
 975                                   struct dwc2_qtd *qtd)
 976 {
 977         struct dwc2_hcd_urb *urb = qtd->urb;
 978         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 979         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 980         int urb_xfer_done;
 981
 982         if (dbg_hc(chan))
 983                 dev_vdbg(hsotg->dev,
 984                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 985                          chnum);
 986
 987         if (hsotg->core_params->dma_desc_enable > 0) {
 988                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
 989                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
 990                         /* Do not disable the interrupt, just clear it */
 991                         return;
 992                 goto handle_xfercomp_done;
 993         }
 994
 995         /* Handle xfer complete on CSPLIT */
 996         if (chan->qh->do_split) {
 997                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 998                     hsotg->core_params->dma_enable > 0) {
 999                         if (qtd->complete_split &&
1000                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1001                                                         qtd))
1002                                 goto handle_xfercomp_done;
1003                 } else {
1004                         qtd->complete_split = 0;
1005                 }
1006         }
1007
1008         if (!urb)
1009                 goto handle_xfercomp_done;
1010
1011         /* Update the QTD and URB states */
1012         switch (pipe_type) {
1013         case USB_ENDPOINT_XFER_CONTROL:
1014                 switch (qtd->control_phase) {
1015                 case DWC2_CONTROL_SETUP:
1016                         if (urb->length > 0)
1017                                 qtd->control_phase = DWC2_CONTROL_DATA;
1018                         else
1019                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1020                         dev_vdbg(hsotg->dev,
1021                                  "  Control setup transaction done\n");
1022                         halt_status = DWC2_HC_XFER_COMPLETE;
1023                         break;
1024                 case DWC2_CONTROL_DATA:
1025                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1026                                                               chnum, urb, qtd);
1027                         if (urb_xfer_done) {
1028                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1029                                 dev_vdbg(hsotg->dev,
1030                                          "  Control data transfer done\n");
1031                         } else {
1032                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1033                                                           qtd);
1034                         }
1035                         halt_status = DWC2_HC_XFER_COMPLETE;
1036                         break;
1037                 case DWC2_CONTROL_STATUS:
1038                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1039                         if (urb->status == -EINPROGRESS)
1040                                 urb->status = 0;
1041                         dwc2_host_complete(hsotg, qtd, urb->status);
1042                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1043                         break;
1044                 }
1045
1046                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1047                                                 halt_status);
1048                 break;
1049         case USB_ENDPOINT_XFER_BULK:
1050                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1051                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1052                                                       qtd);
1053                 if (urb_xfer_done) {
1054                         dwc2_host_complete(hsotg, qtd, urb->status);
1055                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1056                 } else {
1057                         halt_status = DWC2_HC_XFER_COMPLETE;
1058                 }
1059
1060                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1061                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1062                                                 halt_status);
1063                 break;
1064         case USB_ENDPOINT_XFER_INT:
1065                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1066                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1067                                                       qtd);
1068
1069                 /*
1070                  * Interrupt URB is done on the first transfer complete
1071                  * interrupt
1072                  */
1073                 if (urb_xfer_done) {
1074                         dwc2_host_complete(hsotg, qtd, urb->status);
1075                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1076                 } else {
1077                         halt_status = DWC2_HC_XFER_COMPLETE;
1078                 }
1079
1080                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1081                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1082                                             halt_status);
1083                 break;
1084         case USB_ENDPOINT_XFER_ISOC:
1085                 if (dbg_perio())
1086                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1087                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1088                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1089                                         chnum, qtd, DWC2_HC_XFER_COMPLETE);
1090                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1091                                             halt_status);
1092                 break;
1093         }
1094
1095 handle_xfercomp_done:
1096         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1097 }
1098
1099 /*
1100  * Handles a host channel STALL interrupt. This handler may be called in
1101  * either DMA mode or Slave mode.
1102  */
1103 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1104                                struct dwc2_host_chan *chan, int chnum,
1105                                struct dwc2_qtd *qtd)
1106 {
1107         struct dwc2_hcd_urb *urb = qtd->urb;
1108         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1109
1110         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1111                 chnum);
1112
1113         if (hsotg->core_params->dma_desc_enable > 0) {
1114                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1115                                             DWC2_HC_XFER_STALL);
1116                 goto handle_stall_done;
1117         }
1118
1119         if (!urb)
1120                 goto handle_stall_halt;
1121
1122         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1123                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1124
1125         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1126             pipe_type == USB_ENDPOINT_XFER_INT) {
1127                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1128                 /*
1129                  * USB protocol requires resetting the data toggle for bulk
1130                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1131                  * setup command is issued to the endpoint. Anticipate the
1132                  * CLEAR_FEATURE command since a STALL has occurred and reset
1133                  * the data toggle now.
1134                  */
1135                 chan->qh->data_toggle = 0;
1136         }
1137
1138 handle_stall_halt:
1139         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1140
1141 handle_stall_done:
1142         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1143 }
1144
1145 /*
1146  * Updates the state of the URB when a transfer has been stopped due to an
1147  * abnormal condition before the transfer completes. Modifies the
1148  * actual_length field of the URB to reflect the number of bytes that have
1149  * actually been transferred via the host channel.
1150  */
1151 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1152                                       struct dwc2_host_chan *chan, int chnum,
1153                                       struct dwc2_hcd_urb *urb,
1154                                       struct dwc2_qtd *qtd,
1155                                       enum dwc2_halt_status halt_status)
1156 {
1157         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1158                                                       qtd, halt_status, NULL);
1159         u32 hctsiz;
1160
1161         if (urb->actual_length + xfer_length > urb->length) {
1162                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1163                 xfer_length = urb->length - urb->actual_length;
1164         }
1165
1166         /* Non DWORD-aligned buffer case handling */
1167         if (chan->align_buf && xfer_length && chan->ep_is_in) {
1168                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1169                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
1170                                         DMA_FROM_DEVICE);
1171                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
1172                        xfer_length);
1173                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
1174                                            DMA_FROM_DEVICE);
1175         }
1176
1177         urb->actual_length += xfer_length;
1178
1179         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1180         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1181                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1182         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1183                  chan->start_pkt_count);
1184         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1185                  (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1186         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1187         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1188                  xfer_length);
1189         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1190                  urb->actual_length);
1191         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1192                  urb->length);
1193 }
1194
1195 /*
1196  * Handles a host channel NAK interrupt. This handler may be called in either
1197  * DMA mode or Slave mode.
1198  */
1199 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1200                              struct dwc2_host_chan *chan, int chnum,
1201                              struct dwc2_qtd *qtd)
1202 {
1203         if (dbg_hc(chan))
1204                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1205                          chnum);
1206
1207         /*
1208          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1209          * interrupt. Re-start the SSPLIT transfer.
1210          */
1211         if (chan->do_split) {
1212                 if (chan->complete_split)
1213                         qtd->error_count = 0;
1214                 qtd->complete_split = 0;
1215                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1216                 goto handle_nak_done;
1217         }
1218
1219         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1220         case USB_ENDPOINT_XFER_CONTROL:
1221         case USB_ENDPOINT_XFER_BULK:
1222                 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1223                         /*
1224                          * NAK interrupts are enabled on bulk/control IN
1225                          * transfers in DMA mode for the sole purpose of
1226                          * resetting the error count after a transaction error
1227                          * occurs. The core will continue transferring data.
1228                          */
1229                         qtd->error_count = 0;
1230                         break;
1231                 }
1232
1233                 /*
1234                  * NAK interrupts normally occur during OUT transfers in DMA
1235                  * or Slave mode. For IN transfers, more requests will be
1236                  * queued as request queue space is available.
1237                  */
1238                 qtd->error_count = 0;
1239
1240                 if (!chan->qh->ping_state) {
1241                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1242                                                   qtd, DWC2_HC_XFER_NAK);
1243                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1244
1245                         if (chan->speed == USB_SPEED_HIGH)
1246                                 chan->qh->ping_state = 1;
1247                 }
1248
1249                 /*
1250                  * Halt the channel so the transfer can be re-started from
1251                  * the appropriate point or the PING protocol will
1252                  * start/continue
1253                  */
1254                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1255                 break;
1256         case USB_ENDPOINT_XFER_INT:
1257                 qtd->error_count = 0;
1258                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1259                 break;
1260         case USB_ENDPOINT_XFER_ISOC:
1261                 /* Should never get called for isochronous transfers */
1262                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1263                 break;
1264         }
1265
1266 handle_nak_done:
1267         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1268 }
1269
1270 /*
1271  * Handles a host channel ACK interrupt. This interrupt is enabled when
1272  * performing the PING protocol in Slave mode, when errors occur during
1273  * either Slave mode or DMA mode, and during Start Split transactions.
1274  */
1275 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1276                              struct dwc2_host_chan *chan, int chnum,
1277                              struct dwc2_qtd *qtd)
1278 {
1279         struct dwc2_hcd_iso_packet_desc *frame_desc;
1280
1281         if (dbg_hc(chan))
1282                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1283                          chnum);
1284
1285         if (chan->do_split) {
1286                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1287                 if (!chan->ep_is_in &&
1288                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1289                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1290
1291                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1292                         qtd->complete_split = 1;
1293                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1294                 } else {
1295                         /* ISOC OUT */
1296                         switch (chan->xact_pos) {
1297                         case DWC2_HCSPLT_XACTPOS_ALL:
1298                                 break;
1299                         case DWC2_HCSPLT_XACTPOS_END:
1300                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1301                                 qtd->isoc_split_offset = 0;
1302                                 break;
1303                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1304                         case DWC2_HCSPLT_XACTPOS_MID:
1305                                 /*
1306                                  * For BEGIN or MID, calculate the length for
1307                                  * the next microframe to determine the correct
1308                                  * SSPLIT token, either MID or END
1309                                  */
1310                                 frame_desc = &qtd->urb->iso_descs[
1311                                                 qtd->isoc_frame_index];
1312                                 qtd->isoc_split_offset += 188;
1313
1314                                 if (frame_desc->length - qtd->isoc_split_offset
1315                                                         <= 188)
1316                                         qtd->isoc_split_pos =
1317                                                         DWC2_HCSPLT_XACTPOS_END;
1318                                 else
1319                                         qtd->isoc_split_pos =
1320                                                         DWC2_HCSPLT_XACTPOS_MID;
1321                                 break;
1322                         }
1323                 }
1324         } else {
1325                 qtd->error_count = 0;
1326
1327                 if (chan->qh->ping_state) {
1328                         chan->qh->ping_state = 0;
1329                         /*
1330                          * Halt the channel so the transfer can be re-started
1331                          * from the appropriate point. This only happens in
1332                          * Slave mode. In DMA mode, the ping_state is cleared
1333                          * when the transfer is started because the core
1334                          * automatically executes the PING, then the transfer.
1335                          */
1336                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1337                 }
1338         }
1339
1340         /*
1341          * If the ACK occurred when _not_ in the PING state, let the channel
1342          * continue transferring data after clearing the error count
1343          */
1344         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1345 }
1346
1347 /*
1348  * Handles a host channel NYET interrupt. This interrupt should only occur on
1349  * Bulk and Control OUT endpoints and for complete split transactions. If a
1350  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1351  * handled in the xfercomp interrupt handler, not here. This handler may be
1352  * called in either DMA mode or Slave mode.
1353  */
1354 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1355                               struct dwc2_host_chan *chan, int chnum,
1356                               struct dwc2_qtd *qtd)
1357 {
1358         if (dbg_hc(chan))
1359                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1360                          chnum);
1361
1362         /*
1363          * NYET on CSPLIT
1364          * re-do the CSPLIT immediately on non-periodic
1365          */
1366         if (chan->do_split && chan->complete_split) {
1367                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1368                     hsotg->core_params->dma_enable > 0) {
1369                         qtd->complete_split = 0;
1370                         qtd->isoc_split_offset = 0;
1371                         qtd->isoc_frame_index++;
1372                         if (qtd->urb &&
1373                             qtd->isoc_frame_index == qtd->urb->packet_count) {
1374                                 dwc2_host_complete(hsotg, qtd, 0);
1375                                 dwc2_release_channel(hsotg, chan, qtd,
1376                                                      DWC2_HC_XFER_URB_COMPLETE);
1377                         } else {
1378                                 dwc2_release_channel(hsotg, chan, qtd,
1379                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1380                         }
1381                         goto handle_nyet_done;
1382                 }
1383
1384                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1385                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1386                         int frnum = dwc2_hcd_get_frame_number(hsotg);
1387
1388                         if (dwc2_full_frame_num(frnum) !=
1389                             dwc2_full_frame_num(chan->qh->sched_frame)) {
1390                                 /*
1391                                  * No longer in the same full speed frame.
1392                                  * Treat this as a transaction error.
1393                                  */
1394 #if 0
1395                                 /*
1396                                  * Todo: Fix system performance so this can
1397                                  * be treated as an error. Right now complete
1398                                  * splits cannot be scheduled precisely enough
1399                                  * due to other system activity, so this error
1400                                  * occurs regularly in Slave mode.
1401                                  */
1402                                 qtd->error_count++;
1403 #endif
1404                                 qtd->complete_split = 0;
1405                                 dwc2_halt_channel(hsotg, chan, qtd,
1406                                                   DWC2_HC_XFER_XACT_ERR);
1407                                 /* Todo: add support for isoc release */
1408                                 goto handle_nyet_done;
1409                         }
1410                 }
1411
1412                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1413                 goto handle_nyet_done;
1414         }
1415
1416         chan->qh->ping_state = 1;
1417         qtd->error_count = 0;
1418
1419         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1420                                   DWC2_HC_XFER_NYET);
1421         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1422
1423         /*
1424          * Halt the channel and re-start the transfer so the PING protocol
1425          * will start
1426          */
1427         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1428
1429 handle_nyet_done:
1430         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1431 }
1432
1433 /*
1434  * Handles a host channel babble interrupt. This handler may be called in
1435  * either DMA mode or Slave mode.
1436  */
1437 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1438                                 struct dwc2_host_chan *chan, int chnum,
1439                                 struct dwc2_qtd *qtd)
1440 {
1441         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1442                 chnum);
1443
1444         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1445
1446         if (hsotg->core_params->dma_desc_enable > 0) {
1447                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1448                                             DWC2_HC_XFER_BABBLE_ERR);
1449                 goto disable_int;
1450         }
1451
1452         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1453                 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1454                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1455         } else {
1456                 enum dwc2_halt_status halt_status;
1457
1458                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1459                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1460                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1461         }
1462
1463 disable_int:
1464         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1465 }
1466
1467 /*
1468  * Handles a host channel AHB error interrupt. This handler is only called in
1469  * DMA mode.
1470  */
1471 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1472                                 struct dwc2_host_chan *chan, int chnum,
1473                                 struct dwc2_qtd *qtd)
1474 {
1475         struct dwc2_hcd_urb *urb = qtd->urb;
1476         char *pipetype, *speed;
1477         u32 hcchar;
1478         u32 hcsplt;
1479         u32 hctsiz;
1480         u32 hc_dma;
1481
1482         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1483                 chnum);
1484
1485         if (!urb)
1486                 goto handle_ahberr_halt;
1487
1488         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1489
1490         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1491         hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1492         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1493         hc_dma = readl(hsotg->regs + HCDMA(chnum));
1494
1495         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1496         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1497         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1498         dev_err(hsotg->dev, "  Device address: %d\n",
1499                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1500         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1501                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1502                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1503
1504         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1505         case USB_ENDPOINT_XFER_CONTROL:
1506                 pipetype = "CONTROL";
1507                 break;
1508         case USB_ENDPOINT_XFER_BULK:
1509                 pipetype = "BULK";
1510                 break;
1511         case USB_ENDPOINT_XFER_INT:
1512                 pipetype = "INTERRUPT";
1513                 break;
1514         case USB_ENDPOINT_XFER_ISOC:
1515                 pipetype = "ISOCHRONOUS";
1516                 break;
1517         default:
1518                 pipetype = "UNKNOWN";
1519                 break;
1520         }
1521
1522         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1523
1524         switch (chan->speed) {
1525         case USB_SPEED_HIGH:
1526                 speed = "HIGH";
1527                 break;
1528         case USB_SPEED_FULL:
1529                 speed = "FULL";
1530                 break;
1531         case USB_SPEED_LOW:
1532                 speed = "LOW";
1533                 break;
1534         default:
1535                 speed = "UNKNOWN";
1536                 break;
1537         }
1538
1539         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1540
1541         dev_err(hsotg->dev, "  Max packet size: %d\n",
1542                 dwc2_hcd_get_mps(&urb->pipe_info));
1543         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1544         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1545                 urb->buf, (unsigned long)urb->dma);
1546         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1547                 urb->setup_packet, (unsigned long)urb->setup_dma);
1548         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1549
1550         /* Core halts the channel for Descriptor DMA mode */
1551         if (hsotg->core_params->dma_desc_enable > 0) {
1552                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1553                                             DWC2_HC_XFER_AHB_ERR);
1554                 goto handle_ahberr_done;
1555         }
1556
1557         dwc2_host_complete(hsotg, qtd, -EIO);
1558
1559 handle_ahberr_halt:
1560         /*
1561          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1562          * write to the HCCHARn register in DMA mode to force the halt.
1563          */
1564         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1565
1566 handle_ahberr_done:
1567         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1568 }
1569
1570 /*
1571  * Handles a host channel transaction error interrupt. This handler may be
1572  * called in either DMA mode or Slave mode.
1573  */
1574 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1575                                  struct dwc2_host_chan *chan, int chnum,
1576                                  struct dwc2_qtd *qtd)
1577 {
1578         dev_dbg(hsotg->dev,
1579                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1580
1581         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1582
1583         if (hsotg->core_params->dma_desc_enable > 0) {
1584                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1585                                             DWC2_HC_XFER_XACT_ERR);
1586                 goto handle_xacterr_done;
1587         }
1588
1589         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1590         case USB_ENDPOINT_XFER_CONTROL:
1591         case USB_ENDPOINT_XFER_BULK:
1592                 qtd->error_count++;
1593                 if (!chan->qh->ping_state) {
1594
1595                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1596                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1597                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1598                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1599                                 chan->qh->ping_state = 1;
1600                 }
1601
1602                 /*
1603                  * Halt the channel so the transfer can be re-started from
1604                  * the appropriate point or the PING protocol will start
1605                  */
1606                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1607                 break;
1608         case USB_ENDPOINT_XFER_INT:
1609                 qtd->error_count++;
1610                 if (chan->do_split && chan->complete_split)
1611                         qtd->complete_split = 0;
1612                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1613                 break;
1614         case USB_ENDPOINT_XFER_ISOC:
1615                 {
1616                         enum dwc2_halt_status halt_status;
1617
1618                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1619                                         chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1620                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1621                 }
1622                 break;
1623         }
1624
1625 handle_xacterr_done:
1626         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1627 }
1628
1629 /*
1630  * Handles a host channel frame overrun interrupt. This handler may be called
1631  * in either DMA mode or Slave mode.
1632  */
1633 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1634                                   struct dwc2_host_chan *chan, int chnum,
1635                                   struct dwc2_qtd *qtd)
1636 {
1637         enum dwc2_halt_status halt_status;
1638
1639         if (dbg_hc(chan))
1640                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1641                         chnum);
1642
1643         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1644
1645         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1646         case USB_ENDPOINT_XFER_CONTROL:
1647         case USB_ENDPOINT_XFER_BULK:
1648                 break;
1649         case USB_ENDPOINT_XFER_INT:
1650                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1651                 break;
1652         case USB_ENDPOINT_XFER_ISOC:
1653                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1654                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1655                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1656                 break;
1657         }
1658
1659         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1660 }
1661
1662 /*
1663  * Handles a host channel data toggle error interrupt. This handler may be
1664  * called in either DMA mode or Slave mode.
1665  */
1666 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1667                                     struct dwc2_host_chan *chan, int chnum,
1668                                     struct dwc2_qtd *qtd)
1669 {
1670         dev_dbg(hsotg->dev,
1671                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1672
1673         if (chan->ep_is_in)
1674                 qtd->error_count = 0;
1675         else
1676                 dev_err(hsotg->dev,
1677                         "Data Toggle Error on OUT transfer, channel %d\n",
1678                         chnum);
1679
1680         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1681         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1682 }
1683
1684 /*
1685  * For debug only. It checks that a valid halt status is set and that
1686  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1687  * taken and a warning is issued.
1688  *
1689  * Return: true if halt status is ok, false otherwise
1690  */
1691 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1692                                 struct dwc2_host_chan *chan, int chnum,
1693                                 struct dwc2_qtd *qtd)
1694 {
1695 #ifdef DEBUG
1696         u32 hcchar;
1697         u32 hctsiz;
1698         u32 hcintmsk;
1699         u32 hcsplt;
1700
1701         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1702                 /*
1703                  * This code is here only as a check. This condition should
1704                  * never happen. Ignore the halt if it does occur.
1705                  */
1706                 hcchar = readl(hsotg->regs + HCCHAR(chnum));
1707                 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1708                 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1709                 hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1710                 dev_dbg(hsotg->dev,
1711                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1712                          __func__);
1713                 dev_dbg(hsotg->dev,
1714                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1715                         chnum, hcchar, hctsiz);
1716                 dev_dbg(hsotg->dev,
1717                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1718                         chan->hcint, hcintmsk, hcsplt);
1719                 if (qtd)
1720                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1721                                 qtd->complete_split);
1722                 dev_warn(hsotg->dev,
1723                          "%s: no halt status, channel %d, ignoring interrupt\n",
1724                          __func__, chnum);
1725                 return false;
1726         }
1727
1728         /*
1729          * This code is here only as a check. hcchar.chdis should never be set
1730          * when the halt interrupt occurs. Halt the channel again if it does
1731          * occur.
1732          */
1733         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1734         if (hcchar & HCCHAR_CHDIS) {
1735                 dev_warn(hsotg->dev,
1736                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1737                          __func__, hcchar);
1738                 chan->halt_pending = 0;
1739                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1740                 return false;
1741         }
1742 #endif
1743
1744         return true;
1745 }
1746
1747 /*
1748  * Handles a host Channel Halted interrupt in DMA mode. This handler
1749  * determines the reason the channel halted and proceeds accordingly.
1750  */
1751 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1752                                     struct dwc2_host_chan *chan, int chnum,
1753                                     struct dwc2_qtd *qtd)
1754 {
1755         u32 hcintmsk;
1756         int out_nak_enh = 0;
1757
1758         if (dbg_hc(chan))
1759                 dev_vdbg(hsotg->dev,
1760                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1761                          chnum);
1762
1763         /*
1764          * For core with OUT NAK enhancement, the flow for high-speed
1765          * CONTROL/BULK OUT is handled a little differently
1766          */
1767         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1768                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1769                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1770                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1771                         out_nak_enh = 1;
1772                 }
1773         }
1774
1775         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1776             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1777              hsotg->core_params->dma_desc_enable <= 0)) {
1778                 if (hsotg->core_params->dma_desc_enable > 0)
1779                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1780                                                     chan->halt_status);
1781                 else
1782                         /*
1783                          * Just release the channel. A dequeue can happen on a
1784                          * transfer timeout. In the case of an AHB Error, the
1785                          * channel was forced to halt because there's no way to
1786                          * gracefully recover.
1787                          */
1788                         dwc2_release_channel(hsotg, chan, qtd,
1789                                              chan->halt_status);
1790                 return;
1791         }
1792
1793         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1794
1795         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1796                 /*
1797                  * Todo: This is here because of a possible hardware bug. Spec
1798                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1799                  * interrupt w/ACK bit set should occur, but I only see the
1800                  * XFERCOMP bit, even with it masked out. This is a workaround
1801                  * for that behavior. Should fix this when hardware is fixed.
1802                  */
1803                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1804                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1805                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1806         } else if (chan->hcint & HCINTMSK_STALL) {
1807                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1808         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1809                    hsotg->core_params->dma_desc_enable <= 0) {
1810                 if (out_nak_enh) {
1811                         if (chan->hcint &
1812                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1813                                 dev_vdbg(hsotg->dev,
1814                                          "XactErr with NYET/NAK/ACK\n");
1815                                 qtd->error_count = 0;
1816                         } else {
1817                                 dev_vdbg(hsotg->dev,
1818                                          "XactErr without NYET/NAK/ACK\n");
1819                         }
1820                 }
1821
1822                 /*
1823                  * Must handle xacterr before nak or ack. Could get a xacterr
1824                  * at the same time as either of these on a BULK/CONTROL OUT
1825                  * that started with a PING. The xacterr takes precedence.
1826                  */
1827                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1828         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1829                    hsotg->core_params->dma_desc_enable > 0) {
1830                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1831         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1832                    hsotg->core_params->dma_desc_enable > 0) {
1833                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1834         } else if (chan->hcint & HCINTMSK_BBLERR) {
1835                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1836         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1837                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1838         } else if (!out_nak_enh) {
1839                 if (chan->hcint & HCINTMSK_NYET) {
1840                         /*
1841                          * Must handle nyet before nak or ack. Could get a nyet
1842                          * at the same time as either of those on a BULK/CONTROL
1843                          * OUT that started with a PING. The nyet takes
1844                          * precedence.
1845                          */
1846                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1847                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1848                            !(hcintmsk & HCINTMSK_NAK)) {
1849                         /*
1850                          * If nak is not masked, it's because a non-split IN
1851                          * transfer is in an error state. In that case, the nak
1852                          * is handled by the nak interrupt handler, not here.
1853                          * Handle nak here for BULK/CONTROL OUT transfers, which
1854                          * halt on a NAK to allow rewinding the buffer pointer.
1855                          */
1856                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1857                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1858                            !(hcintmsk & HCINTMSK_ACK)) {
1859                         /*
1860                          * If ack is not masked, it's because a non-split IN
1861                          * transfer is in an error state. In that case, the ack
1862                          * is handled by the ack interrupt handler, not here.
1863                          * Handle ack here for split transfers. Start splits
1864                          * halt on ACK.
1865                          */
1866                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1867                 } else {
1868                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1869                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1870                                 /*
1871                                  * A periodic transfer halted with no other
1872                                  * channel interrupts set. Assume it was halted
1873                                  * by the core because it could not be completed
1874                                  * in its scheduled (micro)frame.
1875                                  */
1876                                 dev_dbg(hsotg->dev,
1877                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1878                                         __func__, chnum);
1879                                 dwc2_halt_channel(hsotg, chan, qtd,
1880                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1881                         } else {
1882                                 dev_err(hsotg->dev,
1883                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1884                                         __func__, chnum);
1885                                 dev_err(hsotg->dev,
1886                                         "hcint 0x%08x, intsts 0x%08x\n",
1887                                         chan->hcint,
1888                                         readl(hsotg->regs + GINTSTS));
1889                         }
1890                 }
1891         } else {
1892                 dev_info(hsotg->dev,
1893                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1894                          chan->hcint);
1895         }
1896 }
1897
1898 /*
1899  * Handles a host channel Channel Halted interrupt
1900  *
1901  * In slave mode, this handler is called only when the driver specifically
1902  * requests a halt. This occurs during handling other host channel interrupts
1903  * (e.g. nak, xacterr, stall, nyet, etc.).
1904  *
1905  * In DMA mode, this is the interrupt that occurs when the core has finished
1906  * processing a transfer on a channel. Other host channel interrupts (except
1907  * ahberr) are disabled in DMA mode.
1908  */
1909 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1910                                 struct dwc2_host_chan *chan, int chnum,
1911                                 struct dwc2_qtd *qtd)
1912 {
1913         if (dbg_hc(chan))
1914                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1915                          chnum);
1916
1917         if (hsotg->core_params->dma_enable > 0) {
1918                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1919         } else {
1920                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1921                         return;
1922                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1923         }
1924 }
1925
1926 /* Handles interrupt for a specific Host Channel */
1927 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1928 {
1929         struct dwc2_qtd *qtd;
1930         struct dwc2_host_chan *chan;
1931         u32 hcint, hcintmsk;
1932
1933         chan = hsotg->hc_ptr_array[chnum];
1934
1935         if (dbg_hc(chan))
1936                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
1937                          chnum);
1938
1939         hcint = readl(hsotg->regs + HCINT(chnum));
1940         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1941         if (dbg_hc(chan))
1942                 dev_vdbg(hsotg->dev,
1943                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1944                          hcint, hcintmsk, hcint & hcintmsk);
1945
1946         if (!chan) {
1947                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1948                 writel(hcint, hsotg->regs + HCINT(chnum));
1949                 return;
1950         }
1951
1952         writel(hcint, hsotg->regs + HCINT(chnum));
1953         chan->hcint = hcint;
1954         hcint &= hcintmsk;
1955
1956         /*
1957          * If the channel was halted due to a dequeue, the qtd list might
1958          * be empty or at least the first entry will not be the active qtd.
1959          * In this case, take a shortcut and just release the channel.
1960          */
1961         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
1962                 /*
1963                  * If the channel was halted, this should be the only
1964                  * interrupt unmasked
1965                  */
1966                 WARN_ON(hcint != HCINTMSK_CHHLTD);
1967                 if (hsotg->core_params->dma_desc_enable > 0)
1968                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1969                                                     chan->halt_status);
1970                 else
1971                         dwc2_release_channel(hsotg, chan, NULL,
1972                                              chan->halt_status);
1973                 return;
1974         }
1975
1976         if (list_empty(&chan->qh->qtd_list)) {
1977                 /*
1978                  * TODO: Will this ever happen with the
1979                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
1980                  */
1981                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
1982                         chnum);
1983                 dev_dbg(hsotg->dev,
1984                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1985                         chan->hcint, hcintmsk, hcint);
1986                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
1987                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
1988                 chan->hcint = 0;
1989                 return;
1990         }
1991
1992         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
1993                                qtd_list_entry);
1994
1995         if (hsotg->core_params->dma_enable <= 0) {
1996                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
1997                         hcint &= ~HCINTMSK_CHHLTD;
1998         }
1999
2000         if (hcint & HCINTMSK_XFERCOMPL) {
2001                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2002                 /*
2003                  * If NYET occurred at same time as Xfer Complete, the NYET is
2004                  * handled by the Xfer Complete interrupt handler. Don't want
2005                  * to call the NYET interrupt handler in this case.
2006                  */
2007                 hcint &= ~HCINTMSK_NYET;
2008         }
2009         if (hcint & HCINTMSK_CHHLTD)
2010                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2011         if (hcint & HCINTMSK_AHBERR)
2012                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2013         if (hcint & HCINTMSK_STALL)
2014                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2015         if (hcint & HCINTMSK_NAK)
2016                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2017         if (hcint & HCINTMSK_ACK)
2018                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2019         if (hcint & HCINTMSK_NYET)
2020                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2021         if (hcint & HCINTMSK_XACTERR)
2022                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2023         if (hcint & HCINTMSK_BBLERR)
2024                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2025         if (hcint & HCINTMSK_FRMOVRUN)
2026                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2027         if (hcint & HCINTMSK_DATATGLERR)
2028                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2029
2030         chan->hcint = 0;
2031 }
2032
2033 /*
2034  * This interrupt indicates that one or more host channels has a pending
2035  * interrupt. There are multiple conditions that can cause each host channel
2036  * interrupt. This function determines which conditions have occurred for each
2037  * host channel interrupt and handles them appropriately.
2038  */
2039 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2040 {
2041         u32 haint;
2042         int i;
2043
2044         haint = readl(hsotg->regs + HAINT);
2045         if (dbg_perio()) {
2046                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2047
2048                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2049         }
2050
2051         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2052                 if (haint & (1 << i))
2053                         dwc2_hc_n_intr(hsotg, i);
2054         }
2055 }
2056
2057 /* This function handles interrupts for the HCD */
2058 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2059 {
2060         u32 gintsts, dbg_gintsts;
2061         irqreturn_t retval = IRQ_NONE;
2062
2063         if (dwc2_check_core_status(hsotg) < 0) {
2064                 dev_warn(hsotg->dev, "Controller is disconnected\n");
2065                 return retval;
2066         }
2067
2068         spin_lock(&hsotg->lock);
2069
2070         /* Check if HOST Mode */
2071         if (dwc2_is_host_mode(hsotg)) {
2072                 gintsts = dwc2_read_core_intr(hsotg);
2073                 if (!gintsts) {
2074                         spin_unlock(&hsotg->lock);
2075                         return retval;
2076                 }
2077
2078                 retval = IRQ_HANDLED;
2079
2080                 dbg_gintsts = gintsts;
2081 #ifndef DEBUG_SOF
2082                 dbg_gintsts &= ~GINTSTS_SOF;
2083 #endif
2084                 if (!dbg_perio())
2085                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2086                                          GINTSTS_PTXFEMP);
2087
2088                 /* Only print if there are any non-suppressed interrupts left */
2089                 if (dbg_gintsts)
2090                         dev_vdbg(hsotg->dev,
2091                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2092                                  gintsts);
2093
2094                 if (gintsts & GINTSTS_SOF)
2095                         dwc2_sof_intr(hsotg);
2096                 if (gintsts & GINTSTS_RXFLVL)
2097                         dwc2_rx_fifo_level_intr(hsotg);
2098                 if (gintsts & GINTSTS_NPTXFEMP)
2099                         dwc2_np_tx_fifo_empty_intr(hsotg);
2100                 if (gintsts & GINTSTS_PRTINT)
2101                         dwc2_port_intr(hsotg);
2102                 if (gintsts & GINTSTS_HCHINT)
2103                         dwc2_hc_intr(hsotg);
2104                 if (gintsts & GINTSTS_PTXFEMP)
2105                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2106
2107                 if (dbg_gintsts) {
2108                         dev_vdbg(hsotg->dev,
2109                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2110                         dev_vdbg(hsotg->dev,
2111                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2112                                  readl(hsotg->regs + GINTSTS),
2113                                  readl(hsotg->regs + GINTMSK));
2114                 }
2115         }
2116
2117         spin_unlock(&hsotg->lock);
2118
2119         return retval;
2120 }