drivers/staging/rdma/hfi1/verbs.c

   1 /*
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2015 Intel Corporation.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * BSD LICENSE
  20  *
  21  * Copyright(c) 2015 Intel Corporation.
  22  *
  23  * Redistribution and use in source and binary forms, with or without
  24  * modification, are permitted provided that the following conditions
  25  * are met:
  26  *
  27  *  - Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions and the following disclaimer.
  29  *  - Redistributions in binary form must reproduce the above copyright
  30  *    notice, this list of conditions and the following disclaimer in
  31  *    the documentation and/or other materials provided with the
  32  *    distribution.
  33  *  - Neither the name of Intel Corporation nor the names of its
  34  *    contributors may be used to endorse or promote products derived
  35  *    from this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  */
  50
  51 #include <rdma/ib_mad.h>
  52 #include <rdma/ib_user_verbs.h>
  53 #include <linux/io.h>
  54 #include <linux/module.h>
  55 #include <linux/utsname.h>
  56 #include <linux/rculist.h>
  57 #include <linux/mm.h>
  58 #include <linux/random.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "hfi.h"
  62 #include "common.h"
  63 #include "device.h"
  64 #include "trace.h"
  65 #include "qp.h"
  66 #include "sdma.h"
  67
  68 unsigned int hfi1_lkey_table_size = 16;
  69 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  70                    S_IRUGO);
  71 MODULE_PARM_DESC(lkey_table_size,
  72                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  73
  74 static unsigned int hfi1_max_pds = 0xFFFF;
  75 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  76 MODULE_PARM_DESC(max_pds,
  77                  "Maximum number of protection domains to support");
  78
  79 static unsigned int hfi1_max_ahs = 0xFFFF;
  80 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  81 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  82
  83 unsigned int hfi1_max_cqes = 0x2FFFF;
  84 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  85 MODULE_PARM_DESC(max_cqes,
  86                  "Maximum number of completion queue entries to support");
  87
  88 unsigned int hfi1_max_cqs = 0x1FFFF;
  89 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  90 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  91
  92 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  93 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  94 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  95
  96 unsigned int hfi1_max_qps = 16384;
  97 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  98 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  99
 100 unsigned int hfi1_max_sges = 0x60;
 101 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
 102 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
 103
 104 unsigned int hfi1_max_mcast_grps = 16384;
 105 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 106 MODULE_PARM_DESC(max_mcast_grps,
 107                  "Maximum number of multicast groups to support");
 108
 109 unsigned int hfi1_max_mcast_qp_attached = 16;
 110 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 111                    uint, S_IRUGO);
 112 MODULE_PARM_DESC(max_mcast_qp_attached,
 113                  "Maximum number of attached QPs to support");
 114
 115 unsigned int hfi1_max_srqs = 1024;
 116 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 117 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 118
 119 unsigned int hfi1_max_srq_sges = 128;
 120 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 121 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 122
 123 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 124 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 125 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 126
 127 static void verbs_sdma_complete(
 128         struct sdma_txreq *cookie,
 129         int status,
 130         int drained);
 131
 132 /*
 133  * Note that it is OK to post send work requests in the SQE and ERR
 134  * states; hfi1_do_send() will process them and generate error
 135  * completions as per IB 1.2 C10-96.
 136  */
 137 const int ib_hfi1_state_ops[IB_QPS_ERR + 1] = {
 138         [IB_QPS_RESET] = 0,
 139         [IB_QPS_INIT] = HFI1_POST_RECV_OK,
 140         [IB_QPS_RTR] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK,
 141         [IB_QPS_RTS] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 142             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK |
 143             HFI1_PROCESS_NEXT_SEND_OK,
 144         [IB_QPS_SQD] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 145             HFI1_POST_SEND_OK | HFI1_PROCESS_SEND_OK,
 146         [IB_QPS_SQE] = HFI1_POST_RECV_OK | HFI1_PROCESS_RECV_OK |
 147             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 148         [IB_QPS_ERR] = HFI1_POST_RECV_OK | HFI1_FLUSH_RECV |
 149             HFI1_POST_SEND_OK | HFI1_FLUSH_SEND,
 150 };
 151
 152 struct hfi1_ucontext {
 153         struct ib_ucontext ibucontext;
 154 };
 155
 156 static inline struct hfi1_ucontext *to_iucontext(struct ib_ucontext
 157                                                   *ibucontext)
 158 {
 159         return container_of(ibucontext, struct hfi1_ucontext, ibucontext);
 160 }
 161
 162 /*
 163  * Translate ib_wr_opcode into ib_wc_opcode.
 164  */
 165 const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
 166         [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
 167         [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
 168         [IB_WR_SEND] = IB_WC_SEND,
 169         [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
 170         [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
 171         [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
 172         [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
 173 };
 174
 175 /*
 176  * Length of header by opcode, 0 --> not supported
 177  */
 178 const u8 hdr_len_by_opcode[256] = {
 179         /* RC */
 180         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 181         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 182         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 183         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 184         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 185         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 186         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 187         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 188         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 189         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 190         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 191         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 192         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 193         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 194         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 195         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 196         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 197         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 198         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4,
 199         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 200         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 201         /* UC */
 202         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 203         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 204         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 205         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 206         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 207         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 208         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 209         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 210         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 211         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 212         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 213         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 214         /* UD */
 215         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 216         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 217 };
 218
 219 static const opcode_handler opcode_handler_tbl[256] = {
 220         /* RC */
 221         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 222         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 223         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 224         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 225         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 226         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 227         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 228         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 229         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 230         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 231         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 232         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 233         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 234         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 235         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 236         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 237         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 238         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 239         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 240         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 241         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 242         /* UC */
 243         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 244         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 245         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 246         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 247         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 248         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 249         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 250         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 251         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 252         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 253         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 254         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 255         /* UD */
 256         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 257         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 258         /* CNP */
 259         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 260 };
 261
 262 /*
 263  * System image GUID.
 264  */
 265 __be64 ib_hfi1_sys_image_guid;
 266
 267 /**
 268  * hfi1_copy_sge - copy data to SGE memory
 269  * @ss: the SGE state
 270  * @data: the data to copy
 271  * @length: the length of the data
 272  */
 273 void hfi1_copy_sge(
 274         struct hfi1_sge_state *ss,
 275         void *data, u32 length,
 276         int release)
 277 {
 278         struct hfi1_sge *sge = &ss->sge;
 279
 280         while (length) {
 281                 u32 len = sge->length;
 282
 283                 if (len > length)
 284                         len = length;
 285                 if (len > sge->sge_length)
 286                         len = sge->sge_length;
 287                 WARN_ON_ONCE(len == 0);
 288                 memcpy(sge->vaddr, data, len);
 289                 sge->vaddr += len;
 290                 sge->length -= len;
 291                 sge->sge_length -= len;
 292                 if (sge->sge_length == 0) {
 293                         if (release)
 294                                 hfi1_put_mr(sge->mr);
 295                         if (--ss->num_sge)
 296                                 *sge = *ss->sg_list++;
 297                 } else if (sge->length == 0 && sge->mr->lkey) {
 298                         if (++sge->n >= HFI1_SEGSZ) {
 299                                 if (++sge->m >= sge->mr->mapsz)
 300                                         break;
 301                                 sge->n = 0;
 302                         }
 303                         sge->vaddr =
 304                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 305                         sge->length =
 306                                 sge->mr->map[sge->m]->segs[sge->n].length;
 307                 }
 308                 data += len;
 309                 length -= len;
 310         }
 311 }
 312
 313 /**
 314  * hfi1_skip_sge - skip over SGE memory
 315  * @ss: the SGE state
 316  * @length: the number of bytes to skip
 317  */
 318 void hfi1_skip_sge(struct hfi1_sge_state *ss, u32 length, int release)
 319 {
 320         struct hfi1_sge *sge = &ss->sge;
 321
 322         while (length) {
 323                 u32 len = sge->length;
 324
 325                 if (len > length)
 326                         len = length;
 327                 if (len > sge->sge_length)
 328                         len = sge->sge_length;
 329                 WARN_ON_ONCE(len == 0);
 330                 sge->vaddr += len;
 331                 sge->length -= len;
 332                 sge->sge_length -= len;
 333                 if (sge->sge_length == 0) {
 334                         if (release)
 335                                 hfi1_put_mr(sge->mr);
 336                         if (--ss->num_sge)
 337                                 *sge = *ss->sg_list++;
 338                 } else if (sge->length == 0 && sge->mr->lkey) {
 339                         if (++sge->n >= HFI1_SEGSZ) {
 340                                 if (++sge->m >= sge->mr->mapsz)
 341                                         break;
 342                                 sge->n = 0;
 343                         }
 344                         sge->vaddr =
 345                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 346                         sge->length =
 347                                 sge->mr->map[sge->m]->segs[sge->n].length;
 348                 }
 349                 length -= len;
 350         }
 351 }
 352
 353 /**
 354  * post_one_send - post one RC, UC, or UD send work request
 355  * @qp: the QP to post on
 356  * @wr: the work request to send
 357  */
 358 static int post_one_send(struct hfi1_qp *qp, struct ib_send_wr *wr)
 359 {
 360         struct hfi1_swqe *wqe;
 361         u32 next;
 362         int i;
 363         int j;
 364         int acc;
 365         struct hfi1_lkey_table *rkt;
 366         struct hfi1_pd *pd;
 367         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
 368         struct hfi1_pportdata *ppd;
 369         struct hfi1_ibport *ibp;
 370
 371         /* IB spec says that num_sge == 0 is OK. */
 372         if (unlikely(wr->num_sge > qp->s_max_sge))
 373                 return -EINVAL;
 374
 375         ppd = &dd->pport[qp->port_num - 1];
 376         ibp = &ppd->ibport_data;
 377
 378         /*
 379          * Don't allow RDMA reads or atomic operations on UC or
 380          * undefined operations.
 381          * Make sure buffer is large enough to hold the result for atomics.
 382          */
 383         if (qp->ibqp.qp_type == IB_QPT_UC) {
 384                 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
 385                         return -EINVAL;
 386         } else if (qp->ibqp.qp_type != IB_QPT_RC) {
 387                 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
 388                 if (wr->opcode != IB_WR_SEND &&
 389                     wr->opcode != IB_WR_SEND_WITH_IMM)
 390                         return -EINVAL;
 391                 /* Check UD destination address PD */
 392                 if (qp->ibqp.pd != ud_wr(wr)->ah->pd)
 393                         return -EINVAL;
 394         } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
 395                 return -EINVAL;
 396         else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
 397                    (wr->num_sge == 0 ||
 398                     wr->sg_list[0].length < sizeof(u64) ||
 399                     wr->sg_list[0].addr & (sizeof(u64) - 1)))
 400                 return -EINVAL;
 401         else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
 402                 return -EINVAL;
 403
 404         next = qp->s_head + 1;
 405         if (next >= qp->s_size)
 406                 next = 0;
 407         if (next == qp->s_last)
 408                 return -ENOMEM;
 409
 410         rkt = &to_idev(qp->ibqp.device)->lk_table;
 411         pd = to_ipd(qp->ibqp.pd);
 412         wqe = get_swqe_ptr(qp, qp->s_head);
 413
 414
 415         if (qp->ibqp.qp_type != IB_QPT_UC &&
 416             qp->ibqp.qp_type != IB_QPT_RC)
 417                 memcpy(&wqe->ud_wr, ud_wr(wr), sizeof(wqe->ud_wr));
 418         else if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM ||
 419                  wr->opcode == IB_WR_RDMA_WRITE ||
 420                  wr->opcode == IB_WR_RDMA_READ)
 421                 memcpy(&wqe->rdma_wr, rdma_wr(wr), sizeof(wqe->rdma_wr));
 422         else if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
 423                  wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
 424                 memcpy(&wqe->atomic_wr, atomic_wr(wr), sizeof(wqe->atomic_wr));
 425         else
 426                 memcpy(&wqe->wr, wr, sizeof(wqe->wr));
 427
 428         wqe->length = 0;
 429         j = 0;
 430         if (wr->num_sge) {
 431                 acc = wr->opcode >= IB_WR_RDMA_READ ?
 432                         IB_ACCESS_LOCAL_WRITE : 0;
 433                 for (i = 0; i < wr->num_sge; i++) {
 434                         u32 length = wr->sg_list[i].length;
 435                         int ok;
 436
 437                         if (length == 0)
 438                                 continue;
 439                         ok = hfi1_lkey_ok(rkt, pd, &wqe->sg_list[j],
 440                                           &wr->sg_list[i], acc);
 441                         if (!ok)
 442                                 goto bail_inval_free;
 443                         wqe->length += length;
 444                         j++;
 445                 }
 446                 wqe->wr.num_sge = j;
 447         }
 448         if (qp->ibqp.qp_type == IB_QPT_UC ||
 449             qp->ibqp.qp_type == IB_QPT_RC) {
 450                 if (wqe->length > 0x80000000U)
 451                         goto bail_inval_free;
 452         } else {
 453                 struct hfi1_ah *ah = to_iah(ud_wr(wr)->ah);
 454
 455                 atomic_inc(&ah->refcount);
 456         }
 457         wqe->ssn = qp->s_ssn++;
 458         qp->s_head = next;
 459
 460         return 0;
 461
 462 bail_inval_free:
 463         /* release mr holds */
 464         while (j) {
 465                 struct hfi1_sge *sge = &wqe->sg_list[--j];
 466
 467                 hfi1_put_mr(sge->mr);
 468         }
 469         return -EINVAL;
 470 }
 471
 472 /**
 473  * post_send - post a send on a QP
 474  * @ibqp: the QP to post the send on
 475  * @wr: the list of work requests to post
 476  * @bad_wr: the first bad WR is put here
 477  *
 478  * This may be called from interrupt context.
 479  */
 480 static int post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 481                      struct ib_send_wr **bad_wr)
 482 {
 483         struct hfi1_qp *qp = to_iqp(ibqp);
 484         int err = 0;
 485         int call_send;
 486         unsigned long flags;
 487         unsigned nreq = 0;
 488
 489         spin_lock_irqsave(&qp->s_lock, flags);
 490
 491         /* Check that state is OK to post send. */
 492         if (unlikely(!(ib_hfi1_state_ops[qp->state] & HFI1_POST_SEND_OK))) {
 493                 spin_unlock_irqrestore(&qp->s_lock, flags);
 494                 return -EINVAL;
 495         }
 496
 497         /* sq empty and not list -> call send */
 498         call_send = qp->s_head == qp->s_last && !wr->next;
 499
 500         for (; wr; wr = wr->next) {
 501                 err = post_one_send(qp, wr);
 502                 if (unlikely(err)) {
 503                         *bad_wr = wr;
 504                         goto bail;
 505                 }
 506                 nreq++;
 507         }
 508 bail:
 509         if (nreq && !call_send)
 510                 hfi1_schedule_send(qp);
 511         spin_unlock_irqrestore(&qp->s_lock, flags);
 512         if (nreq && call_send)
 513                 hfi1_do_send(&qp->s_iowait.iowork);
 514         return err;
 515 }
 516
 517 /**
 518  * post_receive - post a receive on a QP
 519  * @ibqp: the QP to post the receive on
 520  * @wr: the WR to post
 521  * @bad_wr: the first bad WR is put here
 522  *
 523  * This may be called from interrupt context.
 524  */
 525 static int post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 526                         struct ib_recv_wr **bad_wr)
 527 {
 528         struct hfi1_qp *qp = to_iqp(ibqp);
 529         struct hfi1_rwq *wq = qp->r_rq.wq;
 530         unsigned long flags;
 531         int ret;
 532
 533         /* Check that state is OK to post receive. */
 534         if (!(ib_hfi1_state_ops[qp->state] & HFI1_POST_RECV_OK) || !wq) {
 535                 *bad_wr = wr;
 536                 ret = -EINVAL;
 537                 goto bail;
 538         }
 539
 540         for (; wr; wr = wr->next) {
 541                 struct hfi1_rwqe *wqe;
 542                 u32 next;
 543                 int i;
 544
 545                 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
 546                         *bad_wr = wr;
 547                         ret = -EINVAL;
 548                         goto bail;
 549                 }
 550
 551                 spin_lock_irqsave(&qp->r_rq.lock, flags);
 552                 next = wq->head + 1;
 553                 if (next >= qp->r_rq.size)
 554                         next = 0;
 555                 if (next == wq->tail) {
 556                         spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 557                         *bad_wr = wr;
 558                         ret = -ENOMEM;
 559                         goto bail;
 560                 }
 561
 562                 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
 563                 wqe->wr_id = wr->wr_id;
 564                 wqe->num_sge = wr->num_sge;
 565                 for (i = 0; i < wr->num_sge; i++)
 566                         wqe->sg_list[i] = wr->sg_list[i];
 567                 /* Make sure queue entry is written before the head index. */
 568                 smp_wmb();
 569                 wq->head = next;
 570                 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
 571         }
 572         ret = 0;
 573
 574 bail:
 575         return ret;
 576 }
 577
 578 /*
 579  * Make sure the QP is ready and able to accept the given opcode.
 580  */
 581 static inline int qp_ok(int opcode, struct hfi1_packet *packet)
 582 {
 583         struct hfi1_ibport *ibp;
 584
 585         if (!(ib_hfi1_state_ops[packet->qp->state] & HFI1_PROCESS_RECV_OK))
 586                 goto dropit;
 587         if (((opcode & OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
 588             (opcode == IB_OPCODE_CNP))
 589                 return 1;
 590 dropit:
 591         ibp = &packet->rcd->ppd->ibport_data;
 592         ibp->n_pkt_drops++;
 593         return 0;
 594 }
 595
 596
 597 /**
 598  * hfi1_ib_rcv - process an incoming packet
 599  * @packet: data packet information
 600  *
 601  * This is called to process an incoming packet at interrupt level.
 602  *
 603  * Tlen is the length of the header + data + CRC in bytes.
 604  */
 605 void hfi1_ib_rcv(struct hfi1_packet *packet)
 606 {
 607         struct hfi1_ctxtdata *rcd = packet->rcd;
 608         struct hfi1_ib_header *hdr = packet->hdr;
 609         u32 tlen = packet->tlen;
 610         struct hfi1_pportdata *ppd = rcd->ppd;
 611         struct hfi1_ibport *ibp = &ppd->ibport_data;
 612         u32 qp_num;
 613         int lnh;
 614         u8 opcode;
 615         u16 lid;
 616
 617         /* Check for GRH */
 618         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 619         if (lnh == HFI1_LRH_BTH)
 620                 packet->ohdr = &hdr->u.oth;
 621         else if (lnh == HFI1_LRH_GRH) {
 622                 u32 vtf;
 623
 624                 packet->ohdr = &hdr->u.l.oth;
 625                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 626                         goto drop;
 627                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 628                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 629                         goto drop;
 630                 packet->rcv_flags |= HFI1_HAS_GRH;
 631         } else
 632                 goto drop;
 633
 634         trace_input_ibhdr(rcd->dd, hdr);
 635
 636         opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
 637         inc_opstats(tlen, &rcd->opstats->stats[opcode]);
 638
 639         /* Get the destination QP number. */
 640         qp_num = be32_to_cpu(packet->ohdr->bth[1]) & HFI1_QPN_MASK;
 641         lid = be16_to_cpu(hdr->lrh[1]);
 642         if (unlikely((lid >= HFI1_MULTICAST_LID_BASE) &&
 643             (lid != HFI1_PERMISSIVE_LID))) {
 644                 struct hfi1_mcast *mcast;
 645                 struct hfi1_mcast_qp *p;
 646
 647                 if (lnh != HFI1_LRH_GRH)
 648                         goto drop;
 649                 mcast = hfi1_mcast_find(ibp, &hdr->u.l.grh.dgid);
 650                 if (mcast == NULL)
 651                         goto drop;
 652                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 653                         packet->qp = p->qp;
 654                         spin_lock(&packet->qp->r_lock);
 655                         if (likely((qp_ok(opcode, packet))))
 656                                 opcode_handler_tbl[opcode](packet);
 657                         spin_unlock(&packet->qp->r_lock);
 658                 }
 659                 /*
 660                  * Notify hfi1_multicast_detach() if it is waiting for us
 661                  * to finish.
 662                  */
 663                 if (atomic_dec_return(&mcast->refcount) <= 1)
 664                         wake_up(&mcast->wait);
 665         } else {
 666                 rcu_read_lock();
 667                 packet->qp = hfi1_lookup_qpn(ibp, qp_num);
 668                 if (!packet->qp) {
 669                         rcu_read_unlock();
 670                         goto drop;
 671                 }
 672                 spin_lock(&packet->qp->r_lock);
 673                 if (likely((qp_ok(opcode, packet))))
 674                         opcode_handler_tbl[opcode](packet);
 675                 spin_unlock(&packet->qp->r_lock);
 676                 rcu_read_unlock();
 677         }
 678         return;
 679
 680 drop:
 681         ibp->n_pkt_drops++;
 682 }
 683
 684 /*
 685  * This is called from a timer to check for QPs
 686  * which need kernel memory in order to send a packet.
 687  */
 688 static void mem_timer(unsigned long data)
 689 {
 690         struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
 691         struct list_head *list = &dev->memwait;
 692         struct hfi1_qp *qp = NULL;
 693         struct iowait *wait;
 694         unsigned long flags;
 695
 696         write_seqlock_irqsave(&dev->iowait_lock, flags);
 697         if (!list_empty(list)) {
 698                 wait = list_first_entry(list, struct iowait, list);
 699                 qp = container_of(wait, struct hfi1_qp, s_iowait);
 700                 list_del_init(&qp->s_iowait.list);
 701                 /* refcount held until actual wake up */
 702                 if (!list_empty(list))
 703                         mod_timer(&dev->mem_timer, jiffies + 1);
 704         }
 705         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 706
 707         if (qp)
 708                 hfi1_qp_wakeup(qp, HFI1_S_WAIT_KMEM);
 709 }
 710
 711 void update_sge(struct hfi1_sge_state *ss, u32 length)
 712 {
 713         struct hfi1_sge *sge = &ss->sge;
 714
 715         sge->vaddr += length;
 716         sge->length -= length;
 717         sge->sge_length -= length;
 718         if (sge->sge_length == 0) {
 719                 if (--ss->num_sge)
 720                         *sge = *ss->sg_list++;
 721         } else if (sge->length == 0 && sge->mr->lkey) {
 722                 if (++sge->n >= HFI1_SEGSZ) {
 723                         if (++sge->m >= sge->mr->mapsz)
 724                                 return;
 725                         sge->n = 0;
 726                 }
 727                 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
 728                 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
 729         }
 730 }
 731
 732 static noinline struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
 733                                                 struct hfi1_qp *qp)
 734 {
 735         struct verbs_txreq *tx;
 736         unsigned long flags;
 737
 738         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 739         if (!tx) {
 740                 spin_lock_irqsave(&qp->s_lock, flags);
 741                 write_seqlock(&dev->iowait_lock);
 742                 if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK &&
 743                     list_empty(&qp->s_iowait.list)) {
 744                         dev->n_txwait++;
 745                         qp->s_flags |= HFI1_S_WAIT_TX;
 746                         list_add_tail(&qp->s_iowait.list, &dev->txwait);
 747                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_TX);
 748                         atomic_inc(&qp->refcount);
 749                 }
 750                 qp->s_flags &= ~HFI1_S_BUSY;
 751                 write_sequnlock(&dev->iowait_lock);
 752                 spin_unlock_irqrestore(&qp->s_lock, flags);
 753                 tx = ERR_PTR(-EBUSY);
 754         }
 755         return tx;
 756 }
 757
 758 static inline struct verbs_txreq *get_txreq(struct hfi1_ibdev *dev,
 759                                             struct hfi1_qp *qp)
 760 {
 761         struct verbs_txreq *tx;
 762
 763         tx = kmem_cache_alloc(dev->verbs_txreq_cache, GFP_ATOMIC);
 764         if (!tx) {
 765                 /* call slow path to get the lock */
 766                 tx =  __get_txreq(dev, qp);
 767                 if (IS_ERR(tx))
 768                         return tx;
 769         }
 770         tx->qp = qp;
 771         return tx;
 772 }
 773
 774 void hfi1_put_txreq(struct verbs_txreq *tx)
 775 {
 776         struct hfi1_ibdev *dev;
 777         struct hfi1_qp *qp;
 778         unsigned long flags;
 779         unsigned int seq;
 780
 781         qp = tx->qp;
 782         dev = to_idev(qp->ibqp.device);
 783
 784         if (tx->mr) {
 785                 hfi1_put_mr(tx->mr);
 786                 tx->mr = NULL;
 787         }
 788         sdma_txclean(dd_from_dev(dev), &tx->txreq);
 789
 790         /* Free verbs_txreq and return to slab cache */
 791         kmem_cache_free(dev->verbs_txreq_cache, tx);
 792
 793         do {
 794                 seq = read_seqbegin(&dev->iowait_lock);
 795                 if (!list_empty(&dev->txwait)) {
 796                         struct iowait *wait;
 797
 798                         write_seqlock_irqsave(&dev->iowait_lock, flags);
 799                         /* Wake up first QP wanting a free struct */
 800                         wait = list_first_entry(&dev->txwait, struct iowait,
 801                                                 list);
 802                         qp = container_of(wait, struct hfi1_qp, s_iowait);
 803                         list_del_init(&qp->s_iowait.list);
 804                         /* refcount held until actual wake up */
 805                         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 806                         hfi1_qp_wakeup(qp, HFI1_S_WAIT_TX);
 807                         break;
 808                 }
 809         } while (read_seqretry(&dev->iowait_lock, seq));
 810 }
 811
 812 /*
 813  * This is called with progress side lock held.
 814  */
 815 /* New API */
 816 static void verbs_sdma_complete(
 817         struct sdma_txreq *cookie,
 818         int status,
 819         int drained)
 820 {
 821         struct verbs_txreq *tx =
 822                 container_of(cookie, struct verbs_txreq, txreq);
 823         struct hfi1_qp *qp = tx->qp;
 824
 825         spin_lock(&qp->s_lock);
 826         if (tx->wqe)
 827                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 828         else if (qp->ibqp.qp_type == IB_QPT_RC) {
 829                 struct hfi1_ib_header *hdr;
 830
 831                 hdr = &tx->phdr.hdr;
 832                 hfi1_rc_send_complete(qp, hdr);
 833         }
 834         if (drained) {
 835                 /*
 836                  * This happens when the send engine notes
 837                  * a QP in the error state and cannot
 838                  * do the flush work until that QP's
 839                  * sdma work has finished.
 840                  */
 841                 if (qp->s_flags & HFI1_S_WAIT_DMA) {
 842                         qp->s_flags &= ~HFI1_S_WAIT_DMA;
 843                         hfi1_schedule_send(qp);
 844                 }
 845         }
 846         spin_unlock(&qp->s_lock);
 847
 848         hfi1_put_txreq(tx);
 849 }
 850
 851 static int wait_kmem(struct hfi1_ibdev *dev, struct hfi1_qp *qp)
 852 {
 853         unsigned long flags;
 854         int ret = 0;
 855
 856         spin_lock_irqsave(&qp->s_lock, flags);
 857         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
 858                 write_seqlock(&dev->iowait_lock);
 859                 if (list_empty(&qp->s_iowait.list)) {
 860                         if (list_empty(&dev->memwait))
 861                                 mod_timer(&dev->mem_timer, jiffies + 1);
 862                         qp->s_flags |= HFI1_S_WAIT_KMEM;
 863                         list_add_tail(&qp->s_iowait.list, &dev->memwait);
 864                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_KMEM);
 865                         atomic_inc(&qp->refcount);
 866                 }
 867                 write_sequnlock(&dev->iowait_lock);
 868                 qp->s_flags &= ~HFI1_S_BUSY;
 869                 ret = -EBUSY;
 870         }
 871         spin_unlock_irqrestore(&qp->s_lock, flags);
 872
 873         return ret;
 874 }
 875
 876 /*
 877  * This routine calls txadds for each sg entry.
 878  *
 879  * Add failures will revert the sge cursor
 880  */
 881 static int build_verbs_ulp_payload(
 882         struct sdma_engine *sde,
 883         struct hfi1_sge_state *ss,
 884         u32 length,
 885         struct verbs_txreq *tx)
 886 {
 887         struct hfi1_sge *sg_list = ss->sg_list;
 888         struct hfi1_sge sge = ss->sge;
 889         u8 num_sge = ss->num_sge;
 890         u32 len;
 891         int ret = 0;
 892
 893         while (length) {
 894                 len = ss->sge.length;
 895                 if (len > length)
 896                         len = length;
 897                 if (len > ss->sge.sge_length)
 898                         len = ss->sge.sge_length;
 899                 WARN_ON_ONCE(len == 0);
 900                 ret = sdma_txadd_kvaddr(
 901                         sde->dd,
 902                         &tx->txreq,
 903                         ss->sge.vaddr,
 904                         len);
 905                 if (ret)
 906                         goto bail_txadd;
 907                 update_sge(ss, len);
 908                 length -= len;
 909         }
 910         return ret;
 911 bail_txadd:
 912         /* unwind cursor */
 913         ss->sge = sge;
 914         ss->num_sge = num_sge;
 915         ss->sg_list = sg_list;
 916         return ret;
 917 }
 918
 919 /*
 920  * Build the number of DMA descriptors needed to send length bytes of data.
 921  *
 922  * NOTE: DMA mapping is held in the tx until completed in the ring or
 923  *       the tx desc is freed without having been submitted to the ring
 924  *
 925  * This routine insures the following all the helper routine
 926  * calls succeed.
 927  */
 928 /* New API */
 929 static int build_verbs_tx_desc(
 930         struct sdma_engine *sde,
 931         struct hfi1_sge_state *ss,
 932         u32 length,
 933         struct verbs_txreq *tx,
 934         struct ahg_ib_header *ahdr,
 935         u64 pbc)
 936 {
 937         int ret = 0;
 938         struct hfi1_pio_header *phdr;
 939         u16 hdrbytes = tx->hdr_dwords << 2;
 940
 941         phdr = &tx->phdr;
 942         if (!ahdr->ahgcount) {
 943                 ret = sdma_txinit_ahg(
 944                         &tx->txreq,
 945                         ahdr->tx_flags,
 946                         hdrbytes + length,
 947                         ahdr->ahgidx,
 948                         0,
 949                         NULL,
 950                         0,
 951                         verbs_sdma_complete);
 952                 if (ret)
 953                         goto bail_txadd;
 954                 phdr->pbc = cpu_to_le64(pbc);
 955                 memcpy(&phdr->hdr, &ahdr->ibh, hdrbytes - sizeof(phdr->pbc));
 956                 /* add the header */
 957                 ret = sdma_txadd_kvaddr(
 958                         sde->dd,
 959                         &tx->txreq,
 960                         &tx->phdr,
 961                         tx->hdr_dwords << 2);
 962                 if (ret)
 963                         goto bail_txadd;
 964         } else {
 965                 struct hfi1_other_headers *sohdr = &ahdr->ibh.u.oth;
 966                 struct hfi1_other_headers *dohdr = &phdr->hdr.u.oth;
 967
 968                 /* needed in rc_send_complete() */
 969                 phdr->hdr.lrh[0] = ahdr->ibh.lrh[0];
 970                 if ((be16_to_cpu(phdr->hdr.lrh[0]) & 3) == HFI1_LRH_GRH) {
 971                         sohdr = &ahdr->ibh.u.l.oth;
 972                         dohdr = &phdr->hdr.u.l.oth;
 973                 }
 974                 /* opcode */
 975                 dohdr->bth[0] = sohdr->bth[0];
 976                 /* PSN/ACK  */
 977                 dohdr->bth[2] = sohdr->bth[2];
 978                 ret = sdma_txinit_ahg(
 979                         &tx->txreq,
 980                         ahdr->tx_flags,
 981                         length,
 982                         ahdr->ahgidx,
 983                         ahdr->ahgcount,
 984                         ahdr->ahgdesc,
 985                         hdrbytes,
 986                         verbs_sdma_complete);
 987                 if (ret)
 988                         goto bail_txadd;
 989         }
 990
 991         /* add the ulp payload - if any.  ss can be NULL for acks */
 992         if (ss)
 993                 ret = build_verbs_ulp_payload(sde, ss, length, tx);
 994 bail_txadd:
 995         return ret;
 996 }
 997
 998 int hfi1_verbs_send_dma(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
 999                         u32 hdrwords, struct hfi1_sge_state *ss, u32 len,
1000                         u32 plen, u32 dwords, u64 pbc)
1001 {
1002         struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
1003         struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1004         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1005         struct verbs_txreq *tx;
1006         struct sdma_txreq *stx;
1007         u64 pbc_flags = 0;
1008         struct sdma_engine *sde;
1009         u8 sc5 = qp->s_sc;
1010         int ret;
1011
1012         if (!list_empty(&qp->s_iowait.tx_head)) {
1013                 stx = list_first_entry(
1014                         &qp->s_iowait.tx_head,
1015                         struct sdma_txreq,
1016                         list);
1017                 list_del_init(&stx->list);
1018                 tx = container_of(stx, struct verbs_txreq, txreq);
1019                 ret = sdma_send_txreq(tx->sde, &qp->s_iowait, stx);
1020                 if (unlikely(ret == -ECOMM))
1021                         goto bail_ecomm;
1022                 return ret;
1023         }
1024
1025         tx = get_txreq(dev, qp);
1026         if (IS_ERR(tx))
1027                 goto bail_tx;
1028
1029         if (!qp->s_hdr->sde) {
1030                 tx->sde = sde = qp_to_sdma_engine(qp, sc5);
1031                 if (!sde)
1032                         goto bail_no_sde;
1033         } else
1034                 tx->sde = sde = qp->s_hdr->sde;
1035
1036         if (likely(pbc == 0)) {
1037                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1038                 /* No vl15 here */
1039                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1040                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1041
1042                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1043         }
1044         tx->wqe = qp->s_wqe;
1045         tx->mr = qp->s_rdma_mr;
1046         if (qp->s_rdma_mr)
1047                 qp->s_rdma_mr = NULL;
1048         tx->hdr_dwords = hdrwords + 2;
1049         ret = build_verbs_tx_desc(sde, ss, len, tx, ahdr, pbc);
1050         if (unlikely(ret))
1051                 goto bail_build;
1052         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1053         ret =  sdma_send_txreq(sde, &qp->s_iowait, &tx->txreq);
1054         if (unlikely(ret == -ECOMM))
1055                 goto bail_ecomm;
1056         return ret;
1057
1058 bail_no_sde:
1059         hfi1_put_txreq(tx);
1060 bail_ecomm:
1061         /* The current one got "sent" */
1062         return 0;
1063 bail_build:
1064         /* kmalloc or mapping fail */
1065         hfi1_put_txreq(tx);
1066         return wait_kmem(dev, qp);
1067 bail_tx:
1068         return PTR_ERR(tx);
1069 }
1070
1071 /*
1072  * If we are now in the error state, return zero to flush the
1073  * send work request.
1074  */
1075 static int no_bufs_available(struct hfi1_qp *qp, struct send_context *sc)
1076 {
1077         struct hfi1_devdata *dd = sc->dd;
1078         struct hfi1_ibdev *dev = &dd->verbs_dev;
1079         unsigned long flags;
1080         int ret = 0;
1081
1082         /*
1083          * Note that as soon as want_buffer() is called and
1084          * possibly before it returns, sc_piobufavail()
1085          * could be called. Therefore, put QP on the I/O wait list before
1086          * enabling the PIO avail interrupt.
1087          */
1088         spin_lock_irqsave(&qp->s_lock, flags);
1089         if (ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) {
1090                 write_seqlock(&dev->iowait_lock);
1091                 if (list_empty(&qp->s_iowait.list)) {
1092                         struct hfi1_ibdev *dev = &dd->verbs_dev;
1093                         int was_empty;
1094
1095                         dev->n_piowait++;
1096                         qp->s_flags |= HFI1_S_WAIT_PIO;
1097                         was_empty = list_empty(&sc->piowait);
1098                         list_add_tail(&qp->s_iowait.list, &sc->piowait);
1099                         trace_hfi1_qpsleep(qp, HFI1_S_WAIT_PIO);
1100                         atomic_inc(&qp->refcount);
1101                         /* counting: only call wantpiobuf_intr if first user */
1102                         if (was_empty)
1103                                 hfi1_sc_wantpiobuf_intr(sc, 1);
1104                 }
1105                 write_sequnlock(&dev->iowait_lock);
1106                 qp->s_flags &= ~HFI1_S_BUSY;
1107                 ret = -EBUSY;
1108         }
1109         spin_unlock_irqrestore(&qp->s_lock, flags);
1110         return ret;
1111 }
1112
1113 struct send_context *qp_to_send_context(struct hfi1_qp *qp, u8 sc5)
1114 {
1115         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1116         struct hfi1_pportdata *ppd = dd->pport + (qp->port_num - 1);
1117         u8 vl;
1118
1119         vl = sc_to_vlt(dd, sc5);
1120         if (vl >= ppd->vls_supported && vl != 15)
1121                 return NULL;
1122         return dd->vld[vl].sc;
1123 }
1124
1125 int hfi1_verbs_send_pio(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
1126                         u32 hdrwords, struct hfi1_sge_state *ss, u32 len,
1127                         u32 plen, u32 dwords, u64 pbc)
1128 {
1129         struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1130         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1131         u32 *hdr = (u32 *)&ahdr->ibh;
1132         u64 pbc_flags = 0;
1133         u32 sc5;
1134         unsigned long flags = 0;
1135         struct send_context *sc;
1136         struct pio_buf *pbuf;
1137         int wc_status = IB_WC_SUCCESS;
1138
1139         /* vl15 special case taken care of in ud.c */
1140         sc5 = qp->s_sc;
1141         sc = qp_to_send_context(qp, sc5);
1142
1143         if (!sc)
1144                 return -EINVAL;
1145         if (likely(pbc == 0)) {
1146                 u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1147                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1148                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1149                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1150         }
1151         pbuf = sc_buffer_alloc(sc, plen, NULL, NULL);
1152         if (unlikely(pbuf == NULL)) {
1153                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1154                         /*
1155                          * If we have filled the PIO buffers to capacity and are
1156                          * not in an active state this request is not going to
1157                          * go out to so just complete it with an error or else a
1158                          * ULP or the core may be stuck waiting.
1159                          */
1160                         hfi1_cdbg(
1161                                 PIO,
1162                                 "alloc failed. state not active, completing");
1163                         wc_status = IB_WC_GENERAL_ERR;
1164                         goto pio_bail;
1165                 } else {
1166                         /*
1167                          * This is a normal occurrence. The PIO buffs are full
1168                          * up but we are still happily sending, well we could be
1169                          * so lets continue to queue the request.
1170                          */
1171                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1172                         return no_bufs_available(qp, sc);
1173                 }
1174         }
1175
1176         if (len == 0) {
1177                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1178         } else {
1179                 if (ss) {
1180                         seg_pio_copy_start(pbuf, pbc, hdr, hdrwords*4);
1181                         while (len) {
1182                                 void *addr = ss->sge.vaddr;
1183                                 u32 slen = ss->sge.length;
1184
1185                                 if (slen > len)
1186                                         slen = len;
1187                                 update_sge(ss, slen);
1188                                 seg_pio_copy_mid(pbuf, addr, slen);
1189                                 len -= slen;
1190                         }
1191                         seg_pio_copy_end(pbuf);
1192                 }
1193         }
1194
1195         trace_output_ibhdr(dd_from_ibdev(qp->ibqp.device), &ahdr->ibh);
1196
1197         if (qp->s_rdma_mr) {
1198                 hfi1_put_mr(qp->s_rdma_mr);
1199                 qp->s_rdma_mr = NULL;
1200         }
1201
1202 pio_bail:
1203         if (qp->s_wqe) {
1204                 spin_lock_irqsave(&qp->s_lock, flags);
1205                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1206                 spin_unlock_irqrestore(&qp->s_lock, flags);
1207         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1208                 spin_lock_irqsave(&qp->s_lock, flags);
1209                 hfi1_rc_send_complete(qp, &ahdr->ibh);
1210                 spin_unlock_irqrestore(&qp->s_lock, flags);
1211         }
1212         return 0;
1213 }
1214 /*
1215  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1216  * being an entry from the ingress partition key table), return 0
1217  * otherwise. Use the matching criteria for egress partition keys
1218  * specified in the OPAv1 spec., section 9.1l.7.
1219  */
1220 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1221 {
1222         u16 mkey = pkey & PKEY_LOW_15_MASK;
1223         u16 ment = ent & PKEY_LOW_15_MASK;
1224
1225         if (mkey == ment) {
1226                 /*
1227                  * If pkey[15] is set (full partition member),
1228                  * is bit 15 in the corresponding table element
1229                  * clear (limited member)?
1230                  */
1231                 if (pkey & PKEY_MEMBER_MASK)
1232                         return !!(ent & PKEY_MEMBER_MASK);
1233                 return 1;
1234         }
1235         return 0;
1236 }
1237
1238 /*
1239  * egress_pkey_check - return 0 if hdr's pkey matches according to the
1240  * criteria in the OPAv1 spec., section 9.11.7.
1241  */
1242 static inline int egress_pkey_check(struct hfi1_pportdata *ppd,
1243                                     struct hfi1_ib_header *hdr,
1244                                     struct hfi1_qp *qp)
1245 {
1246         struct hfi1_other_headers *ohdr;
1247         struct hfi1_devdata *dd;
1248         int i = 0;
1249         u16 pkey;
1250         u8 lnh, sc5 = qp->s_sc;
1251
1252         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1253                 return 0;
1254
1255         /* locate the pkey within the headers */
1256         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1257         if (lnh == HFI1_LRH_GRH)
1258                 ohdr = &hdr->u.l.oth;
1259         else
1260                 ohdr = &hdr->u.oth;
1261
1262         pkey = (u16)be32_to_cpu(ohdr->bth[0]);
1263
1264         /* If SC15, pkey[0:14] must be 0x7fff */
1265         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1266                 goto bad;
1267
1268
1269         /* Is the pkey = 0x0, or 0x8000? */
1270         if ((pkey & PKEY_LOW_15_MASK) == 0)
1271                 goto bad;
1272
1273         /* The most likely matching pkey has index qp->s_pkey_index */
1274         if (unlikely(!egress_pkey_matches_entry(pkey,
1275                                         ppd->pkeys[qp->s_pkey_index]))) {
1276                 /* no match - try the entire table */
1277                 for (; i < MAX_PKEY_VALUES; i++) {
1278                         if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1279                                 break;
1280                 }
1281         }
1282
1283         if (i < MAX_PKEY_VALUES)
1284                 return 0;
1285 bad:
1286         incr_cntr64(&ppd->port_xmit_constraint_errors);
1287         dd = ppd->dd;
1288         if (!(dd->err_info_xmit_constraint.status & OPA_EI_STATUS_SMASK)) {
1289                 u16 slid = be16_to_cpu(hdr->lrh[3]);
1290
1291                 dd->err_info_xmit_constraint.status |= OPA_EI_STATUS_SMASK;
1292                 dd->err_info_xmit_constraint.slid = slid;
1293                 dd->err_info_xmit_constraint.pkey = pkey;
1294         }
1295         return 1;
1296 }
1297
1298 /**
1299  * hfi1_verbs_send - send a packet
1300  * @qp: the QP to send on
1301  * @ahdr: the packet header
1302  * @hdrwords: the number of 32-bit words in the header
1303  * @ss: the SGE to send
1304  * @len: the length of the packet in bytes
1305  *
1306  * Return zero if packet is sent or queued OK.
1307  * Return non-zero and clear qp->s_flags HFI1_S_BUSY otherwise.
1308  */
1309 int hfi1_verbs_send(struct hfi1_qp *qp, struct ahg_ib_header *ahdr,
1310                     u32 hdrwords, struct hfi1_sge_state *ss, u32 len)
1311 {
1312         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1313         u32 plen;
1314         int ret;
1315         int pio = 0;
1316         unsigned long flags = 0;
1317         u32 dwords = (len + 3) >> 2;
1318
1319         /*
1320          * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1321          * can defer SDMA restart until link goes ACTIVE without
1322          * worrying about just how we got there.
1323          */
1324         if ((qp->ibqp.qp_type == IB_QPT_SMI) ||
1325             !(dd->flags & HFI1_HAS_SEND_DMA))
1326                 pio = 1;
1327
1328         ret = egress_pkey_check(dd->pport, &ahdr->ibh, qp);
1329         if (unlikely(ret)) {
1330                 /*
1331                  * The value we are returning here does not get propagated to
1332                  * the verbs caller. Thus we need to complete the request with
1333                  * error otherwise the caller could be sitting waiting on the
1334                  * completion event. Only do this for PIO. SDMA has its own
1335                  * mechanism for handling the errors. So for SDMA we can just
1336                  * return.
1337                  */
1338                 if (pio) {
1339                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1340                                   __func__);
1341                         spin_lock_irqsave(&qp->s_lock, flags);
1342                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1343                         spin_unlock_irqrestore(&qp->s_lock, flags);
1344                 }
1345                 return -EINVAL;
1346         }
1347
1348         /*
1349          * Calculate the send buffer trigger address.
1350          * The +2 counts for the pbc control qword
1351          */
1352         plen = hdrwords + dwords + 2;
1353
1354         if (pio) {
1355                 ret = dd->process_pio_send(
1356                         qp, ahdr, hdrwords, ss, len, plen, dwords, 0);
1357         } else {
1358 #ifdef CONFIG_SDMA_VERBOSITY
1359                 dd_dev_err(dd, "CONFIG SDMA %s:%d %s()\n",
1360                            slashstrip(__FILE__), __LINE__, __func__);
1361                 dd_dev_err(dd, "SDMA hdrwords = %u, len = %u\n", hdrwords, len);
1362 #endif
1363                 ret = dd->process_dma_send(
1364                         qp, ahdr, hdrwords, ss, len, plen, dwords, 0);
1365         }
1366
1367         return ret;
1368 }
1369
1370 static int query_device(struct ib_device *ibdev,
1371                         struct ib_device_attr *props,
1372                         struct ib_udata *uhw)
1373 {
1374         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1375         struct hfi1_ibdev *dev = to_idev(ibdev);
1376
1377         if (uhw->inlen || uhw->outlen)
1378                 return -EINVAL;
1379         memset(props, 0, sizeof(*props));
1380
1381         props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1382                 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1383                 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1384                 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1385
1386         props->page_size_cap = PAGE_SIZE;
1387         props->vendor_id =
1388                 dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1389         props->vendor_part_id = dd->pcidev->device;
1390         props->hw_ver = dd->minrev;
1391         props->sys_image_guid = ib_hfi1_sys_image_guid;
1392         props->max_mr_size = ~0ULL;
1393         props->max_qp = hfi1_max_qps;
1394         props->max_qp_wr = hfi1_max_qp_wrs;
1395         props->max_sge = hfi1_max_sges;
1396         props->max_sge_rd = hfi1_max_sges;
1397         props->max_cq = hfi1_max_cqs;
1398         props->max_ah = hfi1_max_ahs;
1399         props->max_cqe = hfi1_max_cqes;
1400         props->max_mr = dev->lk_table.max;
1401         props->max_fmr = dev->lk_table.max;
1402         props->max_map_per_fmr = 32767;
1403         props->max_pd = hfi1_max_pds;
1404         props->max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1405         props->max_qp_init_rd_atom = 255;
1406         /* props->max_res_rd_atom */
1407         props->max_srq = hfi1_max_srqs;
1408         props->max_srq_wr = hfi1_max_srq_wrs;
1409         props->max_srq_sge = hfi1_max_srq_sges;
1410         /* props->local_ca_ack_delay */
1411         props->atomic_cap = IB_ATOMIC_GLOB;
1412         props->max_pkeys = hfi1_get_npkeys(dd);
1413         props->max_mcast_grp = hfi1_max_mcast_grps;
1414         props->max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1415         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1416                 props->max_mcast_grp;
1417
1418         return 0;
1419 }
1420
1421 static inline u16 opa_speed_to_ib(u16 in)
1422 {
1423         u16 out = 0;
1424
1425         if (in & OPA_LINK_SPEED_25G)
1426                 out |= IB_SPEED_EDR;
1427         if (in & OPA_LINK_SPEED_12_5G)
1428                 out |= IB_SPEED_FDR;
1429
1430         return out;
1431 }
1432
1433 /*
1434  * Convert a single OPA link width (no multiple flags) to an IB value.
1435  * A zero OPA link width means link down, which means the IB width value
1436  * is a don't care.
1437  */
1438 static inline u16 opa_width_to_ib(u16 in)
1439 {
1440         switch (in) {
1441         case OPA_LINK_WIDTH_1X:
1442         /* map 2x and 3x to 1x as they don't exist in IB */
1443         case OPA_LINK_WIDTH_2X:
1444         case OPA_LINK_WIDTH_3X:
1445                 return IB_WIDTH_1X;
1446         default: /* link down or unknown, return our largest width */
1447         case OPA_LINK_WIDTH_4X:
1448                 return IB_WIDTH_4X;
1449         }
1450 }
1451
1452 static int query_port(struct ib_device *ibdev, u8 port,
1453                       struct ib_port_attr *props)
1454 {
1455         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1456         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1457         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1458         u16 lid = ppd->lid;
1459
1460         memset(props, 0, sizeof(*props));
1461         props->lid = lid ? lid : 0;
1462         props->lmc = ppd->lmc;
1463         props->sm_lid = ibp->sm_lid;
1464         props->sm_sl = ibp->sm_sl;
1465         /* OPA logical states match IB logical states */
1466         props->state = driver_lstate(ppd);
1467         props->phys_state = hfi1_ibphys_portstate(ppd);
1468         props->port_cap_flags = ibp->port_cap_flags;
1469         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1470         props->max_msg_sz = 0x80000000;
1471         props->pkey_tbl_len = hfi1_get_npkeys(dd);
1472         props->bad_pkey_cntr = ibp->pkey_violations;
1473         props->qkey_viol_cntr = ibp->qkey_violations;
1474         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1475         /* see rate_show() in ib core/sysfs.c */
1476         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1477         props->max_vl_num = ppd->vls_supported;
1478         props->init_type_reply = 0;
1479
1480         /* Once we are a "first class" citizen and have added the OPA MTUs to
1481          * the core we can advertise the larger MTU enum to the ULPs, for now
1482          * advertise only 4K.
1483          *
1484          * Those applications which are either OPA aware or pass the MTU enum
1485          * from the Path Records to us will get the new 8k MTU.  Those that
1486          * attempt to process the MTU enum may fail in various ways.
1487          */
1488         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1489                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1490         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1491                 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1492         props->subnet_timeout = ibp->subnet_timeout;
1493
1494         return 0;
1495 }
1496
1497 static int port_immutable(struct ib_device *ibdev, u8 port_num,
1498                           struct ib_port_immutable *immutable)
1499 {
1500         struct ib_port_attr attr;
1501         int err;
1502
1503         err = query_port(ibdev, port_num, &attr);
1504         if (err)
1505                 return err;
1506
1507         memset(immutable, 0, sizeof(*immutable));
1508
1509         immutable->pkey_tbl_len = attr.pkey_tbl_len;
1510         immutable->gid_tbl_len = attr.gid_tbl_len;
1511         immutable->core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1512         immutable->max_mad_size = OPA_MGMT_MAD_SIZE;
1513
1514         return 0;
1515 }
1516
1517 static int modify_device(struct ib_device *device,
1518                          int device_modify_mask,
1519                          struct ib_device_modify *device_modify)
1520 {
1521         struct hfi1_devdata *dd = dd_from_ibdev(device);
1522         unsigned i;
1523         int ret;
1524
1525         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1526                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1527                 ret = -EOPNOTSUPP;
1528                 goto bail;
1529         }
1530
1531         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1532                 memcpy(device->node_desc, device_modify->node_desc, 64);
1533                 for (i = 0; i < dd->num_pports; i++) {
1534                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1535
1536                         hfi1_node_desc_chg(ibp);
1537                 }
1538         }
1539
1540         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1541                 ib_hfi1_sys_image_guid =
1542                         cpu_to_be64(device_modify->sys_image_guid);
1543                 for (i = 0; i < dd->num_pports; i++) {
1544                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1545
1546                         hfi1_sys_guid_chg(ibp);
1547                 }
1548         }
1549
1550         ret = 0;
1551
1552 bail:
1553         return ret;
1554 }
1555
1556 static int modify_port(struct ib_device *ibdev, u8 port,
1557                        int port_modify_mask, struct ib_port_modify *props)
1558 {
1559         struct hfi1_ibport *ibp = to_iport(ibdev, port);
1560         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1561         int ret = 0;
1562
1563         ibp->port_cap_flags |= props->set_port_cap_mask;
1564         ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1565         if (props->set_port_cap_mask || props->clr_port_cap_mask)
1566                 hfi1_cap_mask_chg(ibp);
1567         if (port_modify_mask & IB_PORT_SHUTDOWN) {
1568                 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1569                   OPA_LINKDOWN_REASON_UNKNOWN);
1570                 ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1571         }
1572         if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1573                 ibp->qkey_violations = 0;
1574         return ret;
1575 }
1576
1577 static int query_gid(struct ib_device *ibdev, u8 port,
1578                      int index, union ib_gid *gid)
1579 {
1580         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1581         int ret = 0;
1582
1583         if (!port || port > dd->num_pports)
1584                 ret = -EINVAL;
1585         else {
1586                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1587                 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1588
1589                 gid->global.subnet_prefix = ibp->gid_prefix;
1590                 if (index == 0)
1591                         gid->global.interface_id = cpu_to_be64(ppd->guid);
1592                 else if (index < HFI1_GUIDS_PER_PORT)
1593                         gid->global.interface_id = ibp->guids[index - 1];
1594                 else
1595                         ret = -EINVAL;
1596         }
1597
1598         return ret;
1599 }
1600
1601 static struct ib_pd *alloc_pd(struct ib_device *ibdev,
1602                               struct ib_ucontext *context,
1603                               struct ib_udata *udata)
1604 {
1605         struct hfi1_ibdev *dev = to_idev(ibdev);
1606         struct hfi1_pd *pd;
1607         struct ib_pd *ret;
1608
1609         /*
1610          * This is actually totally arbitrary.  Some correctness tests
1611          * assume there's a maximum number of PDs that can be allocated.
1612          * We don't actually have this limit, but we fail the test if
1613          * we allow allocations of more than we report for this value.
1614          */
1615
1616         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1617         if (!pd) {
1618                 ret = ERR_PTR(-ENOMEM);
1619                 goto bail;
1620         }
1621
1622         spin_lock(&dev->n_pds_lock);
1623         if (dev->n_pds_allocated == hfi1_max_pds) {
1624                 spin_unlock(&dev->n_pds_lock);
1625                 kfree(pd);
1626                 ret = ERR_PTR(-ENOMEM);
1627                 goto bail;
1628         }
1629
1630         dev->n_pds_allocated++;
1631         spin_unlock(&dev->n_pds_lock);
1632
1633         /* ib_alloc_pd() will initialize pd->ibpd. */
1634         pd->user = udata != NULL;
1635
1636         ret = &pd->ibpd;
1637
1638 bail:
1639         return ret;
1640 }
1641
1642 static int dealloc_pd(struct ib_pd *ibpd)
1643 {
1644         struct hfi1_pd *pd = to_ipd(ibpd);
1645         struct hfi1_ibdev *dev = to_idev(ibpd->device);
1646
1647         spin_lock(&dev->n_pds_lock);
1648         dev->n_pds_allocated--;
1649         spin_unlock(&dev->n_pds_lock);
1650
1651         kfree(pd);
1652
1653         return 0;
1654 }
1655
1656 /*
1657  * convert ah port,sl to sc
1658  */
1659 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1660 {
1661         struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1662
1663         return ibp->sl_to_sc[ah->sl];
1664 }
1665
1666 int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1667 {
1668         struct hfi1_ibport *ibp;
1669         struct hfi1_pportdata *ppd;
1670         struct hfi1_devdata *dd;
1671         u8 sc5;
1672
1673         /* A multicast address requires a GRH (see ch. 8.4.1). */
1674         if (ah_attr->dlid >= HFI1_MULTICAST_LID_BASE &&
1675             ah_attr->dlid != HFI1_PERMISSIVE_LID &&
1676             !(ah_attr->ah_flags & IB_AH_GRH))
1677                 goto bail;
1678         if ((ah_attr->ah_flags & IB_AH_GRH) &&
1679             ah_attr->grh.sgid_index >= HFI1_GUIDS_PER_PORT)
1680                 goto bail;
1681         if (ah_attr->dlid == 0)
1682                 goto bail;
1683         if (ah_attr->port_num < 1 ||
1684             ah_attr->port_num > ibdev->phys_port_cnt)
1685                 goto bail;
1686         if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1687             ib_rate_to_mbps(ah_attr->static_rate) < 0)
1688                 goto bail;
1689         if (ah_attr->sl >= OPA_MAX_SLS)
1690                 goto bail;
1691         /* test the mapping for validity */
1692         ibp = to_iport(ibdev, ah_attr->port_num);
1693         ppd = ppd_from_ibp(ibp);
1694         sc5 = ibp->sl_to_sc[ah_attr->sl];
1695         dd = dd_from_ppd(ppd);
1696         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1697                 goto bail;
1698         return 0;
1699 bail:
1700         return -EINVAL;
1701 }
1702
1703 /**
1704  * create_ah - create an address handle
1705  * @pd: the protection domain
1706  * @ah_attr: the attributes of the AH
1707  *
1708  * This may be called from interrupt context.
1709  */
1710 static struct ib_ah *create_ah(struct ib_pd *pd,
1711                                struct ib_ah_attr *ah_attr)
1712 {
1713         struct hfi1_ah *ah;
1714         struct ib_ah *ret;
1715         struct hfi1_ibdev *dev = to_idev(pd->device);
1716         unsigned long flags;
1717
1718         if (hfi1_check_ah(pd->device, ah_attr)) {
1719                 ret = ERR_PTR(-EINVAL);
1720                 goto bail;
1721         }
1722
1723         ah = kmalloc(sizeof(*ah), GFP_ATOMIC);
1724         if (!ah) {
1725                 ret = ERR_PTR(-ENOMEM);
1726                 goto bail;
1727         }
1728
1729         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1730         if (dev->n_ahs_allocated == hfi1_max_ahs) {
1731                 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1732                 kfree(ah);
1733                 ret = ERR_PTR(-ENOMEM);
1734                 goto bail;
1735         }
1736
1737         dev->n_ahs_allocated++;
1738         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1739
1740         /* ib_create_ah() will initialize ah->ibah. */
1741         ah->attr = *ah_attr;
1742         atomic_set(&ah->refcount, 0);
1743
1744         ret = &ah->ibah;
1745
1746 bail:
1747         return ret;
1748 }
1749
1750 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1751 {
1752         struct ib_ah_attr attr;
1753         struct ib_ah *ah = ERR_PTR(-EINVAL);
1754         struct hfi1_qp *qp0;
1755
1756         memset(&attr, 0, sizeof(attr));
1757         attr.dlid = dlid;
1758         attr.port_num = ppd_from_ibp(ibp)->port;
1759         rcu_read_lock();
1760         qp0 = rcu_dereference(ibp->qp[0]);
1761         if (qp0)
1762                 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1763         rcu_read_unlock();
1764         return ah;
1765 }
1766
1767 /**
1768  * destroy_ah - destroy an address handle
1769  * @ibah: the AH to destroy
1770  *
1771  * This may be called from interrupt context.
1772  */
1773 static int destroy_ah(struct ib_ah *ibah)
1774 {
1775         struct hfi1_ibdev *dev = to_idev(ibah->device);
1776         struct hfi1_ah *ah = to_iah(ibah);
1777         unsigned long flags;
1778
1779         if (atomic_read(&ah->refcount) != 0)
1780                 return -EBUSY;
1781
1782         spin_lock_irqsave(&dev->n_ahs_lock, flags);
1783         dev->n_ahs_allocated--;
1784         spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1785
1786         kfree(ah);
1787
1788         return 0;
1789 }
1790
1791 static int modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1792 {
1793         struct hfi1_ah *ah = to_iah(ibah);
1794
1795         if (hfi1_check_ah(ibah->device, ah_attr))
1796                 return -EINVAL;
1797
1798         ah->attr = *ah_attr;
1799
1800         return 0;
1801 }
1802
1803 static int query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1804 {
1805         struct hfi1_ah *ah = to_iah(ibah);
1806
1807         *ah_attr = ah->attr;
1808
1809         return 0;
1810 }
1811
1812 /**
1813  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1814  * @dd: the hfi1_ib device
1815  */
1816 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1817 {
1818         return ARRAY_SIZE(dd->pport[0].pkeys);
1819 }
1820
1821 static int query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1822                       u16 *pkey)
1823 {
1824         struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1825         int ret;
1826
1827         if (index >= hfi1_get_npkeys(dd)) {
1828                 ret = -EINVAL;
1829                 goto bail;
1830         }
1831
1832         *pkey = hfi1_get_pkey(to_iport(ibdev, port), index);
1833         ret = 0;
1834
1835 bail:
1836         return ret;
1837 }
1838
1839 /**
1840  * alloc_ucontext - allocate a ucontest
1841  * @ibdev: the infiniband device
1842  * @udata: not used by the driver
1843  */
1844
1845 static struct ib_ucontext *alloc_ucontext(struct ib_device *ibdev,
1846                                           struct ib_udata *udata)
1847 {
1848         struct hfi1_ucontext *context;
1849         struct ib_ucontext *ret;
1850
1851         context = kmalloc(sizeof(*context), GFP_KERNEL);
1852         if (!context) {
1853                 ret = ERR_PTR(-ENOMEM);
1854                 goto bail;
1855         }
1856
1857         ret = &context->ibucontext;
1858
1859 bail:
1860         return ret;
1861 }
1862
1863 static int dealloc_ucontext(struct ib_ucontext *context)
1864 {
1865         kfree(to_iucontext(context));
1866         return 0;
1867 }
1868
1869 static void init_ibport(struct hfi1_pportdata *ppd)
1870 {
1871         struct hfi1_ibport *ibp = &ppd->ibport_data;
1872         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1873         int i;
1874
1875         for (i = 0; i < sz; i++) {
1876                 ibp->sl_to_sc[i] = i;
1877                 ibp->sc_to_sl[i] = i;
1878         }
1879
1880         spin_lock_init(&ibp->lock);
1881         /* Set the prefix to the default value (see ch. 4.1.1) */
1882         ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1883         ibp->sm_lid = 0;
1884         /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1885         ibp->port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1886                 IB_PORT_CAP_MASK_NOTICE_SUP;
1887         ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1888         ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1889         ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1890         ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1891         ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1892
1893         RCU_INIT_POINTER(ibp->qp[0], NULL);
1894         RCU_INIT_POINTER(ibp->qp[1], NULL);
1895 }
1896
1897 static void verbs_txreq_kmem_cache_ctor(void *obj)
1898 {
1899         struct verbs_txreq *tx = (struct verbs_txreq *)obj;
1900
1901         memset(tx, 0, sizeof(*tx));
1902 }
1903
1904 /**
1905  * hfi1_register_ib_device - register our device with the infiniband core
1906  * @dd: the device data structure
1907  * Return 0 if successful, errno if unsuccessful.
1908  */
1909 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1910 {
1911         struct hfi1_ibdev *dev = &dd->verbs_dev;
1912         struct ib_device *ibdev = &dev->ibdev;
1913         struct hfi1_pportdata *ppd = dd->pport;
1914         unsigned i, lk_tab_size;
1915         int ret;
1916         size_t lcpysz = IB_DEVICE_NAME_MAX;
1917         u16 descq_cnt;
1918
1919         ret = hfi1_qp_init(dev);
1920         if (ret)
1921                 goto err_qp_init;
1922
1923
1924         for (i = 0; i < dd->num_pports; i++)
1925                 init_ibport(ppd + i);
1926
1927         /* Only need to initialize non-zero fields. */
1928         spin_lock_init(&dev->n_pds_lock);
1929         spin_lock_init(&dev->n_ahs_lock);
1930         spin_lock_init(&dev->n_cqs_lock);
1931         spin_lock_init(&dev->n_qps_lock);
1932         spin_lock_init(&dev->n_srqs_lock);
1933         spin_lock_init(&dev->n_mcast_grps_lock);
1934         init_timer(&dev->mem_timer);
1935         dev->mem_timer.function = mem_timer;
1936         dev->mem_timer.data = (unsigned long) dev;
1937
1938         /*
1939          * The top hfi1_lkey_table_size bits are used to index the
1940          * table.  The lower 8 bits can be owned by the user (copied from
1941          * the LKEY).  The remaining bits act as a generation number or tag.
1942          */
1943         spin_lock_init(&dev->lk_table.lock);
1944         dev->lk_table.max = 1 << hfi1_lkey_table_size;
1945         /* ensure generation is at least 4 bits (keys.c) */
1946         if (hfi1_lkey_table_size > MAX_LKEY_TABLE_BITS) {
1947                 dd_dev_warn(dd, "lkey bits %u too large, reduced to %u\n",
1948                               hfi1_lkey_table_size, MAX_LKEY_TABLE_BITS);
1949                 hfi1_lkey_table_size = MAX_LKEY_TABLE_BITS;
1950         }
1951         lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
1952         dev->lk_table.table = (struct hfi1_mregion __rcu **)
1953                 vmalloc(lk_tab_size);
1954         if (dev->lk_table.table == NULL) {
1955                 ret = -ENOMEM;
1956                 goto err_lk;
1957         }
1958         RCU_INIT_POINTER(dev->dma_mr, NULL);
1959         for (i = 0; i < dev->lk_table.max; i++)
1960                 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
1961         INIT_LIST_HEAD(&dev->pending_mmaps);
1962         spin_lock_init(&dev->pending_lock);
1963         seqlock_init(&dev->iowait_lock);
1964         dev->mmap_offset = PAGE_SIZE;
1965         spin_lock_init(&dev->mmap_offset_lock);
1966         INIT_LIST_HEAD(&dev->txwait);
1967         INIT_LIST_HEAD(&dev->memwait);
1968
1969         descq_cnt = sdma_get_descq_cnt();
1970
1971         /* SLAB_HWCACHE_ALIGN for AHG */
1972         dev->verbs_txreq_cache = kmem_cache_create("hfi1_vtxreq_cache",
1973                                                    sizeof(struct verbs_txreq),
1974                                                    0, SLAB_HWCACHE_ALIGN,
1975                                                    verbs_txreq_kmem_cache_ctor);
1976         if (!dev->verbs_txreq_cache) {
1977                 ret = -ENOMEM;
1978                 goto err_verbs_txreq;
1979         }
1980
1981         /*
1982          * The system image GUID is supposed to be the same for all
1983          * HFIs in a single system but since there can be other
1984          * device types in the system, we can't be sure this is unique.
1985          */
1986         if (!ib_hfi1_sys_image_guid)
1987                 ib_hfi1_sys_image_guid = cpu_to_be64(ppd->guid);
1988         lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1989         strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1990         ibdev->owner = THIS_MODULE;
1991         ibdev->node_guid = cpu_to_be64(ppd->guid);
1992         ibdev->uverbs_abi_ver = HFI1_UVERBS_ABI_VERSION;
1993         ibdev->uverbs_cmd_mask =
1994                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
1995                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
1996                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
1997                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
1998                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
1999                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
2000                 (1ull << IB_USER_VERBS_CMD_MODIFY_AH)           |
2001                 (1ull << IB_USER_VERBS_CMD_QUERY_AH)            |
2002                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
2003                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
2004                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
2005                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2006                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
2007                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
2008                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
2009                 (1ull << IB_USER_VERBS_CMD_POLL_CQ)             |
2010                 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ)       |
2011                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
2012                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
2013                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
2014                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
2015                 (1ull << IB_USER_VERBS_CMD_POST_SEND)           |
2016                 (1ull << IB_USER_VERBS_CMD_POST_RECV)           |
2017                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
2018                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
2019                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
2020                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
2021                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
2022                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
2023                 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2024         ibdev->node_type = RDMA_NODE_IB_CA;
2025         ibdev->phys_port_cnt = dd->num_pports;
2026         ibdev->num_comp_vectors = 1;
2027         ibdev->dma_device = &dd->pcidev->dev;
2028         ibdev->query_device = query_device;
2029         ibdev->modify_device = modify_device;
2030         ibdev->query_port = query_port;
2031         ibdev->modify_port = modify_port;
2032         ibdev->query_pkey = query_pkey;
2033         ibdev->query_gid = query_gid;
2034         ibdev->alloc_ucontext = alloc_ucontext;
2035         ibdev->dealloc_ucontext = dealloc_ucontext;
2036         ibdev->alloc_pd = alloc_pd;
2037         ibdev->dealloc_pd = dealloc_pd;
2038         ibdev->create_ah = create_ah;
2039         ibdev->destroy_ah = destroy_ah;
2040         ibdev->modify_ah = modify_ah;
2041         ibdev->query_ah = query_ah;
2042         ibdev->create_srq = hfi1_create_srq;
2043         ibdev->modify_srq = hfi1_modify_srq;
2044         ibdev->query_srq = hfi1_query_srq;
2045         ibdev->destroy_srq = hfi1_destroy_srq;
2046         ibdev->create_qp = hfi1_create_qp;
2047         ibdev->modify_qp = hfi1_modify_qp;
2048         ibdev->query_qp = hfi1_query_qp;
2049         ibdev->destroy_qp = hfi1_destroy_qp;
2050         ibdev->post_send = post_send;
2051         ibdev->post_recv = post_receive;
2052         ibdev->post_srq_recv = hfi1_post_srq_receive;
2053         ibdev->create_cq = hfi1_create_cq;
2054         ibdev->destroy_cq = hfi1_destroy_cq;
2055         ibdev->resize_cq = hfi1_resize_cq;
2056         ibdev->poll_cq = hfi1_poll_cq;
2057         ibdev->req_notify_cq = hfi1_req_notify_cq;
2058         ibdev->get_dma_mr = hfi1_get_dma_mr;
2059         ibdev->reg_phys_mr = hfi1_reg_phys_mr;
2060         ibdev->reg_user_mr = hfi1_reg_user_mr;
2061         ibdev->dereg_mr = hfi1_dereg_mr;
2062         ibdev->alloc_mr = hfi1_alloc_mr;
2063         ibdev->alloc_fmr = hfi1_alloc_fmr;
2064         ibdev->map_phys_fmr = hfi1_map_phys_fmr;
2065         ibdev->unmap_fmr = hfi1_unmap_fmr;
2066         ibdev->dealloc_fmr = hfi1_dealloc_fmr;
2067         ibdev->attach_mcast = hfi1_multicast_attach;
2068         ibdev->detach_mcast = hfi1_multicast_detach;
2069         ibdev->process_mad = hfi1_process_mad;
2070         ibdev->mmap = hfi1_mmap;
2071         ibdev->dma_ops = &hfi1_dma_mapping_ops;
2072         ibdev->get_port_immutable = port_immutable;
2073
2074         strncpy(ibdev->node_desc, init_utsname()->nodename,
2075                 sizeof(ibdev->node_desc));
2076
2077         ret = ib_register_device(ibdev, hfi1_create_port_files);
2078         if (ret)
2079                 goto err_reg;
2080
2081         ret = hfi1_create_agents(dev);
2082         if (ret)
2083                 goto err_agents;
2084
2085         ret = hfi1_verbs_register_sysfs(dd);
2086         if (ret)
2087                 goto err_class;
2088
2089         goto bail;
2090
2091 err_class:
2092         hfi1_free_agents(dev);
2093 err_agents:
2094         ib_unregister_device(ibdev);
2095 err_reg:
2096 err_verbs_txreq:
2097         kmem_cache_destroy(dev->verbs_txreq_cache);
2098         vfree(dev->lk_table.table);
2099 err_lk:
2100         hfi1_qp_exit(dev);
2101 err_qp_init:
2102         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2103 bail:
2104         return ret;
2105 }
2106
2107 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
2108 {
2109         struct hfi1_ibdev *dev = &dd->verbs_dev;
2110         struct ib_device *ibdev = &dev->ibdev;
2111
2112         hfi1_verbs_unregister_sysfs(dd);
2113
2114         hfi1_free_agents(dev);
2115
2116         ib_unregister_device(ibdev);
2117
2118         if (!list_empty(&dev->txwait))
2119                 dd_dev_err(dd, "txwait list not empty!\n");
2120         if (!list_empty(&dev->memwait))
2121                 dd_dev_err(dd, "memwait list not empty!\n");
2122         if (dev->dma_mr)
2123                 dd_dev_err(dd, "DMA MR not NULL!\n");
2124
2125         hfi1_qp_exit(dev);
2126         del_timer_sync(&dev->mem_timer);
2127         kmem_cache_destroy(dev->verbs_txreq_cache);
2128         vfree(dev->lk_table.table);
2129 }
2130
2131 /*
2132  * This must be called with s_lock held.
2133  */
2134 void hfi1_schedule_send(struct hfi1_qp *qp)
2135 {
2136         if (hfi1_send_ok(qp)) {
2137                 struct hfi1_ibport *ibp =
2138                         to_iport(qp->ibqp.device, qp->port_num);
2139                 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2140
2141                 iowait_schedule(&qp->s_iowait, ppd->hfi1_wq);
2142         }
2143 }
2144
2145 void hfi1_cnp_rcv(struct hfi1_packet *packet)
2146 {
2147         struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2148
2149         if (packet->qp->ibqp.qp_type == IB_QPT_UC)
2150                 hfi1_uc_rcv(packet);
2151         else if (packet->qp->ibqp.qp_type == IB_QPT_UD)
2152                 hfi1_ud_rcv(packet);
2153         else
2154                 ibp->n_pkt_drops++;
2155 }