drivers/staging/rtl8188eu/hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_HAL_INIT_C_
  21
  22 #include <osdep_service.h>
  23 #include <drv_types.h>
  24 #include <rtw_efuse.h>
  25
  26 #include <rtl8188e_hal.h>
  27 #include <rtl8188e_led.h>
  28 #include <rtw_iol.h>
  29 #include <usb_ops.h>
  30 #include <usb_hal.h>
  31 #include <usb_osintf.h>
  32
  33 #define         HAL_MAC_ENABLE  1
  34 #define         HAL_BB_ENABLE           1
  35 #define         HAL_RF_ENABLE           1
  36
  37 static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
  38 {
  39         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  40
  41         switch (NumOutPipe) {
  42         case    3:
  43                 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
  44                 haldata->OutEpNumber = 3;
  45                 break;
  46         case    2:
  47                 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
  48                 haldata->OutEpNumber = 2;
  49                 break;
  50         case    1:
  51                 haldata->OutEpQueueSel = TX_SELE_HQ;
  52                 haldata->OutEpNumber = 1;
  53                 break;
  54         default:
  55                 break;
  56         }
  57         DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
  58 }
  59
  60 static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
  61 {
  62         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  63         bool                    result          = false;
  64
  65         _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
  66
  67         /*  Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
  68         if (1 == haldata->OutEpNumber) {
  69                 if (1 != NumInPipe)
  70                         return result;
  71         }
  72
  73         /*  All config other than above support one Bulk IN and one Interrupt IN. */
  74
  75         result = Hal_MappingOutPipe(adapt, NumOutPipe);
  76
  77         return result;
  78 }
  79
  80 static void rtl8188eu_interface_configure(struct adapter *adapt)
  81 {
  82         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
  83         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(adapt);
  84
  85         if (pdvobjpriv->ishighspeed)
  86                 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */
  87         else
  88                 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */
  89
  90         haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
  91
  92         haldata->UsbTxAggMode           = 1;
  93         haldata->UsbTxAggDescNum        = 0x6;  /*  only 4 bits */
  94
  95         haldata->UsbRxAggMode           = USB_RX_AGG_DMA;/*  USB_RX_AGG_DMA; */
  96         haldata->UsbRxAggBlockCount     = 8; /* unit : 512b */
  97         haldata->UsbRxAggBlockTimeout   = 0x6;
  98         haldata->UsbRxAggPageCount      = 48; /* uint :128 b 0x0A;      10 = MAX_RX_DMA_BUFFER_SIZE/2/haldata->UsbBulkOutSize */
  99         haldata->UsbRxAggPageTimeout    = 0x4; /* 6, absolute time = 34ms/(2^6) */
 100
 101         HalUsbSetQueuePipeMapping8188EUsb(adapt,
 102                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 103 }
 104
 105 static u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
 106 {
 107         u16 value16;
 108         /*  HW Power on sequence */
 109         struct hal_data_8188e   *haldata        = GET_HAL_DATA(adapt);
 110         if (haldata->bMacPwrCtrlOn)
 111                 return _SUCCESS;
 112
 113         if (!HalPwrSeqCmdParsing(adapt, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) {
 114                 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
 115                 return _FAIL;
 116         }
 117
 118         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 119         /*  Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
 120         rtw_write16(adapt, REG_CR, 0x00);  /* suggseted by zhouzhou, by page, 20111230 */
 121
 122                 /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 123         value16 = rtw_read16(adapt, REG_CR);
 124         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 125                                 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 126         /*  for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
 127
 128         rtw_write16(adapt, REG_CR, value16);
 129         haldata->bMacPwrCtrlOn = true;
 130
 131         return _SUCCESS;
 132 }
 133
 134 /*  Shall USB interface init this? */
 135 static void _InitInterrupt(struct adapter *Adapter)
 136 {
 137         u32 imr, imr_ex;
 138         u8  usb_opt;
 139         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 140
 141         /* HISR write one to clear */
 142         rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
 143         /*  HIMR - */
 144         imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
 145         rtw_write32(Adapter, REG_HIMR_88E, imr);
 146         haldata->IntrMask[0] = imr;
 147
 148         imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
 149         rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
 150         haldata->IntrMask[1] = imr_ex;
 151
 152         /*  REG_USB_SPECIAL_OPTION - BIT(4) */
 153         /*  0; Use interrupt endpoint to upload interrupt pkt */
 154         /*  1; Use bulk endpoint to upload interrupt pkt, */
 155         usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 156
 157         if (!adapter_to_dvobj(Adapter)->ishighspeed)
 158                 usb_opt = usb_opt & (~INT_BULK_SEL);
 159         else
 160                 usb_opt = usb_opt | (INT_BULK_SEL);
 161
 162         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
 163 }
 164
 165 static void _InitQueueReservedPage(struct adapter *Adapter)
 166 {
 167         struct hal_data_8188e           *haldata = GET_HAL_DATA(Adapter);
 168         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 169         u32 numHQ       = 0;
 170         u32 numLQ       = 0;
 171         u32 numNQ       = 0;
 172         u32 numPubQ;
 173         u32 value32;
 174         u8 value8;
 175         bool bWiFiConfig = pregistrypriv->wifi_spec;
 176
 177         if (bWiFiConfig) {
 178                 if (haldata->OutEpQueueSel & TX_SELE_HQ)
 179                         numHQ =  0x29;
 180
 181                 if (haldata->OutEpQueueSel & TX_SELE_LQ)
 182                         numLQ = 0x1C;
 183
 184                 /*  NOTE: This step shall be proceed before writting REG_RQPN. */
 185                 if (haldata->OutEpQueueSel & TX_SELE_NQ)
 186                         numNQ = 0x1C;
 187                 value8 = (u8)_NPQ(numNQ);
 188                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 189
 190                 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
 191
 192                 /*  TX DMA */
 193                 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 194                 rtw_write32(Adapter, REG_RQPN, value32);
 195         } else {
 196                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
 197                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d);
 198                 rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
 199         }
 200 }
 201
 202 static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
 203 {
 204         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 205         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 206         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 207         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 208         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 209 }
 210
 211 static void _InitPageBoundary(struct adapter *Adapter)
 212 {
 213         /*  RX Page Boundary */
 214         /*  */
 215         u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
 216
 217         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 218 }
 219
 220 static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
 221                                        u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
 222                                        u16 hiQ)
 223 {
 224         u16 value16     = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 225
 226         value16 |= _TXDMA_BEQ_MAP(beQ)  | _TXDMA_BKQ_MAP(bkQ) |
 227                    _TXDMA_VIQ_MAP(viQ)  | _TXDMA_VOQ_MAP(voQ) |
 228                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 229
 230         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 231 }
 232
 233 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
 234 {
 235         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 236
 237         u16 value = 0;
 238         switch (haldata->OutEpQueueSel) {
 239         case TX_SELE_HQ:
 240                 value = QUEUE_HIGH;
 241                 break;
 242         case TX_SELE_LQ:
 243                 value = QUEUE_LOW;
 244                 break;
 245         case TX_SELE_NQ:
 246                 value = QUEUE_NORMAL;
 247                 break;
 248         default:
 249                 break;
 250         }
 251         _InitNormalChipRegPriority(Adapter, value, value, value, value,
 252                                    value, value);
 253 }
 254
 255 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
 256 {
 257         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 258         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 259         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 260         u16 valueHi = 0;
 261         u16 valueLow = 0;
 262
 263         switch (haldata->OutEpQueueSel) {
 264         case (TX_SELE_HQ | TX_SELE_LQ):
 265                 valueHi = QUEUE_HIGH;
 266                 valueLow = QUEUE_LOW;
 267                 break;
 268         case (TX_SELE_NQ | TX_SELE_LQ):
 269                 valueHi = QUEUE_NORMAL;
 270                 valueLow = QUEUE_LOW;
 271                 break;
 272         case (TX_SELE_HQ | TX_SELE_NQ):
 273                 valueHi = QUEUE_HIGH;
 274                 valueLow = QUEUE_NORMAL;
 275                 break;
 276         default:
 277                 break;
 278         }
 279
 280         if (!pregistrypriv->wifi_spec) {
 281                 beQ     = valueLow;
 282                 bkQ     = valueLow;
 283                 viQ     = valueHi;
 284                 voQ     = valueHi;
 285                 mgtQ    = valueHi;
 286                 hiQ     = valueHi;
 287         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 288                 beQ     = valueLow;
 289                 bkQ     = valueHi;
 290                 viQ     = valueHi;
 291                 voQ     = valueLow;
 292                 mgtQ    = valueHi;
 293                 hiQ     = valueHi;
 294         }
 295         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 296 }
 297
 298 static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
 299 {
 300         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 301         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 302
 303         if (!pregistrypriv->wifi_spec) {/*  typical setting */
 304                 beQ     = QUEUE_LOW;
 305                 bkQ     = QUEUE_LOW;
 306                 viQ     = QUEUE_NORMAL;
 307                 voQ     = QUEUE_HIGH;
 308                 mgtQ    = QUEUE_HIGH;
 309                 hiQ     = QUEUE_HIGH;
 310         } else {/*  for WMM */
 311                 beQ     = QUEUE_LOW;
 312                 bkQ     = QUEUE_NORMAL;
 313                 viQ     = QUEUE_NORMAL;
 314                 voQ     = QUEUE_HIGH;
 315                 mgtQ    = QUEUE_HIGH;
 316                 hiQ     = QUEUE_HIGH;
 317         }
 318         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 319 }
 320
 321 static void _InitQueuePriority(struct adapter *Adapter)
 322 {
 323         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 324
 325         switch (haldata->OutEpNumber) {
 326         case 1:
 327                 _InitNormalChipOneOutEpPriority(Adapter);
 328                 break;
 329         case 2:
 330                 _InitNormalChipTwoOutEpPriority(Adapter);
 331                 break;
 332         case 3:
 333                 _InitNormalChipThreeOutEpPriority(Adapter);
 334                 break;
 335         default:
 336                 break;
 337         }
 338 }
 339
 340 static void _InitNetworkType(struct adapter *Adapter)
 341 {
 342         u32 value32;
 343
 344         value32 = rtw_read32(Adapter, REG_CR);
 345         /*  TODO: use the other function to set network type */
 346         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 347
 348         rtw_write32(Adapter, REG_CR, value32);
 349 }
 350
 351 static void _InitTransferPageSize(struct adapter *Adapter)
 352 {
 353         /*  Tx page size is always 128. */
 354
 355         u8 value8;
 356         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 357         rtw_write8(Adapter, REG_PBP, value8);
 358 }
 359
 360 static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
 361 {
 362         rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 363 }
 364
 365 static void _InitWMACSetting(struct adapter *Adapter)
 366 {
 367         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 368
 369         haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
 370                                   RCR_CBSSID_DATA | RCR_CBSSID_BCN |
 371                                   RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 372                                   RCR_APP_MIC | RCR_APP_PHYSTS;
 373
 374         /*  some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
 375         rtw_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
 376
 377         /*  Accept all multicast address */
 378         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 379         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 380 }
 381
 382 static void _InitAdaptiveCtrl(struct adapter *Adapter)
 383 {
 384         u16 value16;
 385         u32 value32;
 386
 387         /*  Response Rate Set */
 388         value32 = rtw_read32(Adapter, REG_RRSR);
 389         value32 &= ~RATE_BITMAP_ALL;
 390         value32 |= RATE_RRSR_CCK_ONLY_1M;
 391         rtw_write32(Adapter, REG_RRSR, value32);
 392
 393         /*  CF-END Threshold */
 394
 395         /*  SIFS (used in NAV) */
 396         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 397         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 398
 399         /*  Retry Limit */
 400         value16 = _LRL(0x30) | _SRL(0x30);
 401         rtw_write16(Adapter, REG_RL, value16);
 402 }
 403
 404 static void _InitEDCA(struct adapter *Adapter)
 405 {
 406         /*  Set Spec SIFS (used in NAV) */
 407         rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
 408         rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
 409
 410         /*  Set SIFS for CCK */
 411         rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
 412
 413         /*  Set SIFS for OFDM */
 414         rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
 415
 416         /*  TXOP */
 417         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 418         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 419         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 420         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 421 }
 422
 423 static void _InitBeaconMaxError(struct adapter *Adapter, bool           InfraMode)
 424 {
 425 }
 426
 427 static void _InitHWLed(struct adapter *Adapter)
 428 {
 429         struct led_priv *pledpriv = &(Adapter->ledpriv);
 430
 431         if (pledpriv->LedStrategy != HW_LED)
 432                 return;
 433
 434 /*  HW led control */
 435 /*  to do .... */
 436 /* must consider cases of antenna diversity/ commbo card/solo card/mini card */
 437 }
 438
 439 static void _InitRDGSetting(struct adapter *Adapter)
 440 {
 441         rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
 442         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 443         rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
 444 }
 445
 446 static void _InitRxSetting(struct adapter *Adapter)
 447 {
 448         rtw_write32(Adapter, REG_MACID, 0x87654321);
 449         rtw_write32(Adapter, 0x0700, 0x87654321);
 450 }
 451
 452 static void _InitRetryFunction(struct adapter *Adapter)
 453 {
 454         u8 value8;
 455
 456         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 457         value8 |= EN_AMPDU_RTY_NEW;
 458         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 459
 460         /*  Set ACK timeout */
 461         rtw_write8(Adapter, REG_ACKTO, 0x40);
 462 }
 463
 464 /*-----------------------------------------------------------------------------
 465  * Function:    usb_AggSettingTxUpdate()
 466  *
 467  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 468  *                      dynamic TX/RX aggreagtion parameters update.
 469  *
 470  * Input:                       struct adapter *
 471  *
 472  * Output/Return:       NONE
 473  *
 474  * Revised History:
 475  *      When            Who             Remark
 476  *      12/10/2010      MHC             Seperate to smaller function.
 477  *
 478  *---------------------------------------------------------------------------*/
 479 static void usb_AggSettingTxUpdate(struct adapter *Adapter)
 480 {
 481         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 482         u32 value32;
 483
 484         if (Adapter->registrypriv.wifi_spec)
 485                 haldata->UsbTxAggMode = false;
 486
 487         if (haldata->UsbTxAggMode) {
 488                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 489                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 490                 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 491
 492                 rtw_write32(Adapter, REG_TDECTRL, value32);
 493         }
 494 }       /*  usb_AggSettingTxUpdate */
 495
 496 /*-----------------------------------------------------------------------------
 497  * Function:    usb_AggSettingRxUpdate()
 498  *
 499  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 500  *                      dynamic TX/RX aggreagtion parameters update.
 501  *
 502  * Input:                       struct adapter *
 503  *
 504  * Output/Return:       NONE
 505  *
 506  * Revised History:
 507  *      When            Who             Remark
 508  *      12/10/2010      MHC             Seperate to smaller function.
 509  *
 510  *---------------------------------------------------------------------------*/
 511 static void
 512 usb_AggSettingRxUpdate(
 513                 struct adapter *Adapter
 514         )
 515 {
 516         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 517         u8 valueDMA;
 518         u8 valueUSB;
 519
 520         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 521         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 522
 523         switch (haldata->UsbRxAggMode) {
 524         case USB_RX_AGG_DMA:
 525                 valueDMA |= RXDMA_AGG_EN;
 526                 valueUSB &= ~USB_AGG_EN;
 527                 break;
 528         case USB_RX_AGG_USB:
 529                 valueDMA &= ~RXDMA_AGG_EN;
 530                 valueUSB |= USB_AGG_EN;
 531                 break;
 532         case USB_RX_AGG_MIX:
 533                 valueDMA |= RXDMA_AGG_EN;
 534                 valueUSB |= USB_AGG_EN;
 535                 break;
 536         case USB_RX_AGG_DISABLE:
 537         default:
 538                 valueDMA &= ~RXDMA_AGG_EN;
 539                 valueUSB &= ~USB_AGG_EN;
 540                 break;
 541         }
 542
 543         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 544         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 545
 546         switch (haldata->UsbRxAggMode) {
 547         case USB_RX_AGG_DMA:
 548                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
 549                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
 550                 break;
 551         case USB_RX_AGG_USB:
 552                 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
 553                 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
 554                 break;
 555         case USB_RX_AGG_MIX:
 556                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
 557                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));/* 0x280[12:8] */
 558                 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
 559                 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
 560                 break;
 561         case USB_RX_AGG_DISABLE:
 562         default:
 563                 /*  TODO: */
 564                 break;
 565         }
 566
 567         switch (PBP_128) {
 568         case PBP_128:
 569                 haldata->HwRxPageSize = 128;
 570                 break;
 571         case PBP_64:
 572                 haldata->HwRxPageSize = 64;
 573                 break;
 574         case PBP_256:
 575                 haldata->HwRxPageSize = 256;
 576                 break;
 577         case PBP_512:
 578                 haldata->HwRxPageSize = 512;
 579                 break;
 580         case PBP_1024:
 581                 haldata->HwRxPageSize = 1024;
 582                 break;
 583         default:
 584                 break;
 585         }
 586 }       /*  usb_AggSettingRxUpdate */
 587
 588 static void InitUsbAggregationSetting(struct adapter *Adapter)
 589 {
 590         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 591
 592         /*  Tx aggregation setting */
 593         usb_AggSettingTxUpdate(Adapter);
 594
 595         /*  Rx aggregation setting */
 596         usb_AggSettingRxUpdate(Adapter);
 597
 598         /*  201/12/10 MH Add for USB agg mode dynamic switch. */
 599         haldata->UsbRxHighSpeedMode = false;
 600 }
 601
 602 static void _InitOperationMode(struct adapter *Adapter)
 603 {
 604 }
 605
 606 static void _InitBeaconParameters(struct adapter *Adapter)
 607 {
 608         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
 609
 610         rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
 611
 612         /*  TODO: Remove these magic number */
 613         rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/*  ms */
 614         rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/*  5ms */
 615         rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /*  2ms */
 616
 617         /*  Suggested by designer timchen. Change beacon AIFS to the largest number */
 618         /*  beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
 619         rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
 620
 621         haldata->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
 622         haldata->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
 623         haldata->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
 624         haldata->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
 625         haldata->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
 626 }
 627
 628 static void _BeaconFunctionEnable(struct adapter *Adapter,
 629                                   bool Enable, bool Linked)
 630 {
 631         rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
 632
 633         rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
 634 }
 635
 636 /*  Set CCK and OFDM Block "ON" */
 637 static void _BBTurnOnBlock(struct adapter *Adapter)
 638 {
 639         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 640         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 641 }
 642
 643 enum {
 644         Antenna_Lfet = 1,
 645         Antenna_Right = 2,
 646 };
 647
 648 static void _InitAntenna_Selection(struct adapter *Adapter)
 649 {
 650         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 651
 652         if (haldata->AntDivCfg == 0)
 653                 return;
 654         DBG_88E("==>  %s ....\n", __func__);
 655
 656         rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
 657         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
 658
 659         if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
 660                 haldata->CurAntenna = Antenna_A;
 661         else
 662                 haldata->CurAntenna = Antenna_B;
 663         DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
 664 }
 665
 666 /*-----------------------------------------------------------------------------
 667  * Function:    HwSuspendModeEnable92Cu()
 668  *
 669  * Overview:    HW suspend mode switch.
 670  *
 671  * Input:               NONE
 672  *
 673  * Output:      NONE
 674  *
 675  * Return:      NONE
 676  *
 677  * Revised History:
 678  *      When            Who             Remark
 679  *      08/23/2010      MHC             HW suspend mode switch test..
 680  *---------------------------------------------------------------------------*/
 681 enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
 682 {
 683         u8 val8;
 684         enum rt_rf_power_state rfpowerstate = rf_off;
 685
 686         if (adapt->pwrctrlpriv.bHWPowerdown) {
 687                 val8 = rtw_read8(adapt, REG_HSISR);
 688                 DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8);
 689                 rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
 690         } else { /*  rf on/off */
 691                 rtw_write8(adapt, REG_MAC_PINMUX_CFG, rtw_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3));
 692                 val8 = rtw_read8(adapt, REG_GPIO_IO_SEL);
 693                 DBG_88E("GPIO_IN=%02x\n", val8);
 694                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
 695         }
 696         return rfpowerstate;
 697 }       /*  HalDetectPwrDownMode */
 698
 699 static u32 rtl8188eu_hal_init(struct adapter *Adapter)
 700 {
 701         u8 value8 = 0;
 702         u16  value16;
 703         u8 txpktbuf_bndy;
 704         u32 status = _SUCCESS;
 705         struct hal_data_8188e           *haldata = GET_HAL_DATA(Adapter);
 706         struct pwrctrl_priv             *pwrctrlpriv = &Adapter->pwrctrlpriv;
 707         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 708         u32 init_start_time = rtw_get_current_time();
 709
 710         #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
 711
 712 _func_enter_;
 713
 714         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
 715
 716         if (Adapter->pwrctrlpriv.bkeepfwalive) {
 717                 _ps_open_RF(Adapter);
 718
 719                 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
 720                         PHY_IQCalibrate_8188E(Adapter, true);
 721                 } else {
 722                         PHY_IQCalibrate_8188E(Adapter, false);
 723                         haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 724                 }
 725
 726                 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
 727                 PHY_LCCalibrate_8188E(Adapter);
 728
 729                 goto exit;
 730         }
 731
 732         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
 733         status = rtl8188eu_InitPowerOn(Adapter);
 734         if (status == _FAIL) {
 735                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
 736                 goto exit;
 737         }
 738
 739         /*  Save target channel */
 740         haldata->CurrentChannel = 6;/* default set to 6 */
 741
 742         if (pwrctrlpriv->reg_rfoff) {
 743                 pwrctrlpriv->rf_pwrstate = rf_off;
 744         }
 745
 746         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 747         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 748         /*  2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
 749
 750         if (!pregistrypriv->wifi_spec) {
 751                 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
 752         } else {
 753                 /*  for WMM */
 754                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
 755         }
 756
 757         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
 758         _InitQueueReservedPage(Adapter);
 759         _InitQueuePriority(Adapter);
 760         _InitPageBoundary(Adapter);
 761         _InitTransferPageSize(Adapter);
 762
 763         _InitTxBufferBoundary(Adapter, 0);
 764
 765         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
 766         if (Adapter->registrypriv.mp_mode == 1) {
 767                 _InitRxSetting(Adapter);
 768                 Adapter->bFWReady = false;
 769                 haldata->fw_ractrl = false;
 770         } else {
 771                 status = rtl8188e_FirmwareDownload(Adapter);
 772
 773                 if (status != _SUCCESS) {
 774                         DBG_88E("%s: Download Firmware failed!!\n", __func__);
 775                         Adapter->bFWReady = false;
 776                         haldata->fw_ractrl = false;
 777                         return status;
 778                 } else {
 779                         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
 780                         Adapter->bFWReady = true;
 781                         haldata->fw_ractrl = false;
 782                 }
 783         }
 784         rtl8188e_InitializeFirmwareVars(Adapter);
 785
 786         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
 787 #if (HAL_MAC_ENABLE == 1)
 788         status = PHY_MACConfig8188E(Adapter);
 789         if (status == _FAIL) {
 790                 DBG_88E(" ### Failed to init MAC ......\n ");
 791                 goto exit;
 792         }
 793 #endif
 794
 795         /*  */
 796         /* d. Initialize BB related configurations. */
 797         /*  */
 798         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
 799 #if (HAL_BB_ENABLE == 1)
 800         status = PHY_BBConfig8188E(Adapter);
 801         if (status == _FAIL) {
 802                 DBG_88E(" ### Failed to init BB ......\n ");
 803                 goto exit;
 804         }
 805 #endif
 806
 807         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
 808 #if (HAL_RF_ENABLE == 1)
 809         status = PHY_RFConfig8188E(Adapter);
 810         if (status == _FAIL) {
 811                 DBG_88E(" ### Failed to init RF ......\n ");
 812                 goto exit;
 813         }
 814 #endif
 815
 816         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
 817         status = rtl8188e_iol_efuse_patch(Adapter);
 818         if (status == _FAIL) {
 819                 DBG_88E("%s  rtl8188e_iol_efuse_patch failed\n", __func__);
 820                 goto exit;
 821         }
 822
 823         _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
 824
 825         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
 826         status =  InitLLTTable(Adapter, txpktbuf_bndy);
 827         if (status == _FAIL) {
 828                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
 829                 goto exit;
 830         }
 831
 832         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
 833         /*  Get Rx PHY status in order to report RSSI and others. */
 834         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
 835
 836         _InitInterrupt(Adapter);
 837         hal_init_macaddr(Adapter);/* set mac_address */
 838         _InitNetworkType(Adapter);/* set msr */
 839         _InitWMACSetting(Adapter);
 840         _InitAdaptiveCtrl(Adapter);
 841         _InitEDCA(Adapter);
 842         _InitRetryFunction(Adapter);
 843         InitUsbAggregationSetting(Adapter);
 844         _InitOperationMode(Adapter);/* todo */
 845         _InitBeaconParameters(Adapter);
 846         _InitBeaconMaxError(Adapter, true);
 847
 848         /*  */
 849         /*  Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
 850         /*  Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E. */
 851         /*  */
 852         /*  Enable MACTXEN/MACRXEN block */
 853         value16 = rtw_read16(Adapter, REG_CR);
 854         value16 |= (MACTXEN | MACRXEN);
 855         rtw_write8(Adapter, REG_CR, value16);
 856
 857         if (haldata->bRDGEnable)
 858                 _InitRDGSetting(Adapter);
 859
 860         /* Enable TX Report */
 861         /* Enable Tx Report Timer */
 862         value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
 863         rtw_write8(Adapter,  REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
 864         /* Set MAX RPT MACID */
 865         rtw_write8(Adapter,  REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
 866         /* Tx RPT Timer. Unit: 32us */
 867         rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
 868
 869         rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
 870
 871         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  /*  unit: 256us. 256ms */
 872         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  /*  unit: 256us. 256ms */
 873
 874         _InitHWLed(Adapter);
 875
 876         /* Keep RfRegChnlVal for later use. */
 877         haldata->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
 878         haldata->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
 879
 880 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
 881         _BBTurnOnBlock(Adapter);
 882
 883 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
 884         invalidate_cam_all(Adapter);
 885
 886 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
 887         /*  2010/12/17 MH We need to set TX power according to EFUSE content at first. */
 888         PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel);
 889
 890 /*  Move by Neo for USB SS to below setp */
 891 /* _RfPowerSave(Adapter); */
 892
 893         _InitAntenna_Selection(Adapter);
 894
 895         /*  */
 896         /*  Disable BAR, suggested by Scott */
 897         /*  2010.04.09 add by hpfan */
 898         /*  */
 899         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 900
 901         /*  HW SEQ CTRL */
 902         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 903         rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
 904
 905         if (pregistrypriv->wifi_spec)
 906                 rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
 907
 908         /* Nav limit , suggest by scott */
 909         rtw_write8(Adapter, 0x652, 0x0);
 910
 911 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
 912         rtl8188e_InitHalDm(Adapter);
 913
 914         if (Adapter->registrypriv.mp_mode == 1) {
 915                 Adapter->mppriv.channel = haldata->CurrentChannel;
 916                 MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
 917         } else {
 918                 /*  2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
 919                 /*  and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
 920                 /*  call initstruct adapter. May cause some problem?? */
 921                 /*  Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
 922                 /*  in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
 923                 /*  is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
 924                 /*  Added by tynli. 2010.03.30. */
 925                 pwrctrlpriv->rf_pwrstate = rf_on;
 926
 927                 /*  enable Tx report. */
 928                 rtw_write8(Adapter,  REG_FWHW_TXQ_CTRL+1, 0x0F);
 929
 930                 /*  Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
 931                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
 932
 933                 /* tynli_test_tx_report. */
 934                 rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
 935
 936                 /* enable tx DMA to drop the redundate data of packet */
 937                 rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
 938
 939 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
 940                 /*  2010/08/26 MH Merge from 8192CE. */
 941                 if (pwrctrlpriv->rf_pwrstate == rf_on) {
 942                         if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
 943                                 PHY_IQCalibrate_8188E(Adapter, true);
 944                         } else {
 945                                 PHY_IQCalibrate_8188E(Adapter, false);
 946                                 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 947                         }
 948
 949 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
 950
 951                         ODM_TXPowerTrackingCheck(&haldata->odmpriv);
 952
 953 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
 954                         PHY_LCCalibrate_8188E(Adapter);
 955                 }
 956         }
 957
 958 /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
 959 /*      _InitPABias(Adapter); */
 960         rtw_write8(Adapter, REG_USB_HRPWM, 0);
 961
 962         /* ack for xmit mgmt frames. */
 963         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
 964
 965 exit:
 966 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
 967
 968         DBG_88E("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
 969
 970 _func_exit_;
 971
 972         return status;
 973 }
 974
 975 void _ps_open_RF(struct adapter *adapt)
 976 {
 977         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
 978         /* phy_SsPwrSwitch92CU(adapt, rf_on, 1); */
 979 }
 980
 981 static void _ps_close_RF(struct adapter *adapt)
 982 {
 983         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
 984         /* phy_SsPwrSwitch92CU(adapt, rf_off, 1); */
 985 }
 986
 987 static void CardDisableRTL8188EU(struct adapter *Adapter)
 988 {
 989         u8 val8;
 990         struct hal_data_8188e   *haldata        = GET_HAL_DATA(Adapter);
 991
 992         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
 993
 994         /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
 995         val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
 996         rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
 997
 998         /*  stop rx */
 999         rtw_write8(Adapter, REG_CR, 0x0);
1000
1001         /*  Run LPS WL RFOFF flow */
1002         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
1003
1004         /*  2. 0x1F[7:0] = 0            turn off RF */
1005
1006         val8 = rtw_read8(Adapter, REG_MCUFWDL);
1007         if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */
1008                 /*  Reset MCU 0x2[10]=0. */
1009                 val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
1010                 val8 &= ~BIT(2);        /*  0x2[10], FEN_CPUEN */
1011                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
1012         }
1013
1014         /*  reset MCU ready status */
1015         rtw_write8(Adapter, REG_MCUFWDL, 0);
1016
1017         /* YJ,add,111212 */
1018         /* Disable 32k */
1019         val8 = rtw_read8(Adapter, REG_32K_CTRL);
1020         rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
1021
1022         /*  Card disable power action flow */
1023         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);
1024
1025         /*  Reset MCU IO Wrapper */
1026         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
1027         rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
1028         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
1029         rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
1030
1031         /* YJ,test add, 111207. For Power Consumption. */
1032         val8 = rtw_read8(Adapter, GPIO_IN);
1033         rtw_write8(Adapter, GPIO_OUT, val8);
1034         rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */
1035
1036         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
1037         rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
1038         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
1039         rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);/* Reg0x43 */
1040         rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
1041         haldata->bMacPwrCtrlOn = false;
1042         Adapter->bFWReady = false;
1043 }
1044 static void rtl8192cu_hw_power_down(struct adapter *adapt)
1045 {
1046         /*  2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. */
1047         /*  Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. */
1048
1049         /*  Enable register area 0x0-0xc. */
1050         rtw_write8(adapt, REG_RSV_CTRL, 0x0);
1051         rtw_write16(adapt, REG_APS_FSMCO, 0x8812);
1052 }
1053
1054 static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
1055 {
1056
1057         DBG_88E("==> %s\n", __func__);
1058
1059         rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
1060         rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
1061
1062         DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
1063         if (Adapter->pwrctrlpriv.bkeepfwalive) {
1064                 _ps_close_RF(Adapter);
1065                 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1066                         rtl8192cu_hw_power_down(Adapter);
1067         } else {
1068                 if (Adapter->hw_init_completed) {
1069                         CardDisableRTL8188EU(Adapter);
1070
1071                         if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1072                                 rtl8192cu_hw_power_down(Adapter);
1073                 }
1074         }
1075         return _SUCCESS;
1076  }
1077
1078 static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
1079 {
1080         u8 i;
1081         struct recv_buf *precvbuf;
1082         uint    status;
1083         struct intf_hdl *pintfhdl = &Adapter->iopriv.intf;
1084         struct recv_priv *precvpriv = &(Adapter->recvpriv);
1085         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
1086
1087 _func_enter_;
1088
1089         _read_port = pintfhdl->io_ops._read_port;
1090
1091         status = _SUCCESS;
1092
1093         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1094                  ("===> usb_inirp_init\n"));
1095
1096         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1097
1098         /* issue Rx irp to receive data */
1099         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1100         for (i = 0; i < NR_RECVBUFF; i++) {
1101                 if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false) {
1102                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n"));
1103                         status = _FAIL;
1104                         goto exit;
1105                 }
1106
1107                 precvbuf++;
1108                 precvpriv->free_recv_buf_queue_cnt--;
1109         }
1110
1111 exit:
1112
1113         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n"));
1114
1115 _func_exit_;
1116
1117         return status;
1118 }
1119
1120 static unsigned int rtl8188eu_inirp_deinit(struct adapter *Adapter)
1121 {
1122         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n ===> usb_rx_deinit\n"));
1123
1124         rtw_read_port_cancel(Adapter);
1125
1126         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n <=== usb_rx_deinit\n"));
1127
1128         return _SUCCESS;
1129 }
1130
1131 /*  */
1132 /*  */
1133 /*      EEPROM/EFUSE Content Parsing */
1134 /*  */
1135 /*  */
1136 static void _ReadLEDSetting(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
1137 {
1138         struct led_priv *pledpriv = &(Adapter->ledpriv);
1139         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1140
1141         pledpriv->bRegUseLed = true;
1142         pledpriv->LedStrategy = SW_LED_MODE1;
1143         haldata->bLedOpenDrain = true;/*  Support Open-drain arrangement for controlling the LED. */
1144 }
1145
1146 static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1147 {
1148         struct hal_data_8188e   *haldata = GET_HAL_DATA(adapt);
1149
1150         if (!AutoLoadFail) {
1151                 /*  VID, PID */
1152                 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1153                 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1154
1155                 /*  Customer ID, 0x00 and 0xff are reserved for Realtek. */
1156                 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1157                 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1158         } else {
1159                 haldata->EEPROMVID                      = EEPROM_Default_VID;
1160                 haldata->EEPROMPID                      = EEPROM_Default_PID;
1161
1162                 /*  Customer ID, 0x00 and 0xff are reserved for Realtek. */
1163                 haldata->EEPROMCustomerID               = EEPROM_Default_CustomerID;
1164                 haldata->EEPROMSubCustomerID    = EEPROM_Default_SubCustomerID;
1165         }
1166
1167         DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1168         DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1169 }
1170
1171 static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1172 {
1173         u16 i;
1174         u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1175         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1176
1177         if (AutoLoadFail) {
1178                 for (i = 0; i < 6; i++)
1179                         eeprom->mac_addr[i] = sMacAddr[i];
1180         } else {
1181                 /* Read Permanent MAC address */
1182                 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1183         }
1184         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1185                  ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1186                  eeprom->mac_addr[0], eeprom->mac_addr[1],
1187                  eeprom->mac_addr[2], eeprom->mac_addr[3],
1188                  eeprom->mac_addr[4], eeprom->mac_addr[5]));
1189 }
1190
1191 static void Hal_CustomizeByCustomerID_8188EU(struct adapter *adapt)
1192 {
1193 }
1194
1195 static void
1196 readAdapterInfo_8188EU(
1197                 struct adapter *adapt
1198         )
1199 {
1200         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1201
1202         /* parse the eeprom/efuse content */
1203         Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1204         Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1205         Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1206
1207         Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1208         Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1209         Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1210         rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1211         Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1212         Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1213         Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1214         Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1215         Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1216
1217         /*  */
1218         /*  The following part initialize some vars by PG info. */
1219         /*  */
1220         Hal_InitChannelPlan(adapt);
1221         Hal_CustomizeByCustomerID_8188EU(adapt);
1222
1223         _ReadLEDSetting(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1224 }
1225
1226 static void _ReadPROMContent(
1227         struct adapter *Adapter
1228         )
1229 {
1230         struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1231         u8 eeValue;
1232
1233         /* check system boot selection */
1234         eeValue = rtw_read8(Adapter, REG_9346CR);
1235         eeprom->EepromOrEfuse           = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1236         eeprom->bautoload_fail_flag     = (eeValue & EEPROM_EN) ? false : true;
1237
1238         DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1239                 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1240
1241         Hal_InitPGData88E(Adapter);
1242         readAdapterInfo_8188EU(Adapter);
1243 }
1244
1245 static void _ReadRFType(struct adapter *Adapter)
1246 {
1247         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1248
1249         haldata->rf_chip = RF_6052;
1250 }
1251
1252 static int _ReadAdapterInfo8188EU(struct adapter *Adapter)
1253 {
1254         u32 start = rtw_get_current_time();
1255
1256         MSG_88E("====> %s\n", __func__);
1257
1258         _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1259         _ReadPROMContent(Adapter);
1260
1261         MSG_88E("<==== %s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
1262
1263         return _SUCCESS;
1264 }
1265
1266 static void ReadAdapterInfo8188EU(struct adapter *Adapter)
1267 {
1268         /*  Read EEPROM size before call any EEPROM function */
1269         Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
1270
1271         _ReadAdapterInfo8188EU(Adapter);
1272 }
1273
1274 #define GPIO_DEBUG_PORT_NUM 0
1275 static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1276 {
1277 }
1278
1279 static void ResumeTxBeacon(struct adapter *adapt)
1280 {
1281         struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1282
1283         /*  2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1284         /*  which should be read from register to a global variable. */
1285
1286         rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6);
1287         haldata->RegFwHwTxQCtrl |= BIT6;
1288         rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
1289         haldata->RegReg542 |= BIT0;
1290         rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1291 }
1292
1293 static void StopTxBeacon(struct adapter *adapt)
1294 {
1295         struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1296
1297         /*  2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1298         /*  which should be read from register to a global variable. */
1299
1300         rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6));
1301         haldata->RegFwHwTxQCtrl &= (~BIT6);
1302         rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
1303         haldata->RegReg542 &= ~(BIT0);
1304         rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1305
1306          /* todo: CheckFwRsvdPageContent(Adapter);  2010.06.23. Added by tynli. */
1307 }
1308
1309 static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1310 {
1311         u8 val8;
1312         u8 mode = *((u8 *)val);
1313
1314         /*  disable Port0 TSF update */
1315         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1316
1317         /*  set net_type */
1318         val8 = rtw_read8(Adapter, MSR)&0x0c;
1319         val8 |= mode;
1320         rtw_write8(Adapter, MSR, val8);
1321
1322         DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1323
1324         if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1325                 StopTxBeacon(Adapter);
1326
1327                 rtw_write8(Adapter, REG_BCN_CTRL, 0x19);/* disable atim wnd */
1328         } else if ((mode == _HW_STATE_ADHOC_)) {
1329                 ResumeTxBeacon(Adapter);
1330                 rtw_write8(Adapter, REG_BCN_CTRL, 0x1a);
1331         } else if (mode == _HW_STATE_AP_) {
1332                 ResumeTxBeacon(Adapter);
1333
1334                 rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
1335
1336                 /* Set RCR */
1337                 rtw_write32(Adapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0,reject ICV_ERR packet */
1338                 /* enable to rx data frame */
1339                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1340                 /* enable to rx ps-poll */
1341                 rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
1342
1343                 /* Beacon Control related register for first time */
1344                 rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /*  2ms */
1345
1346                 rtw_write8(Adapter, REG_ATIMWND, 0x0a); /*  10ms */
1347                 rtw_write16(Adapter, REG_BCNTCFG, 0x00);
1348                 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1349                 rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/*  +32767 (~32ms) */
1350
1351                 /* reset TSF */
1352                 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
1353
1354                 /* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */
1355                 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
1356
1357                 /* enable BCN0 Function for if1 */
1358                 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
1359                 rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | BIT(1)));
1360
1361                 /* dis BCN1 ATIM  WND if if2 is station */
1362                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
1363         }
1364 }
1365
1366 static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1367 {
1368         u8 idx = 0;
1369         u32 reg_macid;
1370
1371         reg_macid = REG_MACID;
1372
1373         for (idx = 0; idx < 6; idx++)
1374                 rtw_write8(Adapter, (reg_macid+idx), val[idx]);
1375 }
1376
1377 static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1378 {
1379         u8 idx = 0;
1380         u32 reg_bssid;
1381
1382         reg_bssid = REG_BSSID;
1383
1384         for (idx = 0; idx < 6; idx++)
1385                 rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
1386 }
1387
1388 static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1389 {
1390         u32 bcn_ctrl_reg;
1391
1392         bcn_ctrl_reg = REG_BCN_CTRL;
1393
1394         if (*((u8 *)val))
1395                 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
1396         else
1397                 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
1398 }
1399
1400 static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1401 {
1402         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1403         struct dm_priv  *pdmpriv = &haldata->dmpriv;
1404         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1405 _func_enter_;
1406
1407         switch (variable) {
1408         case HW_VAR_MEDIA_STATUS:
1409                 {
1410                         u8 val8;
1411
1412                         val8 = rtw_read8(Adapter, MSR)&0x0c;
1413                         val8 |= *((u8 *)val);
1414                         rtw_write8(Adapter, MSR, val8);
1415                 }
1416                 break;
1417         case HW_VAR_MEDIA_STATUS1:
1418                 {
1419                         u8 val8;
1420
1421                         val8 = rtw_read8(Adapter, MSR) & 0x03;
1422                         val8 |= *((u8 *)val) << 2;
1423                         rtw_write8(Adapter, MSR, val8);
1424                 }
1425                 break;
1426         case HW_VAR_SET_OPMODE:
1427                 hw_var_set_opmode(Adapter, variable, val);
1428                 break;
1429         case HW_VAR_MAC_ADDR:
1430                 hw_var_set_macaddr(Adapter, variable, val);
1431                 break;
1432         case HW_VAR_BSSID:
1433                 hw_var_set_bssid(Adapter, variable, val);
1434                 break;
1435         case HW_VAR_BASIC_RATE:
1436                 {
1437                         u16 BrateCfg = 0;
1438                         u8 RateIndex = 0;
1439
1440                         /*  2007.01.16, by Emily */
1441                         /*  Select RRSR (in Legacy-OFDM and CCK) */
1442                         /*  For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */
1443                         /*  We do not use other rates. */
1444                         HalSetBrateCfg(Adapter, val, &BrateCfg);
1445                         DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1446
1447                         /* 2011.03.30 add by Luke Lee */
1448                         /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
1449                         /* because CCK 2M has poor TXEVM */
1450                         /* CCK 5.5M & 11M ACK should be enabled for better performance */
1451
1452                         BrateCfg = (BrateCfg | 0xd) & 0x15d;
1453                         haldata->BasicRateSet = BrateCfg;
1454
1455                         BrateCfg |= 0x01; /*  default enable 1M ACK rate */
1456                         /*  Set RRSR rate table. */
1457                         rtw_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1458                         rtw_write8(Adapter, REG_RRSR+1, (BrateCfg >> 8) & 0xff);
1459                         rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0);
1460
1461                         /*  Set RTS initial rate */
1462                         while (BrateCfg > 0x1) {
1463                                 BrateCfg = (BrateCfg >> 1);
1464                                 RateIndex++;
1465                         }
1466                         /*  Ziv - Check */
1467                         rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
1468                 }
1469                 break;
1470         case HW_VAR_TXPAUSE:
1471                 rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
1472                 break;
1473         case HW_VAR_BCN_FUNC:
1474                 hw_var_set_bcn_func(Adapter, variable, val);
1475                 break;
1476         case HW_VAR_CORRECT_TSF:
1477                 {
1478                         u64     tsf;
1479                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1480                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1481
1482                         tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024; /* us */
1483
1484                         if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1485                                 StopTxBeacon(Adapter);
1486
1487                         /* disable related TSF function */
1488                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
1489
1490                         rtw_write32(Adapter, REG_TSFTR, tsf);
1491                         rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
1492
1493                         /* enable related TSF function */
1494                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
1495
1496                         if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1497                                 ResumeTxBeacon(Adapter);
1498                 }
1499                 break;
1500         case HW_VAR_CHECK_BSSID:
1501                 if (*((u8 *)val)) {
1502                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1503                 } else {
1504                         u32 val32;
1505
1506                         val32 = rtw_read32(Adapter, REG_RCR);
1507
1508                         val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1509
1510                         rtw_write32(Adapter, REG_RCR, val32);
1511                 }
1512                 break;
1513         case HW_VAR_MLME_DISCONNECT:
1514                 /* Set RCR to not to receive data frame when NO LINK state */
1515                 /* reject all data frames */
1516                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1517
1518                 /* reset TSF */
1519                 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
1520
1521                 /* disable update TSF */
1522                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1523                 break;
1524         case HW_VAR_MLME_SITESURVEY:
1525                 if (*((u8 *)val)) { /* under sitesurvey */
1526                         /* config RCR to receive different BSSID & not to receive data frame */
1527                         u32 v = rtw_read32(Adapter, REG_RCR);
1528                         v &= ~(RCR_CBSSID_BCN);
1529                         rtw_write32(Adapter, REG_RCR, v);
1530                         /* reject all data frame */
1531                         rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1532
1533                         /* disable update TSF */
1534                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1535                 } else { /* sitesurvey done */
1536                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1537                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1538
1539                         if ((is_client_associated_to_ap(Adapter)) ||
1540                             ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) {
1541                                 /* enable to rx data frame */
1542                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1543
1544                                 /* enable update TSF */
1545                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1546                         } else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1547                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1548                                 /* enable update TSF */
1549                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1550                         }
1551                         if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1552                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1553                         } else {
1554                                 if (Adapter->in_cta_test) {
1555                                         u32 v = rtw_read32(Adapter, REG_RCR);
1556                                         v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/*  RCR_ADF */
1557                                         rtw_write32(Adapter, REG_RCR, v);
1558                                 } else {
1559                                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1560                                 }
1561                         }
1562                 }
1563                 break;
1564         case HW_VAR_MLME_JOIN:
1565                 {
1566                         u8 RetryLimit = 0x30;
1567                         u8 type = *((u8 *)val);
1568                         struct mlme_priv        *pmlmepriv = &Adapter->mlmepriv;
1569
1570                         if (type == 0) { /*  prepare to join */
1571                                 /* enable to rx data frame.Accept all data frame */
1572                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1573
1574                                 if (Adapter->in_cta_test) {
1575                                         u32 v = rtw_read32(Adapter, REG_RCR);
1576                                         v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/*  RCR_ADF */
1577                                         rtw_write32(Adapter, REG_RCR, v);
1578                                 } else {
1579                                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1580                                 }
1581
1582                                 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1583                                         RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1584                                 else /*  Ad-hoc Mode */
1585                                         RetryLimit = 0x7;
1586                         } else if (type == 1) {
1587                                 /* joinbss_event call back when join res < 0 */
1588                                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1589                         } else if (type == 2) {
1590                                 /* sta add event call back */
1591                                 /* enable update TSF */
1592                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1593
1594                                 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
1595                                         RetryLimit = 0x7;
1596                         }
1597                         rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
1598                 }
1599                 break;
1600         case HW_VAR_BEACON_INTERVAL:
1601                 rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
1602                 break;
1603         case HW_VAR_SLOT_TIME:
1604                 {
1605                         u8 u1bAIFS, aSifsTime;
1606                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
1607                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
1608
1609                         rtw_write8(Adapter, REG_SLOT, val[0]);
1610
1611                         if (pmlmeinfo->WMM_enable == 0) {
1612                                 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1613                                         aSifsTime = 10;
1614                                 else
1615                                         aSifsTime = 16;
1616
1617                                 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1618
1619                                 /*  <Roger_EXP> Temporary removed, 2008.06.20. */
1620                                 rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1621                                 rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1622                                 rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1623                                 rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
1624                         }
1625                 }
1626                 break;
1627         case HW_VAR_RESP_SIFS:
1628                 /* RESP_SIFS for CCK */
1629                 rtw_write8(Adapter, REG_R2T_SIFS, val[0]); /*  SIFS_T2T_CCK (0x08) */
1630                 rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); /* SIFS_R2T_CCK(0x08) */
1631                 /* RESP_SIFS for OFDM */
1632                 rtw_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */
1633                 rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
1634                 break;
1635         case HW_VAR_ACK_PREAMBLE:
1636                 {
1637                         u8 regTmp;
1638                         u8 bShortPreamble = *((bool *)val);
1639                         /*  Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
1640                         regTmp = (haldata->nCur40MhzPrimeSC)<<5;
1641                         if (bShortPreamble)
1642                                 regTmp |= 0x80;
1643
1644                         rtw_write8(Adapter, REG_RRSR+2, regTmp);
1645                 }
1646                 break;
1647         case HW_VAR_SEC_CFG:
1648                 rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
1649                 break;
1650         case HW_VAR_DM_FLAG:
1651                 podmpriv->SupportAbility = *((u8 *)val);
1652                 break;
1653         case HW_VAR_DM_FUNC_OP:
1654                 if (val[0])
1655                         podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1656                 else
1657                         podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1658                 break;
1659         case HW_VAR_DM_FUNC_SET:
1660                 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1661                         pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1662                         podmpriv->SupportAbility =      pdmpriv->InitODMFlag;
1663                 } else {
1664                         podmpriv->SupportAbility |= *((u32 *)val);
1665                 }
1666                 break;
1667         case HW_VAR_DM_FUNC_CLR:
1668                 podmpriv->SupportAbility &= *((u32 *)val);
1669                 break;
1670         case HW_VAR_CAM_EMPTY_ENTRY:
1671                 {
1672                         u8 ucIndex = *((u8 *)val);
1673                         u8 i;
1674                         u32 ulCommand = 0;
1675                         u32 ulContent = 0;
1676                         u32 ulEncAlgo = CAM_AES;
1677
1678                         for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1679                                 /*  filled id in CAM config 2 byte */
1680                                 if (i == 0)
1681                                         ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
1682                                 else
1683                                         ulContent = 0;
1684                                 /*  polling bit, and No Write enable, and address */
1685                                 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
1686                                 ulCommand = ulCommand | CAM_POLLINIG|CAM_WRITE;
1687                                 /*  write content 0 is equall to mark invalid */
1688                                 rtw_write32(Adapter, WCAMI, ulContent);  /* delay_ms(40); */
1689                                 rtw_write32(Adapter, RWCAM, ulCommand);  /* delay_ms(40); */
1690                         }
1691                 }
1692                 break;
1693         case HW_VAR_CAM_INVALID_ALL:
1694                 rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
1695                 break;
1696         case HW_VAR_CAM_WRITE:
1697                 {
1698                         u32 cmd;
1699                         u32 *cam_val = (u32 *)val;
1700                         rtw_write32(Adapter, WCAMI, cam_val[0]);
1701
1702                         cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
1703                         rtw_write32(Adapter, RWCAM, cmd);
1704                 }
1705                 break;
1706         case HW_VAR_AC_PARAM_VO:
1707                 rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
1708                 break;
1709         case HW_VAR_AC_PARAM_VI:
1710                 rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
1711                 break;
1712         case HW_VAR_AC_PARAM_BE:
1713                 haldata->AcParam_BE = ((u32 *)(val))[0];
1714                 rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
1715                 break;
1716         case HW_VAR_AC_PARAM_BK:
1717                 rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
1718                 break;
1719         case HW_VAR_ACM_CTRL:
1720                 {
1721                         u8 acm_ctrl = *((u8 *)val);
1722                         u8 AcmCtrl = rtw_read8(Adapter, REG_ACMHWCTRL);
1723
1724                         if (acm_ctrl > 1)
1725                                 AcmCtrl = AcmCtrl | 0x1;
1726
1727                         if (acm_ctrl & BIT(3))
1728                                 AcmCtrl |= AcmHw_VoqEn;
1729                         else
1730                                 AcmCtrl &= (~AcmHw_VoqEn);
1731
1732                         if (acm_ctrl & BIT(2))
1733                                 AcmCtrl |= AcmHw_ViqEn;
1734                         else
1735                                 AcmCtrl &= (~AcmHw_ViqEn);
1736
1737                         if (acm_ctrl & BIT(1))
1738                                 AcmCtrl |= AcmHw_BeqEn;
1739                         else
1740                                 AcmCtrl &= (~AcmHw_BeqEn);
1741
1742                         DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1743                         rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
1744                 }
1745                 break;
1746         case HW_VAR_AMPDU_MIN_SPACE:
1747                 {
1748                         u8 MinSpacingToSet;
1749                         u8 SecMinSpace;
1750
1751                         MinSpacingToSet = *((u8 *)val);
1752                         if (MinSpacingToSet <= 7) {
1753                                 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1754                                 case _NO_PRIVACY_:
1755                                 case _AES_:
1756                                         SecMinSpace = 0;
1757                                         break;
1758                                 case _WEP40_:
1759                                 case _WEP104_:
1760                                 case _TKIP_:
1761                                 case _TKIP_WTMIC_:
1762                                         SecMinSpace = 6;
1763                                         break;
1764                                 default:
1765                                         SecMinSpace = 7;
1766                                         break;
1767                                 }
1768                                 if (MinSpacingToSet < SecMinSpace)
1769                                         MinSpacingToSet = SecMinSpace;
1770                                 rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
1771                         }
1772                 }
1773                 break;
1774         case HW_VAR_AMPDU_FACTOR:
1775                 {
1776                         u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1777                         u8 FactorToSet;
1778                         u8 *pRegToSet;
1779                         u8 index = 0;
1780
1781                         pRegToSet = RegToSet_Normal; /*  0xb972a841; */
1782                         FactorToSet = *((u8 *)val);
1783                         if (FactorToSet <= 3) {
1784                                 FactorToSet = (1<<(FactorToSet + 2));
1785                                 if (FactorToSet > 0xf)
1786                                         FactorToSet = 0xf;
1787
1788                                 for (index = 0; index < 4; index++) {
1789                                         if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
1790                                                 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
1791
1792                                         if ((pRegToSet[index] & 0x0f) > FactorToSet)
1793                                                 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1794
1795                                         rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
1796                                 }
1797                         }
1798                 }
1799                 break;
1800         case HW_VAR_RXDMA_AGG_PG_TH:
1801                 {
1802                         u8 threshold = *((u8 *)val);
1803                         if (threshold == 0)
1804                                 threshold = haldata->UsbRxAggPageCount;
1805                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
1806                 }
1807                 break;
1808         case HW_VAR_SET_RPWM:
1809                 break;
1810         case HW_VAR_H2C_FW_PWRMODE:
1811                 {
1812                         u8 psmode = (*(u8 *)val);
1813
1814                         /*  Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
1815                         /*  saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
1816                         if ((psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(haldata->VersionID)))
1817                                 ODM_RF_Saving(podmpriv, true);
1818                         rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1819                 }
1820                 break;
1821         case HW_VAR_H2C_FW_JOINBSSRPT:
1822                 {
1823                         u8 mstatus = (*(u8 *)val);
1824                         rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1825                 }
1826                 break;
1827 #ifdef CONFIG_88EU_P2P
1828         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
1829                 {
1830                         u8 p2p_ps_state = (*(u8 *)val);
1831                         rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
1832                 }
1833                 break;
1834 #endif
1835         case HW_VAR_INITIAL_GAIN:
1836                 {
1837                         struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1838                         u32 rx_gain = ((u32 *)(val))[0];
1839
1840                         if (rx_gain == 0xff) {/* restore rx gain */
1841                                 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1842                         } else {
1843                                 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1844                                 ODM_Write_DIG(podmpriv, rx_gain);
1845                         }
1846                 }
1847                 break;
1848         case HW_VAR_TRIGGER_GPIO_0:
1849                 rtl8192cu_trigger_gpio_0(Adapter);
1850                 break;
1851         case HW_VAR_RPT_TIMER_SETTING:
1852                 {
1853                         u16 min_rpt_time = (*(u16 *)val);
1854                         ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1855                 }
1856                 break;
1857         case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1858                 {
1859                         u8 Optimum_antenna = (*(u8 *)val);
1860                         u8 Ant;
1861                         /* switch antenna to Optimum_antenna */
1862                         if (haldata->CurAntenna !=  Optimum_antenna) {
1863                                 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
1864                                 ODM_UpdateRxIdleAnt_88E(&haldata->odmpriv, Ant);
1865
1866                                 haldata->CurAntenna = Optimum_antenna;
1867                         }
1868                 }
1869                 break;
1870         case HW_VAR_EFUSE_BYTES: /*  To set EFUE total used bytes, added by Roger, 2008.12.22. */
1871                 haldata->EfuseUsedBytes = *((u16 *)val);
1872                 break;
1873         case HW_VAR_FIFO_CLEARN_UP:
1874                 {
1875                         struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1876                         u8 trycnt = 100;
1877
1878                         /* pause tx */
1879                         rtw_write8(Adapter, REG_TXPAUSE, 0xff);
1880
1881                         /* keep sn */
1882                         Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter, REG_NQOS_SEQ);
1883
1884                         if (!pwrpriv->bkeepfwalive) {
1885                                 /* RX DMA stop */
1886                                 rtw_write32(Adapter, REG_RXPKT_NUM, (rtw_read32(Adapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1887                                 do {
1888                                         if (!(rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE))
1889                                                 break;
1890                                 } while (trycnt--);
1891                                 if (trycnt == 0)
1892                                         DBG_88E("Stop RX DMA failed......\n");
1893
1894                                 /* RQPN Load 0 */
1895                                 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0);
1896                                 rtw_write32(Adapter, REG_RQPN, 0x80000000);
1897                                 rtw_mdelay_os(10);
1898                         }
1899                 }
1900                 break;
1901         case HW_VAR_CHECK_TXBUF:
1902                 break;
1903         case HW_VAR_APFM_ON_MAC:
1904                 haldata->bMacPwrCtrlOn = *val;
1905                 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1906                 break;
1907         case HW_VAR_TX_RPT_MAX_MACID:
1908                 {
1909                         u8 maxMacid = *val;
1910                         DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
1911                         rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
1912                 }
1913                 break;
1914         case HW_VAR_H2C_MEDIA_STATUS_RPT:
1915                 rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(__le16 *)val));
1916                 break;
1917         case HW_VAR_BCN_VALID:
1918                 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
1919                 rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0);
1920                 break;
1921         default:
1922                 break;
1923         }
1924 _func_exit_;
1925 }
1926
1927 static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1928 {
1929         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1930         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1931 _func_enter_;
1932
1933         switch (variable) {
1934         case HW_VAR_BASIC_RATE:
1935                 *((u16 *)(val)) = haldata->BasicRateSet;
1936         case HW_VAR_TXPAUSE:
1937                 val[0] = rtw_read8(Adapter, REG_TXPAUSE);
1938                 break;
1939         case HW_VAR_BCN_VALID:
1940                 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
1941                 val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2)) ? true : false;
1942                 break;
1943         case HW_VAR_DM_FLAG:
1944                 val[0] = podmpriv->SupportAbility;
1945                 break;
1946         case HW_VAR_RF_TYPE:
1947                 val[0] = haldata->rf_type;
1948                 break;
1949         case HW_VAR_FWLPS_RF_ON:
1950                 {
1951                         /* When we halt NIC, we should check if FW LPS is leave. */
1952                         if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1953                                 /*  If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
1954                                 /*  because Fw is unload. */
1955                                 val[0] = true;
1956                         } else {
1957                                 u32 valRCR;
1958                                 valRCR = rtw_read32(Adapter, REG_RCR);
1959                                 valRCR &= 0x00070000;
1960                                 if (valRCR)
1961                                         val[0] = false;
1962                                 else
1963                                         val[0] = true;
1964                         }
1965                 }
1966                 break;
1967         case HW_VAR_CURRENT_ANTENNA:
1968                 val[0] = haldata->CurAntenna;
1969                 break;
1970         case HW_VAR_EFUSE_BYTES: /*  To get EFUE total used bytes, added by Roger, 2008.12.22. */
1971                 *((u16 *)(val)) = haldata->EfuseUsedBytes;
1972                 break;
1973         case HW_VAR_APFM_ON_MAC:
1974                 *val = haldata->bMacPwrCtrlOn;
1975                 break;
1976         case HW_VAR_CHK_HI_QUEUE_EMPTY:
1977                 *val = ((rtw_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00) == 0) ? true : false;
1978                 break;
1979         default:
1980                 break;
1981         }
1982
1983 _func_exit_;
1984 }
1985
1986 /*  */
1987 /*      Description: */
1988 /*              Query setting of specified variable. */
1989 /*  */
1990 static u8
1991 GetHalDefVar8188EUsb(
1992                 struct adapter *Adapter,
1993                 enum hal_def_variable eVariable,
1994                 void *pValue
1995         )
1996 {
1997         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
1998         u8 bResult = _SUCCESS;
1999
2000         switch (eVariable) {
2001         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
2002                 {
2003                         struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
2004                         struct sta_priv *pstapriv = &Adapter->stapriv;
2005                         struct sta_info *psta;
2006                         psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
2007                         if (psta)
2008                                 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
2009                 }
2010                 break;
2011         case HAL_DEF_IS_SUPPORT_ANT_DIV:
2012                 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
2013                 break;
2014         case HAL_DEF_CURRENT_ANTENNA:
2015                 *((u8 *)pValue) = haldata->CurAntenna;
2016                 break;
2017         case HAL_DEF_DRVINFO_SZ:
2018                 *((u32 *)pValue) = DRVINFO_SZ;
2019                 break;
2020         case HAL_DEF_MAX_RECVBUF_SZ:
2021                 *((u32 *)pValue) = MAX_RECVBUF_SZ;
2022                 break;
2023         case HAL_DEF_RX_PACKET_OFFSET:
2024                 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
2025                 break;
2026         case HAL_DEF_DBG_DM_FUNC:
2027                 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
2028                 break;
2029         case HAL_DEF_RA_DECISION_RATE:
2030                 {
2031                         u8 MacID = *((u8 *)pValue);
2032                         *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&(haldata->odmpriv), MacID);
2033                 }
2034                 break;
2035         case HAL_DEF_RA_SGI:
2036                 {
2037                         u8 MacID = *((u8 *)pValue);
2038                         *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&(haldata->odmpriv), MacID);
2039                 }
2040                 break;
2041         case HAL_DEF_PT_PWR_STATUS:
2042                 {
2043                         u8 MacID = *((u8 *)pValue);
2044                         *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(haldata->odmpriv), MacID);
2045                 }
2046                 break;
2047         case HW_VAR_MAX_RX_AMPDU_FACTOR:
2048                 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
2049                 break;
2050         case HW_DEF_RA_INFO_DUMP:
2051                 {
2052                         u8 entry_id = *((u8 *)pValue);
2053                         if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
2054                                 DBG_88E("============ RA status check ===================\n");
2055                                 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
2056                                         entry_id,
2057                                         haldata->odmpriv.RAInfo[entry_id].RateID,
2058                                         haldata->odmpriv.RAInfo[entry_id].RAUseRate,
2059                                         haldata->odmpriv.RAInfo[entry_id].RateSGI,
2060                                         haldata->odmpriv.RAInfo[entry_id].DecisionRate,
2061                                         haldata->odmpriv.RAInfo[entry_id].PTStage);
2062                         }
2063                 }
2064                 break;
2065         case HW_DEF_ODM_DBG_FLAG:
2066                 {
2067                         struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2068                         pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents);
2069                 }
2070                 break;
2071         case HAL_DEF_DBG_DUMP_RXPKT:
2072                 *((u8 *)pValue) = haldata->bDumpRxPkt;
2073                 break;
2074         case HAL_DEF_DBG_DUMP_TXPKT:
2075                 *((u8 *)pValue) = haldata->bDumpTxPkt;
2076                 break;
2077         default:
2078                 bResult = _FAIL;
2079                 break;
2080         }
2081
2082         return bResult;
2083 }
2084
2085 /*  */
2086 /*      Description: */
2087 /*              Change default setting of specified variable. */
2088 /*  */
2089 static u8 SetHalDefVar8188EUsb(struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue)
2090 {
2091         struct hal_data_8188e   *haldata = GET_HAL_DATA(Adapter);
2092         u8 bResult = _SUCCESS;
2093
2094         switch (eVariable) {
2095         case HAL_DEF_DBG_DM_FUNC:
2096                 {
2097                         u8 dm_func = *((u8 *)pValue);
2098                         struct odm_dm_struct *podmpriv = &haldata->odmpriv;
2099
2100                         if (dm_func == 0) { /* disable all dynamic func */
2101                                 podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
2102                                 DBG_88E("==> Disable all dynamic function...\n");
2103                         } else if (dm_func == 1) {/* disable DIG */
2104                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
2105                                 DBG_88E("==> Disable DIG...\n");
2106                         } else if (dm_func == 2) {/* disable High power */
2107                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
2108                         } else if (dm_func == 3) {/* disable tx power tracking */
2109                                 podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
2110                                 DBG_88E("==> Disable tx power tracking...\n");
2111                         } else if (dm_func == 5) {/* disable antenna diversity */
2112                                 podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
2113                         } else if (dm_func == 6) {/* turn on all dynamic func */
2114                                 if (!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG)) {
2115                                         struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
2116                                         pDigTable->CurIGValue = rtw_read8(Adapter, 0xc50);
2117                                 }
2118                                 podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
2119                                 DBG_88E("==> Turn on all dynamic function...\n");
2120                         }
2121                 }
2122                 break;
2123         case HAL_DEF_DBG_DUMP_RXPKT:
2124                 haldata->bDumpRxPkt = *((u8 *)pValue);
2125                 break;
2126         case HAL_DEF_DBG_DUMP_TXPKT:
2127                 haldata->bDumpTxPkt = *((u8 *)pValue);
2128                 break;
2129         case HW_DEF_FA_CNT_DUMP:
2130                 {
2131                         u8 bRSSIDump = *((u8 *)pValue);
2132                         struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2133                         if (bRSSIDump)
2134                                 dm_ocm->DebugComponents =       ODM_COMP_DIG|ODM_COMP_FA_CNT    ;
2135                         else
2136                                 dm_ocm->DebugComponents = 0;
2137                 }
2138                 break;
2139         case HW_DEF_ODM_DBG_FLAG:
2140                 {
2141                         u64     DebugComponents = *((u64 *)pValue);
2142                         struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2143                         dm_ocm->DebugComponents = DebugComponents;
2144                 }
2145                 break;
2146         default:
2147                 bResult = _FAIL;
2148                 break;
2149         }
2150
2151         return bResult;
2152 }
2153
2154 static void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
2155 {
2156         u8 init_rate = 0;
2157         u8 networkType, raid;
2158         u32 mask, rate_bitmap;
2159         u8 shortGIrate = false;
2160         int     supportRateNum = 0;
2161         struct sta_info *psta;
2162         struct hal_data_8188e   *haldata = GET_HAL_DATA(adapt);
2163         struct mlme_ext_priv    *pmlmeext = &adapt->mlmeextpriv;
2164         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
2165         struct wlan_bssid_ex    *cur_network = &(pmlmeinfo->network);
2166
2167         if (mac_id >= NUM_STA) /* CAM_SIZE */
2168                 return;
2169         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2170         if (psta == NULL)
2171                 return;
2172         switch (mac_id) {
2173         case 0:/*  for infra mode */
2174                 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
2175                 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
2176                 raid = networktype_to_raid(networkType);
2177                 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2178                 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&(pmlmeinfo->HT_caps)) : 0;
2179                 if (support_short_GI(adapt, &(pmlmeinfo->HT_caps)))
2180                         shortGIrate = true;
2181                 break;
2182         case 1:/* for broadcast/multicast */
2183                 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2184                 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
2185                         networkType = WIRELESS_11B;
2186                 else
2187                         networkType = WIRELESS_11G;
2188                 raid = networktype_to_raid(networkType);
2189                 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
2190                 break;
2191         default: /* for each sta in IBSS */
2192                 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2193                 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
2194                 raid = networktype_to_raid(networkType);
2195                 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2196
2197                 /* todo: support HT in IBSS */
2198                 break;
2199         }
2200
2201         rate_bitmap = 0x0fffffff;
2202         rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
2203         DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2204                 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
2205
2206         mask &= rate_bitmap;
2207
2208         init_rate = get_highest_rate_idx(mask)&0x3f;
2209
2210         if (haldata->fw_ractrl) {
2211                 u8 arg;
2212
2213                 arg = mac_id & 0x1f;/* MACID */
2214                 arg |= BIT(7);
2215                 if (shortGIrate)
2216                         arg |= BIT(5);
2217                 mask |= ((raid << 28) & 0xf0000000);
2218                 DBG_88E("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
2219                 psta->ra_mask = mask;
2220                 mask |= ((raid << 28) & 0xf0000000);
2221
2222                 /* to do ,for 8188E-SMIC */
2223                 rtl8188e_set_raid_cmd(adapt, mask);
2224         } else {
2225                 ODM_RA_UpdateRateInfo_8188E(&(haldata->odmpriv),
2226                                 mac_id,
2227                                 raid,
2228                                 mask,
2229                                 shortGIrate
2230                                 );
2231         }
2232         /* set ra_id */
2233         psta->raid = raid;
2234         psta->init_rate = init_rate;
2235 }
2236
2237 static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
2238 {
2239         u32 value32;
2240         struct mlme_ext_priv    *pmlmeext = &(adapt->mlmeextpriv);
2241         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
2242         u32 bcn_ctrl_reg                        = REG_BCN_CTRL;
2243         /* reset TSF, enable update TSF, correcting TSF On Beacon */
2244
2245         /* BCN interval */
2246         rtw_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2247         rtw_write8(adapt, REG_ATIMWND, 0x02);/*  2ms */
2248
2249         _InitBeaconParameters(adapt);
2250
2251         rtw_write8(adapt, REG_SLOT, 0x09);
2252
2253         value32 = rtw_read32(adapt, REG_TCR);
2254         value32 &= ~TSFRST;
2255         rtw_write32(adapt,  REG_TCR, value32);
2256
2257         value32 |= TSFRST;
2258         rtw_write32(adapt, REG_TCR, value32);
2259
2260         /*  NOTE: Fix test chip's bug (about contention windows's randomness) */
2261         rtw_write8(adapt,  REG_RXTSF_OFFSET_CCK, 0x50);
2262         rtw_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
2263
2264         _BeaconFunctionEnable(adapt, true, true);
2265
2266         ResumeTxBeacon(adapt);
2267
2268         rtw_write8(adapt, bcn_ctrl_reg, rtw_read8(adapt, bcn_ctrl_reg)|BIT(1));
2269 }
2270
2271 static void rtl8188eu_init_default_value(struct adapter *adapt)
2272 {
2273         struct hal_data_8188e *haldata;
2274         struct pwrctrl_priv *pwrctrlpriv;
2275         u8 i;
2276
2277         haldata = GET_HAL_DATA(adapt);
2278         pwrctrlpriv = &adapt->pwrctrlpriv;
2279
2280         /* init default value */
2281         haldata->fw_ractrl = false;
2282         if (!pwrctrlpriv->bkeepfwalive)
2283                 haldata->LastHMEBoxNum = 0;
2284
2285         /* init dm default value */
2286         haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
2287         haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */
2288         haldata->pwrGroupCnt = 0;
2289         haldata->PGMaxGroup = 13;
2290         haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
2291         for (i = 0; i < HP_THERMAL_NUM; i++)
2292                 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2293 }
2294
2295 static u8 rtl8188eu_ps_func(struct adapter *Adapter, enum hal_intf_ps_func efunc_id, u8 *val)
2296 {
2297         u8 bResult = true;
2298         return bResult;
2299 }
2300
2301 void rtl8188eu_set_hal_ops(struct adapter *adapt)
2302 {
2303         struct hal_ops  *halfunc = &adapt->HalFunc;
2304
2305 _func_enter_;
2306
2307         adapt->HalData = rtw_zmalloc(sizeof(struct hal_data_8188e));
2308         if (adapt->HalData == NULL)
2309                 DBG_88E("cant not alloc memory for HAL DATA\n");
2310         adapt->hal_data_sz = sizeof(struct hal_data_8188e);
2311
2312         halfunc->hal_power_on = rtl8188eu_InitPowerOn;
2313         halfunc->hal_init = &rtl8188eu_hal_init;
2314         halfunc->hal_deinit = &rtl8188eu_hal_deinit;
2315
2316         halfunc->inirp_init = &rtl8188eu_inirp_init;
2317         halfunc->inirp_deinit = &rtl8188eu_inirp_deinit;
2318
2319         halfunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
2320         halfunc->free_xmit_priv = &rtl8188eu_free_xmit_priv;
2321
2322         halfunc->init_recv_priv = &rtl8188eu_init_recv_priv;
2323         halfunc->free_recv_priv = &rtl8188eu_free_recv_priv;
2324         halfunc->InitSwLeds = &rtl8188eu_InitSwLeds;
2325         halfunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
2326
2327         halfunc->init_default_value = &rtl8188eu_init_default_value;
2328         halfunc->intf_chip_configure = &rtl8188eu_interface_configure;
2329         halfunc->read_adapter_info = &ReadAdapterInfo8188EU;
2330
2331         halfunc->SetHwRegHandler = &SetHwReg8188EU;
2332         halfunc->GetHwRegHandler = &GetHwReg8188EU;
2333         halfunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
2334         halfunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
2335
2336         halfunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
2337         halfunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
2338
2339         halfunc->hal_xmit = &rtl8188eu_hal_xmit;
2340         halfunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
2341
2342         halfunc->interface_ps_func = &rtl8188eu_ps_func;
2343
2344         rtl8188e_set_hal_ops(halfunc);
2345 _func_exit_;
2346 }