2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/acpi.h>
27 #include <linux/clk.h>
28 #include <linux/reset.h>
29 #include <linux/pm_runtime.h>
31 #include <asm/byteorder.h>
35 /* Offsets for the DesignWare specific registers */
36 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
38 #define DW_UART_UCV 0xf8 /* UART Component Version */
40 /* Component Parameter Register bits */
41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
42 #define DW_UART_CPR_AFCE_MODE (1 << 4)
43 #define DW_UART_CPR_THRE_MODE (1 << 5)
44 #define DW_UART_CPR_SIR_MODE (1 << 6)
45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
48 #define DW_UART_CPR_FIFO_STAT (1 << 10)
49 #define DW_UART_CPR_SHADOW (1 << 11)
50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
51 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
52 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
53 /* Helper for fifo size calculation */
54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
64 struct reset_control *rst;
65 struct uart_8250_dma dma;
67 unsigned int skip_autocfg:1;
70 #define BYT_PRV_CLK 0x800
71 #define BYT_PRV_CLK_EN (1 << 0)
72 #define BYT_PRV_CLK_M_VAL_SHIFT 1
73 #define BYT_PRV_CLK_N_VAL_SHIFT 16
74 #define BYT_PRV_CLK_UPDATE (1 << 31)
76 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
78 struct dw8250_data *d = p->private_data;
80 /* Override any modem control signals if needed */
81 if (offset == UART_MSR) {
82 value |= d->msr_mask_on;
83 value &= ~d->msr_mask_off;
89 static void dw8250_force_idle(struct uart_port *p)
91 struct uart_8250_port *up = up_to_u8250p(p);
93 serial8250_clear_and_reinit_fifos(up);
94 (void)p->serial_in(p, UART_RX);
97 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
99 writeb(value, p->membase + (offset << p->regshift));
101 /* Make sure LCR write wasn't ignored */
102 if (offset == UART_LCR) {
105 unsigned int lcr = p->serial_in(p, UART_LCR);
106 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
108 dw8250_force_idle(p);
109 writeb(value, p->membase + (UART_LCR << p->regshift));
112 * FIXME: this deadlocks if port->lock is already held
113 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
118 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
120 unsigned int value = readb(p->membase + (offset << p->regshift));
122 return dw8250_modify_msr(p, offset, value);
126 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
130 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
132 return dw8250_modify_msr(p, offset, value);
135 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
138 __raw_writeq(value, p->membase + (offset << p->regshift));
139 /* Read back to ensure register write ordering. */
140 __raw_readq(p->membase + (UART_LCR << p->regshift));
142 /* Make sure LCR write wasn't ignored */
143 if (offset == UART_LCR) {
146 unsigned int lcr = p->serial_in(p, UART_LCR);
147 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
149 dw8250_force_idle(p);
150 __raw_writeq(value & 0xff,
151 p->membase + (UART_LCR << p->regshift));
154 * FIXME: this deadlocks if port->lock is already held
155 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
159 #endif /* CONFIG_64BIT */
161 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
163 writel(value, p->membase + (offset << p->regshift));
165 /* Make sure LCR write wasn't ignored */
166 if (offset == UART_LCR) {
169 unsigned int lcr = p->serial_in(p, UART_LCR);
170 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
172 dw8250_force_idle(p);
173 writel(value, p->membase + (UART_LCR << p->regshift));
176 * FIXME: this deadlocks if port->lock is already held
177 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
182 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
184 unsigned int value = readl(p->membase + (offset << p->regshift));
186 return dw8250_modify_msr(p, offset, value);
189 static int dw8250_handle_irq(struct uart_port *p)
191 struct dw8250_data *d = p->private_data;
192 unsigned int iir = p->serial_in(p, UART_IIR);
194 if (serial8250_handle_irq(p, iir)) {
196 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
198 (void)p->serial_in(p, d->usr_reg);
207 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
210 pm_runtime_get_sync(port->dev);
212 serial8250_do_pm(port, state, old);
215 pm_runtime_put_sync_suspend(port->dev);
218 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
219 struct ktermios *old)
221 unsigned int baud = tty_termios_baud_rate(termios);
222 struct dw8250_data *d = p->private_data;
226 if (IS_ERR(d->clk) || !old)
229 /* Not requesting clock rates below 1.8432Mhz */
233 clk_disable_unprepare(d->clk);
234 rate = clk_round_rate(d->clk, baud * 16);
235 ret = clk_set_rate(d->clk, rate);
236 clk_prepare_enable(d->clk);
241 p->status &= ~UPSTAT_AUTOCTS;
242 if (termios->c_cflag & CRTSCTS)
243 p->status |= UPSTAT_AUTOCTS;
246 serial8250_do_set_termios(p, termios, old);
249 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
254 static void dw8250_setup_port(struct uart_8250_port *up)
256 struct uart_port *p = &up->port;
257 u32 reg = readl(p->membase + DW_UART_UCV);
260 * If the Component Version Register returns zero, we know that
261 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
266 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
267 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
269 reg = readl(p->membase + DW_UART_CPR);
273 /* Select the type based on fifo */
274 if (reg & DW_UART_CPR_FIFO_MODE) {
275 p->type = PORT_16550A;
276 p->flags |= UPF_FIXED_TYPE;
277 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
278 up->tx_loadsz = p->fifosize;
279 up->capabilities = UART_CAP_FIFO;
282 if (reg & DW_UART_CPR_AFCE_MODE)
283 up->capabilities |= UART_CAP_AFE;
286 static int dw8250_probe_of(struct uart_port *p,
287 struct dw8250_data *data)
289 struct device_node *np = p->dev->of_node;
293 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
294 p->serial_in = dw8250_serial_inq;
295 p->serial_out = dw8250_serial_outq;
296 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
297 p->type = PORT_OCTEON;
298 data->usr_reg = 0x27;
299 data->skip_autocfg = true;
302 /* get index of serial line, if found in DT aliases */
303 id = of_alias_get_id(np, "serial");
310 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
312 struct device *dev = param;
314 if (dev != chan->device->dev->parent)
320 static int dw8250_probe_acpi(struct uart_8250_port *up,
321 struct dw8250_data *data)
323 struct uart_port *p = &up->port;
325 p->iotype = UPIO_MEM32;
326 p->serial_in = dw8250_serial_in32;
327 p->serial_out = dw8250_serial_out32;
330 /* Platforms with iDMA */
331 if (platform_get_resource_byname(to_platform_device(up->port.dev),
332 IORESOURCE_MEM, "lpss_priv")) {
333 data->dma.rx_param = up->port.dev->parent;
334 data->dma.tx_param = up->port.dev->parent;
335 data->dma.fn = dw8250_idma_filter;
338 up->port.set_termios = dw8250_set_termios;
343 static int dw8250_probe(struct platform_device *pdev)
345 struct uart_8250_port uart = {};
346 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
347 int irq = platform_get_irq(pdev, 0);
348 struct uart_port *p = &uart.port;
349 struct dw8250_data *data;
354 dev_err(&pdev->dev, "no registers defined\n");
359 if (irq != -EPROBE_DEFER)
360 dev_err(&pdev->dev, "cannot get irq\n");
364 spin_lock_init(&p->lock);
365 p->mapbase = regs->start;
367 p->handle_irq = dw8250_handle_irq;
368 p->pm = dw8250_do_pm;
370 p->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
372 p->iotype = UPIO_MEM;
373 p->serial_in = dw8250_serial_in;
374 p->serial_out = dw8250_serial_out;
376 p->membase = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
380 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
384 data->usr_reg = DW_UART_USR;
385 p->private_data = data;
387 err = device_property_read_u32(p->dev, "reg-shift", &val);
391 err = device_property_read_u32(p->dev, "reg-io-width", &val);
392 if (!err && val == 4) {
393 p->iotype = UPIO_MEM32;
394 p->serial_in = dw8250_serial_in32;
395 p->serial_out = dw8250_serial_out32;
398 if (device_property_read_bool(p->dev, "dcd-override")) {
399 /* Always report DCD as active */
400 data->msr_mask_on |= UART_MSR_DCD;
401 data->msr_mask_off |= UART_MSR_DDCD;
404 if (device_property_read_bool(p->dev, "dsr-override")) {
405 /* Always report DSR as active */
406 data->msr_mask_on |= UART_MSR_DSR;
407 data->msr_mask_off |= UART_MSR_DDSR;
410 if (device_property_read_bool(p->dev, "cts-override")) {
411 /* Always report CTS as active */
412 data->msr_mask_on |= UART_MSR_CTS;
413 data->msr_mask_off |= UART_MSR_DCTS;
416 if (device_property_read_bool(p->dev, "ri-override")) {
417 /* Always report Ring indicator as inactive */
418 data->msr_mask_off |= UART_MSR_RI;
419 data->msr_mask_off |= UART_MSR_TERI;
422 /* Always ask for fixed clock rate from a property. */
423 device_property_read_u32(p->dev, "clock-frequency", &p->uartclk);
425 /* If there is separate baudclk, get the rate from it. */
426 data->clk = devm_clk_get(&pdev->dev, "baudclk");
427 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
428 data->clk = devm_clk_get(&pdev->dev, NULL);
429 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
430 return -EPROBE_DEFER;
431 if (!IS_ERR_OR_NULL(data->clk)) {
432 err = clk_prepare_enable(data->clk);
434 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
437 p->uartclk = clk_get_rate(data->clk);
440 /* If no clock rate is defined, fail. */
442 dev_err(&pdev->dev, "clock rate not defined\n");
446 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
447 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
451 if (!IS_ERR(data->pclk)) {
452 err = clk_prepare_enable(data->pclk);
454 dev_err(&pdev->dev, "could not enable apb_pclk\n");
459 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
460 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
464 if (!IS_ERR(data->rst))
465 reset_control_deassert(data->rst);
467 data->dma.rx_param = data;
468 data->dma.tx_param = data;
469 data->dma.fn = dw8250_dma_filter;
471 if (pdev->dev.of_node) {
472 err = dw8250_probe_of(p, data);
475 } else if (ACPI_HANDLE(&pdev->dev)) {
476 err = dw8250_probe_acpi(&uart, data);
484 if (!data->skip_autocfg)
485 dw8250_setup_port(&uart);
487 /* If we have a valid fifosize, try hooking up DMA */
489 data->dma.rxconf.src_maxburst = p->fifosize / 4;
490 data->dma.txconf.dst_maxburst = p->fifosize / 4;
491 uart.dma = &data->dma;
494 data->line = serial8250_register_8250_port(&uart);
495 if (data->line < 0) {
500 platform_set_drvdata(pdev, data);
502 pm_runtime_set_active(&pdev->dev);
503 pm_runtime_enable(&pdev->dev);
508 if (!IS_ERR(data->rst))
509 reset_control_assert(data->rst);
512 if (!IS_ERR(data->pclk))
513 clk_disable_unprepare(data->pclk);
516 if (!IS_ERR(data->clk))
517 clk_disable_unprepare(data->clk);
522 static int dw8250_remove(struct platform_device *pdev)
524 struct dw8250_data *data = platform_get_drvdata(pdev);
526 pm_runtime_get_sync(&pdev->dev);
528 serial8250_unregister_port(data->line);
530 if (!IS_ERR(data->rst))
531 reset_control_assert(data->rst);
533 if (!IS_ERR(data->pclk))
534 clk_disable_unprepare(data->pclk);
536 if (!IS_ERR(data->clk))
537 clk_disable_unprepare(data->clk);
539 pm_runtime_disable(&pdev->dev);
540 pm_runtime_put_noidle(&pdev->dev);
545 #ifdef CONFIG_PM_SLEEP
546 static int dw8250_suspend(struct device *dev)
548 struct dw8250_data *data = dev_get_drvdata(dev);
550 serial8250_suspend_port(data->line);
555 static int dw8250_resume(struct device *dev)
557 struct dw8250_data *data = dev_get_drvdata(dev);
559 serial8250_resume_port(data->line);
563 #endif /* CONFIG_PM_SLEEP */
566 static int dw8250_runtime_suspend(struct device *dev)
568 struct dw8250_data *data = dev_get_drvdata(dev);
570 if (!IS_ERR(data->clk))
571 clk_disable_unprepare(data->clk);
573 if (!IS_ERR(data->pclk))
574 clk_disable_unprepare(data->pclk);
579 static int dw8250_runtime_resume(struct device *dev)
581 struct dw8250_data *data = dev_get_drvdata(dev);
583 if (!IS_ERR(data->pclk))
584 clk_prepare_enable(data->pclk);
586 if (!IS_ERR(data->clk))
587 clk_prepare_enable(data->clk);
593 static const struct dev_pm_ops dw8250_pm_ops = {
594 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
595 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
598 static const struct of_device_id dw8250_of_match[] = {
599 { .compatible = "snps,dw-apb-uart" },
600 { .compatible = "cavium,octeon-3860-uart" },
603 MODULE_DEVICE_TABLE(of, dw8250_of_match);
605 static const struct acpi_device_id dw8250_acpi_match[] = {
616 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
618 static struct platform_driver dw8250_platform_driver = {
620 .name = "dw-apb-uart",
621 .pm = &dw8250_pm_ops,
622 .of_match_table = dw8250_of_match,
623 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
625 .probe = dw8250_probe,
626 .remove = dw8250_remove,
629 module_platform_driver(dw8250_platform_driver);
631 MODULE_AUTHOR("Jamie Iles");
632 MODULE_LICENSE("GPL");
633 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
634 MODULE_ALIAS("platform:dw-apb-uart");