2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 #include <linux/rational.h>
26 #include <asm/byteorder.h>
29 #include <linux/dmaengine.h>
30 #include <linux/platform_data/dma-dw.h>
35 * init function returns:
36 * > 0 - number of ports
37 * = 0 - use board->num_ports
40 struct pci_serial_quirk {
45 int (*probe)(struct pci_dev *dev);
46 int (*init)(struct pci_dev *dev);
47 int (*setup)(struct serial_private *,
48 const struct pciserial_board *,
49 struct uart_8250_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static int pci_default_setup(struct serial_private*,
64 const struct pciserial_board*, struct uart_8250_port *, int);
66 static void moan_device(const char *str, struct pci_dev *dev)
70 "Please send the output of lspci -vv, this\n"
71 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
72 "manufacturer and name of serial board or\n"
73 "modem board to <linux-serial@vger.kernel.org>.\n",
74 pci_name(dev), str, dev->vendor, dev->device,
75 dev->subsystem_vendor, dev->subsystem_device);
79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
80 int bar, int offset, int regshift)
82 struct pci_dev *dev = priv->dev;
84 if (bar >= PCI_NUM_BAR_RESOURCES)
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
90 if (!priv->remapped_bar[bar])
93 port->port.iotype = UPIO_MEM;
94 port->port.iobase = 0;
95 port->port.mapbase = pci_resource_start(dev, bar) + offset;
96 port->port.membase = priv->remapped_bar[bar] + offset;
97 port->port.regshift = regshift;
99 port->port.iotype = UPIO_PORT;
100 port->port.iobase = pci_resource_start(dev, bar) + offset;
101 port->port.mapbase = 0;
102 port->port.membase = NULL;
103 port->port.regshift = 0;
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_8250_port *port, int idx)
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
128 offset += ((idx - 6) * board->uart_offset);
131 return setup_port(priv, port, bar, offset, board->reg_shift);
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_8250_port *port, int idx)
142 unsigned int bar, offset = board->first_offset;
144 bar = FL_GET_BASE(board->flags);
149 offset += (idx - 4) * board->uart_offset;
152 return setup_port(priv, port, bar, offset, board->reg_shift);
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
162 static int pci_hp_diva_init(struct pci_dev *dev)
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
193 pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_8250_port *port, int idx)
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
215 offset += idx * board->uart_offset;
217 return setup_port(priv, port, bar, offset, board->reg_shift);
221 * Added for EKF Intel i960 serial boards
223 static int pci_inteli960ni_init(struct pci_dev *dev)
227 if (!(dev->subsystem_device & 0x1000))
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, &oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
245 static int pci_plx9050_init(struct pci_dev *dev)
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
272 * enable/disable interrupts
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 writel(irq_config, p + 0x4c);
280 * Read the register back to ensure that it took effect.
288 static void pci_plx9050_exit(struct pci_dev *dev)
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
303 * Read the register back to ensure that it took effect.
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
313 static void pci_ni8420_exit(struct pci_dev *dev)
316 unsigned int bar = 0;
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
323 p = pci_ioremap_bar(dev, bar);
327 /* Disable the CPU Interrupt */
328 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
329 p + NI8420_INT_ENABLE_REG);
335 #define MITE_IOWBSR1 0xc4
336 #define MITE_IOWCR1 0xf4
337 #define MITE_LCIMR1 0x08
338 #define MITE_LCIMR2 0x10
340 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342 static void pci_ni8430_exit(struct pci_dev *dev)
345 unsigned int bar = 0;
347 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
348 moan_device("no memory in bar", dev);
352 p = pci_ioremap_bar(dev, bar);
356 /* Disable the CPU Interrupt */
357 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
361 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
364 struct uart_8250_port *port, int idx)
366 unsigned int bar, offset = board->first_offset;
371 /* first four channels map to 0, 0x100, 0x200, 0x300 */
372 offset += idx * board->uart_offset;
373 } else if (idx < 8) {
374 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
375 offset += idx * board->uart_offset + 0xC00;
376 } else /* we have only 8 ports on PMC-OCTALPRO */
379 return setup_port(priv, port, bar, offset, board->reg_shift);
383 * This does initialization for PMC OCTALPRO cards:
384 * maps the device memory, resets the UARTs (needed, bc
385 * if the module is removed and inserted again, the card
386 * is in the sleep mode) and enables global interrupt.
389 /* global control register offset for SBS PMC-OctalPro */
390 #define OCT_REG_CR_OFF 0x500
392 static int sbs_init(struct pci_dev *dev)
396 p = pci_ioremap_bar(dev, 0);
400 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
401 writeb(0x10, p + OCT_REG_CR_OFF);
403 writeb(0x0, p + OCT_REG_CR_OFF);
405 /* Set bit-2 (INTENABLE) of Control Register */
406 writeb(0x4, p + OCT_REG_CR_OFF);
413 * Disables the global interrupt of PMC-OctalPro
416 static void sbs_exit(struct pci_dev *dev)
420 p = pci_ioremap_bar(dev, 0);
421 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 writeb(0, p + OCT_REG_CR_OFF);
428 * SIIG serial cards have an PCI interface chip which also controls
429 * the UART clocking frequency. Each UART can be clocked independently
430 * (except cards equipped with 4 UARTs) and initial clocking settings
431 * are stored in the EEPROM chip. It can cause problems because this
432 * version of serial driver doesn't support differently clocked UART's
433 * on single PCI card. To prevent this, initialization functions set
434 * high frequency clocking for all UART's on given card. It is safe (I
435 * hope) because it doesn't touch EEPROM settings to prevent conflicts
436 * with other OSes (like M$ DOS).
438 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
440 * There is two family of SIIG serial cards with different PCI
441 * interface chip and different configuration methods:
442 * - 10x cards have control registers in IO and/or memory space;
443 * - 20x cards have control registers in standard PCI configuration space.
445 * Note: all 10x cards have PCI device ids 0x10..
446 * all 20x cards have PCI device ids 0x20..
448 * There are also Quartet Serial cards which use Oxford Semiconductor
449 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 * Note: some SIIG cards are probed by the parport_serial object.
454 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
455 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457 static int pci_siig10x_init(struct pci_dev *dev)
462 switch (dev->device & 0xfff8) {
463 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
466 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
469 default: /* 1S1P, 4S */
474 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
478 writew(readw(p + 0x28) & data, p + 0x28);
484 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
485 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487 static int pci_siig20x_init(struct pci_dev *dev)
491 /* Change clock frequency for the first UART. */
492 pci_read_config_byte(dev, 0x6f, &data);
493 pci_write_config_byte(dev, 0x6f, data & 0xef);
495 /* If this card has 2 UART, we have to do the same with second UART. */
496 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
497 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
498 pci_read_config_byte(dev, 0x73, &data);
499 pci_write_config_byte(dev, 0x73, data & 0xef);
504 static int pci_siig_init(struct pci_dev *dev)
506 unsigned int type = dev->device & 0xff00;
509 return pci_siig10x_init(dev);
510 else if (type == 0x2000)
511 return pci_siig20x_init(dev);
513 moan_device("Unknown SIIG card", dev);
517 static int pci_siig_setup(struct serial_private *priv,
518 const struct pciserial_board *board,
519 struct uart_8250_port *port, int idx)
521 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
525 offset = (idx - 4) * 8;
528 return setup_port(priv, port, bar, offset, 0);
532 * Timedia has an explosion of boards, and to avoid the PCI table from
533 * growing *huge*, we use this function to collapse some 70 entries
534 * in the PCI table into one, for sanity's and compactness's sake.
536 static const unsigned short timedia_single_port[] = {
537 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
540 static const unsigned short timedia_dual_port[] = {
541 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
542 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
543 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
544 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
548 static const unsigned short timedia_quad_port[] = {
549 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
550 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
551 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
555 static const unsigned short timedia_eight_port[] = {
556 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
557 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
560 static const struct timedia_struct {
562 const unsigned short *ids;
564 { 1, timedia_single_port },
565 { 2, timedia_dual_port },
566 { 4, timedia_quad_port },
567 { 8, timedia_eight_port }
571 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
572 * listing them individually, this driver merely grabs them all with
573 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
574 * and should be left free to be claimed by parport_serial instead.
576 static int pci_timedia_probe(struct pci_dev *dev)
579 * Check the third digit of the subdevice ID
580 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 "ignoring Timedia subdevice %04x for parport_serial\n",
585 dev->subsystem_device);
592 static int pci_timedia_init(struct pci_dev *dev)
594 const unsigned short *ids;
597 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
598 ids = timedia_data[i].ids;
599 for (j = 0; ids[j]; j++)
600 if (dev->subsystem_device == ids[j])
601 return timedia_data[i].num;
607 * Timedia/SUNIX uses a mixture of BARs and offsets
608 * Ugh, this is ugly as all hell --- TYT
611 pci_timedia_setup(struct serial_private *priv,
612 const struct pciserial_board *board,
613 struct uart_8250_port *port, int idx)
615 unsigned int bar = 0, offset = board->first_offset;
622 offset = board->uart_offset;
629 offset = board->uart_offset;
638 return setup_port(priv, port, bar, offset, board->reg_shift);
642 * Some Titan cards are also a little weird
645 titan_400l_800l_setup(struct serial_private *priv,
646 const struct pciserial_board *board,
647 struct uart_8250_port *port, int idx)
649 unsigned int bar, offset = board->first_offset;
660 offset = (idx - 2) * board->uart_offset;
663 return setup_port(priv, port, bar, offset, board->reg_shift);
666 static int pci_xircom_init(struct pci_dev *dev)
672 static int pci_ni8420_init(struct pci_dev *dev)
675 unsigned int bar = 0;
677 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
678 moan_device("no memory in bar", dev);
682 p = pci_ioremap_bar(dev, bar);
686 /* Enable CPU Interrupt */
687 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
688 p + NI8420_INT_ENABLE_REG);
694 #define MITE_IOWBSR1_WSIZE 0xa
695 #define MITE_IOWBSR1_WIN_OFFSET 0x800
696 #define MITE_IOWBSR1_WENAB (1 << 7)
697 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
698 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
699 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701 static int pci_ni8430_init(struct pci_dev *dev)
704 struct pci_bus_region region;
706 unsigned int bar = 0;
708 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
709 moan_device("no memory in bar", dev);
713 p = pci_ioremap_bar(dev, bar);
718 * Set device window address and size in BAR0, while acknowledging that
719 * the resource structure may contain a translated address that differs
720 * from the address the device responds to.
722 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
723 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
724 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
725 writel(device_window, p + MITE_IOWBSR1);
727 /* Set window access to go to RAMSEL IO address space */
728 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
731 /* Enable IO Bus Interrupt 0 */
732 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734 /* Enable CPU Interrupt */
735 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
741 /* UART Port Control Register */
742 #define NI8430_PORTCON 0x0f
743 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
746 pci_ni8430_setup(struct serial_private *priv,
747 const struct pciserial_board *board,
748 struct uart_8250_port *port, int idx)
750 struct pci_dev *dev = priv->dev;
752 unsigned int bar, offset = board->first_offset;
754 if (idx >= board->num_ports)
757 bar = FL_GET_BASE(board->flags);
758 offset += idx * board->uart_offset;
760 p = pci_ioremap_bar(dev, bar);
764 /* enable the transceiver */
765 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
766 p + offset + NI8430_PORTCON);
770 return setup_port(priv, port, bar, offset, board->reg_shift);
773 static int pci_netmos_9900_setup(struct serial_private *priv,
774 const struct pciserial_board *board,
775 struct uart_8250_port *port, int idx)
779 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
780 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
781 /* netmos apparently orders BARs by datasheet layout, so serial
782 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
786 return setup_port(priv, port, bar, 0, board->reg_shift);
788 return pci_default_setup(priv, board, port, idx);
792 /* the 99xx series comes with a range of device IDs and a variety
795 * 9900 has varying capabilities and can cascade to sub-controllers
796 * (cascading should be purely internal)
797 * 9904 is hardwired with 4 serial ports
798 * 9912 and 9922 are hardwired with 2 serial ports
800 static int pci_netmos_9900_numports(struct pci_dev *dev)
802 unsigned int c = dev->class;
804 unsigned short sub_serports;
811 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
812 /* two possibilities: 0x30ps encodes number of parallel and
813 * serial ports, or 0x1000 indicates *something*. This is not
814 * immediately obvious, since the 2s1p+4s configuration seems
815 * to offer all functionality on functions 0..2, while still
816 * advertising the same function 3 as the 4s+2s1p config.
818 sub_serports = dev->subsystem_device & 0xf;
819 if (sub_serports > 0)
823 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
827 moan_device("unknown NetMos/Mostech program interface", dev);
831 static int pci_netmos_init(struct pci_dev *dev)
833 /* subdevice 0x00PS means <P> parallel, <S> serial */
834 unsigned int num_serial = dev->subsystem_device & 0xf;
836 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
837 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
840 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
841 dev->subsystem_device == 0x0299)
844 switch (dev->device) { /* FALLTHROUGH on all */
845 case PCI_DEVICE_ID_NETMOS_9904:
846 case PCI_DEVICE_ID_NETMOS_9912:
847 case PCI_DEVICE_ID_NETMOS_9922:
848 case PCI_DEVICE_ID_NETMOS_9900:
849 num_serial = pci_netmos_9900_numports(dev);
856 if (num_serial == 0) {
857 moan_device("unknown NetMos/Mostech device", dev);
865 * These chips are available with optionally one parallel port and up to
866 * two serial ports. Unfortunately they all have the same product id.
868 * Basic configuration is done over a region of 32 I/O ports. The base
869 * ioport is called INTA or INTC, depending on docs/other drivers.
871 * The region of the 32 I/O ports is configured in POSIO0R...
875 #define ITE_887x_MISCR 0x9c
876 #define ITE_887x_INTCBAR 0x78
877 #define ITE_887x_UARTBAR 0x7c
878 #define ITE_887x_PS0BAR 0x10
879 #define ITE_887x_POSIO0 0x60
882 #define ITE_887x_IOSIZE 32
883 /* I/O space size (bits 26-24; 8 bytes = 011b) */
884 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
885 /* I/O space size (bits 26-24; 32 bytes = 101b) */
886 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
887 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
888 #define ITE_887x_POSIO_SPEED (3 << 29)
889 /* enable IO_Space bit */
890 #define ITE_887x_POSIO_ENABLE (1 << 31)
892 static int pci_ite887x_init(struct pci_dev *dev)
894 /* inta_addr are the configuration addresses of the ITE */
895 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
898 struct resource *iobase = NULL;
899 u32 miscr, uartbar, ioport;
901 /* search for the base-ioport */
903 while (inta_addr[i] && iobase == NULL) {
904 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 if (iobase != NULL) {
907 /* write POSIO0R - speed | size | ioport */
908 pci_write_config_dword(dev, ITE_887x_POSIO0,
909 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
910 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
911 /* write INTCBAR - ioport */
912 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 ret = inb(inta_addr[i]);
916 /* ioport connected */
919 release_region(iobase->start, ITE_887x_IOSIZE);
926 dev_err(&dev->dev, "ite887x: could not find iobase\n");
930 /* start of undocumented type checking (see parport_pc.c) */
931 type = inb(iobase->start + 0x18) & 0x0f;
934 case 0x2: /* ITE8871 (1P) */
935 case 0xa: /* ITE8875 (1P) */
938 case 0xe: /* ITE8872 (2S1P) */
941 case 0x6: /* ITE8873 (1S) */
944 case 0x8: /* ITE8874 (2S) */
948 moan_device("Unknown ITE887x", dev);
952 /* configure all serial ports */
953 for (i = 0; i < ret; i++) {
954 /* read the I/O port from the device */
955 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 ioport &= 0x0000FF00; /* the actual base address */
958 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
959 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
960 ITE_887x_POSIO_IOSIZE_8 | ioport);
962 /* write the ioport to the UARTBAR */
963 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
964 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
965 uartbar |= (ioport << (16 * i)); /* set the ioport */
966 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968 /* get current config */
969 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
970 /* disable interrupts (UARTx_Routing[3:0]) */
971 miscr &= ~(0xf << (12 - 4 * i));
972 /* activate the UART (UARTx_En) */
973 miscr |= 1 << (23 - i);
974 /* write new config with activated UART */
975 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
979 /* the device has no UARTs if we get here */
980 release_region(iobase->start, ITE_887x_IOSIZE);
986 static void pci_ite887x_exit(struct pci_dev *dev)
989 /* the ioport is bit 0-15 in POSIO0R */
990 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 release_region(ioport, ITE_887x_IOSIZE);
996 * EndRun Technologies.
997 * Determine the number of ports available on the device.
999 #define PCI_VENDOR_ID_ENDRUN 0x7401
1000 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002 static int pci_endrun_init(struct pci_dev *dev)
1005 unsigned long deviceID;
1006 unsigned int number_uarts = 0;
1008 /* EndRun device is all 0xexxx */
1009 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1010 (dev->device & 0xf000) != 0xe000)
1013 p = pci_iomap(dev, 0, 5);
1017 deviceID = ioread32(p);
1019 if (deviceID == 0x07000200) {
1020 number_uarts = ioread8(p + 4);
1022 "%d ports detected on EndRun PCI Express device\n",
1025 pci_iounmap(dev, p);
1026 return number_uarts;
1030 * Oxford Semiconductor Inc.
1031 * Check that device is part of the Tornado range of devices, then determine
1032 * the number of ports available on the device.
1034 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1037 unsigned long deviceID;
1038 unsigned int number_uarts = 0;
1040 /* OxSemi Tornado devices are all 0xCxxx */
1041 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1042 (dev->device & 0xF000) != 0xC000)
1045 p = pci_iomap(dev, 0, 5);
1049 deviceID = ioread32(p);
1050 /* Tornado device */
1051 if (deviceID == 0x07000200) {
1052 number_uarts = ioread8(p + 4);
1054 "%d ports detected on Oxford PCI Express device\n",
1057 pci_iounmap(dev, p);
1058 return number_uarts;
1061 static int pci_asix_setup(struct serial_private *priv,
1062 const struct pciserial_board *board,
1063 struct uart_8250_port *port, int idx)
1065 port->bugs |= UART_BUG_PARITY;
1066 return pci_default_setup(priv, board, port, idx);
1069 /* Quatech devices have their own extra interface features */
1071 struct quatech_feature {
1076 #define QPCR_TEST_FOR1 0x3F
1077 #define QPCR_TEST_GET1 0x00
1078 #define QPCR_TEST_FOR2 0x40
1079 #define QPCR_TEST_GET2 0x40
1080 #define QPCR_TEST_FOR3 0x80
1081 #define QPCR_TEST_GET3 0x40
1082 #define QPCR_TEST_FOR4 0xC0
1083 #define QPCR_TEST_GET4 0x80
1085 #define QOPR_CLOCK_X1 0x0000
1086 #define QOPR_CLOCK_X2 0x0001
1087 #define QOPR_CLOCK_X4 0x0002
1088 #define QOPR_CLOCK_X8 0x0003
1089 #define QOPR_CLOCK_RATE_MASK 0x0003
1092 static struct quatech_feature quatech_cards[] = {
1093 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1100 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1115 static int pci_quatech_amcc(u16 devid)
1117 struct quatech_feature *qf = &quatech_cards[0];
1119 if (qf->devid == devid)
1123 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1127 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 unsigned long base = port->port.iobase;
1132 LCR = inb(base + UART_LCR);
1133 outb(0xBF, base + UART_LCR);
1134 val = inb(base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1139 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 unsigned long base = port->port.iobase;
1144 LCR = inb(base + UART_LCR);
1145 outb(0xBF, base + UART_LCR);
1146 val = inb(base + UART_SCR);
1147 outb(qopr, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1151 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 unsigned long base = port->port.iobase;
1156 LCR = inb(base + UART_LCR);
1157 outb(0xBF, base + UART_LCR);
1158 val = inb(base + UART_SCR);
1159 outb(val | 0x10, base + UART_SCR);
1160 qmcr = inb(base + UART_MCR);
1161 outb(val, base + UART_SCR);
1162 outb(LCR, base + UART_LCR);
1167 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 unsigned long base = port->port.iobase;
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1175 outb(val | 0x10, base + UART_SCR);
1176 outb(qmcr, base + UART_MCR);
1177 outb(val, base + UART_SCR);
1178 outb(LCR, base + UART_LCR);
1181 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 unsigned long base = port->port.iobase;
1186 LCR = inb(base + UART_LCR);
1187 outb(0xBF, base + UART_LCR);
1188 val = inb(base + UART_SCR);
1190 outb(0x80, UART_LCR);
1191 if (!(inb(UART_SCR) & 0x20)) {
1192 outb(LCR, base + UART_LCR);
1199 static int pci_quatech_test(struct uart_8250_port *port)
1203 qopr = pci_quatech_rqopr(port);
1204 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205 reg = pci_quatech_rqopr(port) & 0xC0;
1206 if (reg != QPCR_TEST_GET1)
1208 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209 reg = pci_quatech_rqopr(port) & 0xC0;
1210 if (reg != QPCR_TEST_GET2)
1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET3)
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET4)
1221 pci_quatech_wqopr(port, qopr);
1225 static int pci_quatech_clock(struct uart_8250_port *port)
1228 unsigned long clock;
1230 if (pci_quatech_test(port) < 0)
1233 qopr = pci_quatech_rqopr(port);
1235 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (reg & QOPR_CLOCK_X8) {
1241 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242 reg = pci_quatech_rqopr(port);
1243 if (!(reg & QOPR_CLOCK_X8)) {
1247 reg &= QOPR_CLOCK_X8;
1248 if (reg == QOPR_CLOCK_X2) {
1250 set = QOPR_CLOCK_X2;
1251 } else if (reg == QOPR_CLOCK_X4) {
1253 set = QOPR_CLOCK_X4;
1254 } else if (reg == QOPR_CLOCK_X8) {
1256 set = QOPR_CLOCK_X8;
1259 set = QOPR_CLOCK_X1;
1261 qopr &= ~QOPR_CLOCK_RATE_MASK;
1265 pci_quatech_wqopr(port, qopr);
1269 static int pci_quatech_rs422(struct uart_8250_port *port)
1274 if (!pci_quatech_has_qmcr(port))
1276 qmcr = pci_quatech_rqmcr(port);
1277 pci_quatech_wqmcr(port, 0xFF);
1278 if (pci_quatech_rqmcr(port))
1280 pci_quatech_wqmcr(port, qmcr);
1284 static int pci_quatech_init(struct pci_dev *dev)
1286 if (pci_quatech_amcc(dev->device)) {
1287 unsigned long base = pci_resource_start(dev, 0);
1291 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1292 tmp = inl(base + 0x3c);
1293 outl(tmp | 0x01000000, base + 0x3c);
1294 outl(tmp &= ~0x01000000, base + 0x3c);
1300 static int pci_quatech_setup(struct serial_private *priv,
1301 const struct pciserial_board *board,
1302 struct uart_8250_port *port, int idx)
1304 /* Needed by pci_quatech calls below */
1305 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1306 /* Set up the clocking */
1307 port->port.uartclk = pci_quatech_clock(port);
1308 /* For now just warn about RS422 */
1309 if (pci_quatech_rs422(port))
1310 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1311 return pci_default_setup(priv, board, port, idx);
1314 static void pci_quatech_exit(struct pci_dev *dev)
1318 static int pci_default_setup(struct serial_private *priv,
1319 const struct pciserial_board *board,
1320 struct uart_8250_port *port, int idx)
1322 unsigned int bar, offset = board->first_offset, maxnr;
1324 bar = FL_GET_BASE(board->flags);
1325 if (board->flags & FL_BASE_BARS)
1328 offset += idx * board->uart_offset;
1330 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1331 (board->reg_shift + 3);
1333 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1336 return setup_port(priv, port, bar, offset, board->reg_shift);
1340 ce4100_serial_setup(struct serial_private *priv,
1341 const struct pciserial_board *board,
1342 struct uart_8250_port *port, int idx)
1346 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1347 port->port.iotype = UPIO_MEM32;
1348 port->port.type = PORT_XSCALE;
1349 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1350 port->port.regshift = 2;
1355 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1356 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1358 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1359 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1361 #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
1362 #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
1364 #define BYT_PRV_CLK 0x800
1365 #define BYT_PRV_CLK_EN (1 << 0)
1366 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1367 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1368 #define BYT_PRV_CLK_UPDATE (1 << 31)
1370 #define BYT_TX_OVF_INT 0x820
1371 #define BYT_TX_OVF_INT_MASK (1 << 1)
1374 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1375 struct ktermios *old)
1377 unsigned int baud = tty_termios_baud_rate(termios);
1378 unsigned long fref = 100000000, fuart = baud * 16;
1379 unsigned long w = BIT(15) - 1;
1383 /* Get Fuart closer to Fref */
1384 fuart *= rounddown_pow_of_two(fref / fuart);
1387 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1388 * dividers must be adjusted.
1390 * uartclk = (m / n) * 100 MHz, where m <= n
1392 rational_best_approximation(fuart, fref, w, w, &m, &n);
1395 /* Reset the clock */
1396 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1397 writel(reg, p->membase + BYT_PRV_CLK);
1398 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1399 writel(reg, p->membase + BYT_PRV_CLK);
1401 p->status &= ~UPSTAT_AUTOCTS;
1402 if (termios->c_cflag & CRTSCTS)
1403 p->status |= UPSTAT_AUTOCTS;
1405 serial8250_do_set_termios(p, termios, old);
1408 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1410 struct dw_dma_slave *dws = param;
1412 if (dws->dma_dev != chan->device->dev)
1415 chan->private = dws;
1420 byt_serial_setup(struct serial_private *priv,
1421 const struct pciserial_board *board,
1422 struct uart_8250_port *port, int idx)
1424 struct pci_dev *pdev = priv->dev;
1425 struct device *dev = port->port.dev;
1426 struct uart_8250_dma *dma;
1427 struct dw_dma_slave *tx_param, *rx_param;
1428 struct pci_dev *dma_dev;
1431 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1435 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1439 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1443 switch (pdev->device) {
1444 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1445 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1446 case PCI_DEVICE_ID_INTEL_BDW_UART1:
1447 rx_param->src_id = 3;
1448 tx_param->dst_id = 2;
1450 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1451 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1452 case PCI_DEVICE_ID_INTEL_BDW_UART2:
1453 rx_param->src_id = 5;
1454 tx_param->dst_id = 4;
1460 rx_param->src_master = 1;
1461 rx_param->dst_master = 0;
1463 dma->rxconf.src_maxburst = 16;
1465 tx_param->src_master = 1;
1466 tx_param->dst_master = 0;
1468 dma->txconf.dst_maxburst = 16;
1470 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1471 rx_param->dma_dev = &dma_dev->dev;
1472 tx_param->dma_dev = &dma_dev->dev;
1474 dma->fn = byt_dma_filter;
1475 dma->rx_param = rx_param;
1476 dma->tx_param = tx_param;
1478 ret = pci_default_setup(priv, board, port, idx);
1479 port->port.iotype = UPIO_MEM;
1480 port->port.type = PORT_16550A;
1481 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1482 port->port.set_termios = byt_set_termios;
1483 port->port.fifosize = 64;
1484 port->tx_loadsz = 64;
1486 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1488 /* Disable Tx counter interrupts */
1489 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1495 pci_omegapci_setup(struct serial_private *priv,
1496 const struct pciserial_board *board,
1497 struct uart_8250_port *port, int idx)
1499 return setup_port(priv, port, 2, idx * 8, 0);
1503 pci_brcm_trumanage_setup(struct serial_private *priv,
1504 const struct pciserial_board *board,
1505 struct uart_8250_port *port, int idx)
1507 int ret = pci_default_setup(priv, board, port, idx);
1509 port->port.type = PORT_BRCM_TRUMANAGE;
1510 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1514 /* RTS will control by MCR if this bit is 0 */
1515 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1516 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1517 #define FINTEK_RTS_INVERT BIT(5)
1519 /* We should do proper H/W transceiver setting before change to RS485 mode */
1520 static int pci_fintek_rs485_config(struct uart_port *port,
1521 struct serial_rs485 *rs485)
1523 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1525 u8 *index = (u8 *) port->private_data;
1527 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1530 rs485 = &port->rs485;
1531 else if (rs485->flags & SER_RS485_ENABLED)
1532 memset(rs485->padding, 0, sizeof(rs485->padding));
1534 memset(rs485, 0, sizeof(*rs485));
1536 /* F81504/508/512 not support RTS delay before or after send */
1537 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1539 if (rs485->flags & SER_RS485_ENABLED) {
1540 /* Enable RTS H/W control mode */
1541 setting |= FINTEK_RTS_CONTROL_BY_HW;
1543 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1544 /* RTS driving high on TX */
1545 setting &= ~FINTEK_RTS_INVERT;
1547 /* RTS driving low on TX */
1548 setting |= FINTEK_RTS_INVERT;
1551 rs485->delay_rts_after_send = 0;
1552 rs485->delay_rts_before_send = 0;
1554 /* Disable RTS H/W control mode */
1555 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1558 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1560 if (rs485 != &port->rs485)
1561 port->rs485 = *rs485;
1566 static int pci_fintek_setup(struct serial_private *priv,
1567 const struct pciserial_board *board,
1568 struct uart_8250_port *port, int idx)
1570 struct pci_dev *pdev = priv->dev;
1575 config_base = 0x40 + 0x08 * idx;
1577 /* Get the io address from configuration space */
1578 pci_read_config_word(pdev, config_base + 4, &iobase);
1580 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1582 port->port.iotype = UPIO_PORT;
1583 port->port.iobase = iobase;
1584 port->port.rs485_config = pci_fintek_rs485_config;
1586 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1590 /* preserve index in PCI configuration space */
1592 port->port.private_data = data;
1597 static int pci_fintek_init(struct pci_dev *dev)
1599 unsigned long iobase;
1603 struct serial_private *priv = pci_get_drvdata(dev);
1604 struct uart_8250_port *port;
1606 switch (dev->device) {
1607 case 0x1104: /* 4 ports */
1608 case 0x1108: /* 8 ports */
1609 max_port = dev->device & 0xff;
1611 case 0x1112: /* 12 ports */
1618 /* Get the io address dispatch from the BIOS */
1619 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1620 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1621 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1623 for (i = 0; i < max_port; ++i) {
1624 /* UART0 configuration offset start from 0x40 */
1625 config_base = 0x40 + 0x08 * i;
1627 /* Calculate Real IO Port */
1628 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1630 /* Enable UART I/O port */
1631 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1633 /* Select 128-byte FIFO and 8x FIFO threshold */
1634 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1637 pci_write_config_byte(dev, config_base + 0x04,
1638 (u8)(iobase & 0xff));
1641 pci_write_config_byte(dev, config_base + 0x05,
1642 (u8)((iobase & 0xff00) >> 8));
1644 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1647 /* re-apply RS232/485 mode when
1648 * pciserial_resume_ports()
1650 port = serial8250_get_port(priv->line[i]);
1651 pci_fintek_rs485_config(&port->port, NULL);
1653 /* First init without port data
1654 * force init to RS232 Mode
1656 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1663 static int skip_tx_en_setup(struct serial_private *priv,
1664 const struct pciserial_board *board,
1665 struct uart_8250_port *port, int idx)
1667 port->port.flags |= UPF_NO_TXEN_TEST;
1668 dev_dbg(&priv->dev->dev,
1669 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1670 priv->dev->vendor, priv->dev->device,
1671 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1673 return pci_default_setup(priv, board, port, idx);
1676 static void kt_handle_break(struct uart_port *p)
1678 struct uart_8250_port *up = up_to_u8250p(p);
1680 * On receipt of a BI, serial device in Intel ME (Intel
1681 * management engine) needs to have its fifos cleared for sane
1682 * SOL (Serial Over Lan) output.
1684 serial8250_clear_and_reinit_fifos(up);
1687 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1689 struct uart_8250_port *up = up_to_u8250p(p);
1693 * When the Intel ME (management engine) gets reset its serial
1694 * port registers could return 0 momentarily. Functions like
1695 * serial8250_console_write, read and save the IER, perform
1696 * some operation and then restore it. In order to avoid
1697 * setting IER register inadvertently to 0, if the value read
1698 * is 0, double check with ier value in uart_8250_port and use
1699 * that instead. up->ier should be the same value as what is
1700 * currently configured.
1702 val = inb(p->iobase + offset);
1703 if (offset == UART_IER) {
1710 static int kt_serial_setup(struct serial_private *priv,
1711 const struct pciserial_board *board,
1712 struct uart_8250_port *port, int idx)
1714 port->port.flags |= UPF_BUG_THRE;
1715 port->port.serial_in = kt_serial_in;
1716 port->port.handle_break = kt_handle_break;
1717 return skip_tx_en_setup(priv, board, port, idx);
1720 static int pci_eg20t_init(struct pci_dev *dev)
1722 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1729 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1730 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1733 pci_xr17c154_setup(struct serial_private *priv,
1734 const struct pciserial_board *board,
1735 struct uart_8250_port *port, int idx)
1737 port->port.flags |= UPF_EXAR_EFR;
1738 return pci_default_setup(priv, board, port, idx);
1742 xr17v35x_has_slave(struct serial_private *priv)
1744 const int dev_id = priv->dev->device;
1746 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1747 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1751 pci_xr17v35x_setup(struct serial_private *priv,
1752 const struct pciserial_board *board,
1753 struct uart_8250_port *port, int idx)
1757 p = pci_ioremap_bar(priv->dev, 0);
1761 port->port.flags |= UPF_EXAR_EFR;
1764 * Setup the uart clock for the devices on expansion slot to
1765 * half the clock speed of the main chip (which is 125MHz)
1767 if (xr17v35x_has_slave(priv) && idx >= 8)
1768 port->port.uartclk = (7812500 * 16 / 2);
1771 * Setup Multipurpose Input/Output pins.
1774 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1775 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1776 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1777 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1778 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1779 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1780 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1781 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1782 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1783 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1784 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1785 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1787 writeb(0x00, p + UART_EXAR_8XMODE);
1788 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1789 writeb(128, p + UART_EXAR_TXTRG);
1790 writeb(128, p + UART_EXAR_RXTRG);
1793 return pci_default_setup(priv, board, port, idx);
1796 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1797 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1798 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1799 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1802 pci_fastcom335_setup(struct serial_private *priv,
1803 const struct pciserial_board *board,
1804 struct uart_8250_port *port, int idx)
1808 p = pci_ioremap_bar(priv->dev, 0);
1812 port->port.flags |= UPF_EXAR_EFR;
1815 * Setup Multipurpose Input/Output pins.
1818 switch (priv->dev->device) {
1819 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1820 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1821 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1822 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1823 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1825 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1826 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1827 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1828 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1829 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1832 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1833 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1834 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1836 writeb(0x00, p + UART_EXAR_8XMODE);
1837 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1838 writeb(32, p + UART_EXAR_TXTRG);
1839 writeb(32, p + UART_EXAR_RXTRG);
1842 return pci_default_setup(priv, board, port, idx);
1846 pci_wch_ch353_setup(struct serial_private *priv,
1847 const struct pciserial_board *board,
1848 struct uart_8250_port *port, int idx)
1850 port->port.flags |= UPF_FIXED_TYPE;
1851 port->port.type = PORT_16550A;
1852 return pci_default_setup(priv, board, port, idx);
1856 pci_wch_ch38x_setup(struct serial_private *priv,
1857 const struct pciserial_board *board,
1858 struct uart_8250_port *port, int idx)
1860 port->port.flags |= UPF_FIXED_TYPE;
1861 port->port.type = PORT_16850;
1862 return pci_default_setup(priv, board, port, idx);
1865 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1866 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1867 #define PCI_DEVICE_ID_OCTPRO 0x0001
1868 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1869 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1870 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1871 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1872 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1873 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1874 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1875 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1876 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1877 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1878 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1879 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1880 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1881 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1882 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1883 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1884 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1885 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1886 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1887 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1888 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1889 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1890 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1891 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1892 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1893 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1894 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1895 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1896 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1897 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1898 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1899 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1900 #define PCI_VENDOR_ID_WCH 0x4348
1901 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1902 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1903 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1904 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1905 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1906 #define PCI_VENDOR_ID_AGESTAR 0x5372
1907 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1908 #define PCI_VENDOR_ID_ASIX 0x9710
1909 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1910 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1911 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1912 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1913 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1914 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1916 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1917 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1919 #define PCIE_VENDOR_ID_WCH 0x1c00
1920 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1921 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1922 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1924 #define PCI_VENDOR_ID_PERICOM 0x12D8
1925 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1926 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1927 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1928 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1930 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1931 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1932 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1935 * Master list of serial port init/setup/exit quirks.
1936 * This does not describe the general nature of the port.
1937 * (ie, baud base, number and location of ports, etc)
1939 * This list is ordered alphabetically by vendor then device.
1940 * Specific entries must come before more generic entries.
1942 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1944 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1947 .vendor = PCI_VENDOR_ID_AMCC,
1948 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1949 .subvendor = PCI_ANY_ID,
1950 .subdevice = PCI_ANY_ID,
1951 .setup = addidata_apci7800_setup,
1954 * AFAVLAB cards - these may be called via parport_serial
1955 * It is not clear whether this applies to all products.
1958 .vendor = PCI_VENDOR_ID_AFAVLAB,
1959 .device = PCI_ANY_ID,
1960 .subvendor = PCI_ANY_ID,
1961 .subdevice = PCI_ANY_ID,
1962 .setup = afavlab_setup,
1968 .vendor = PCI_VENDOR_ID_HP,
1969 .device = PCI_DEVICE_ID_HP_DIVA,
1970 .subvendor = PCI_ANY_ID,
1971 .subdevice = PCI_ANY_ID,
1972 .init = pci_hp_diva_init,
1973 .setup = pci_hp_diva_setup,
1979 .vendor = PCI_VENDOR_ID_INTEL,
1980 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1981 .subvendor = 0xe4bf,
1982 .subdevice = PCI_ANY_ID,
1983 .init = pci_inteli960ni_init,
1984 .setup = pci_default_setup,
1987 .vendor = PCI_VENDOR_ID_INTEL,
1988 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1989 .subvendor = PCI_ANY_ID,
1990 .subdevice = PCI_ANY_ID,
1991 .setup = skip_tx_en_setup,
1994 .vendor = PCI_VENDOR_ID_INTEL,
1995 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .setup = skip_tx_en_setup,
2001 .vendor = PCI_VENDOR_ID_INTEL,
2002 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .setup = skip_tx_en_setup,
2008 .vendor = PCI_VENDOR_ID_INTEL,
2009 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = ce4100_serial_setup,
2015 .vendor = PCI_VENDOR_ID_INTEL,
2016 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .setup = kt_serial_setup,
2022 .vendor = PCI_VENDOR_ID_INTEL,
2023 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2024 .subvendor = PCI_ANY_ID,
2025 .subdevice = PCI_ANY_ID,
2026 .setup = byt_serial_setup,
2029 .vendor = PCI_VENDOR_ID_INTEL,
2030 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2031 .subvendor = PCI_ANY_ID,
2032 .subdevice = PCI_ANY_ID,
2033 .setup = byt_serial_setup,
2036 .vendor = PCI_VENDOR_ID_INTEL,
2037 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2038 .subvendor = PCI_ANY_ID,
2039 .subdevice = PCI_ANY_ID,
2040 .setup = byt_serial_setup,
2043 .vendor = PCI_VENDOR_ID_INTEL,
2044 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2045 .subvendor = PCI_ANY_ID,
2046 .subdevice = PCI_ANY_ID,
2047 .setup = byt_serial_setup,
2050 .vendor = PCI_VENDOR_ID_INTEL,
2051 .device = PCI_DEVICE_ID_INTEL_BDW_UART1,
2052 .subvendor = PCI_ANY_ID,
2053 .subdevice = PCI_ANY_ID,
2054 .setup = byt_serial_setup,
2057 .vendor = PCI_VENDOR_ID_INTEL,
2058 .device = PCI_DEVICE_ID_INTEL_BDW_UART2,
2059 .subvendor = PCI_ANY_ID,
2060 .subdevice = PCI_ANY_ID,
2061 .setup = byt_serial_setup,
2067 .vendor = PCI_VENDOR_ID_ITE,
2068 .device = PCI_DEVICE_ID_ITE_8872,
2069 .subvendor = PCI_ANY_ID,
2070 .subdevice = PCI_ANY_ID,
2071 .init = pci_ite887x_init,
2072 .setup = pci_default_setup,
2073 .exit = pci_ite887x_exit,
2076 * National Instruments
2079 .vendor = PCI_VENDOR_ID_NI,
2080 .device = PCI_DEVICE_ID_NI_PCI23216,
2081 .subvendor = PCI_ANY_ID,
2082 .subdevice = PCI_ANY_ID,
2083 .init = pci_ni8420_init,
2084 .setup = pci_default_setup,
2085 .exit = pci_ni8420_exit,
2088 .vendor = PCI_VENDOR_ID_NI,
2089 .device = PCI_DEVICE_ID_NI_PCI2328,
2090 .subvendor = PCI_ANY_ID,
2091 .subdevice = PCI_ANY_ID,
2092 .init = pci_ni8420_init,
2093 .setup = pci_default_setup,
2094 .exit = pci_ni8420_exit,
2097 .vendor = PCI_VENDOR_ID_NI,
2098 .device = PCI_DEVICE_ID_NI_PCI2324,
2099 .subvendor = PCI_ANY_ID,
2100 .subdevice = PCI_ANY_ID,
2101 .init = pci_ni8420_init,
2102 .setup = pci_default_setup,
2103 .exit = pci_ni8420_exit,
2106 .vendor = PCI_VENDOR_ID_NI,
2107 .device = PCI_DEVICE_ID_NI_PCI2322,
2108 .subvendor = PCI_ANY_ID,
2109 .subdevice = PCI_ANY_ID,
2110 .init = pci_ni8420_init,
2111 .setup = pci_default_setup,
2112 .exit = pci_ni8420_exit,
2115 .vendor = PCI_VENDOR_ID_NI,
2116 .device = PCI_DEVICE_ID_NI_PCI2324I,
2117 .subvendor = PCI_ANY_ID,
2118 .subdevice = PCI_ANY_ID,
2119 .init = pci_ni8420_init,
2120 .setup = pci_default_setup,
2121 .exit = pci_ni8420_exit,
2124 .vendor = PCI_VENDOR_ID_NI,
2125 .device = PCI_DEVICE_ID_NI_PCI2322I,
2126 .subvendor = PCI_ANY_ID,
2127 .subdevice = PCI_ANY_ID,
2128 .init = pci_ni8420_init,
2129 .setup = pci_default_setup,
2130 .exit = pci_ni8420_exit,
2133 .vendor = PCI_VENDOR_ID_NI,
2134 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2135 .subvendor = PCI_ANY_ID,
2136 .subdevice = PCI_ANY_ID,
2137 .init = pci_ni8420_init,
2138 .setup = pci_default_setup,
2139 .exit = pci_ni8420_exit,
2142 .vendor = PCI_VENDOR_ID_NI,
2143 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2144 .subvendor = PCI_ANY_ID,
2145 .subdevice = PCI_ANY_ID,
2146 .init = pci_ni8420_init,
2147 .setup = pci_default_setup,
2148 .exit = pci_ni8420_exit,
2151 .vendor = PCI_VENDOR_ID_NI,
2152 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2153 .subvendor = PCI_ANY_ID,
2154 .subdevice = PCI_ANY_ID,
2155 .init = pci_ni8420_init,
2156 .setup = pci_default_setup,
2157 .exit = pci_ni8420_exit,
2160 .vendor = PCI_VENDOR_ID_NI,
2161 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2162 .subvendor = PCI_ANY_ID,
2163 .subdevice = PCI_ANY_ID,
2164 .init = pci_ni8420_init,
2165 .setup = pci_default_setup,
2166 .exit = pci_ni8420_exit,
2169 .vendor = PCI_VENDOR_ID_NI,
2170 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .init = pci_ni8420_init,
2174 .setup = pci_default_setup,
2175 .exit = pci_ni8420_exit,
2178 .vendor = PCI_VENDOR_ID_NI,
2179 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2180 .subvendor = PCI_ANY_ID,
2181 .subdevice = PCI_ANY_ID,
2182 .init = pci_ni8420_init,
2183 .setup = pci_default_setup,
2184 .exit = pci_ni8420_exit,
2187 .vendor = PCI_VENDOR_ID_NI,
2188 .device = PCI_ANY_ID,
2189 .subvendor = PCI_ANY_ID,
2190 .subdevice = PCI_ANY_ID,
2191 .init = pci_ni8430_init,
2192 .setup = pci_ni8430_setup,
2193 .exit = pci_ni8430_exit,
2197 .vendor = PCI_VENDOR_ID_QUATECH,
2198 .device = PCI_ANY_ID,
2199 .subvendor = PCI_ANY_ID,
2200 .subdevice = PCI_ANY_ID,
2201 .init = pci_quatech_init,
2202 .setup = pci_quatech_setup,
2203 .exit = pci_quatech_exit,
2209 .vendor = PCI_VENDOR_ID_PANACOM,
2210 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2211 .subvendor = PCI_ANY_ID,
2212 .subdevice = PCI_ANY_ID,
2213 .init = pci_plx9050_init,
2214 .setup = pci_default_setup,
2215 .exit = pci_plx9050_exit,
2218 .vendor = PCI_VENDOR_ID_PANACOM,
2219 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2220 .subvendor = PCI_ANY_ID,
2221 .subdevice = PCI_ANY_ID,
2222 .init = pci_plx9050_init,
2223 .setup = pci_default_setup,
2224 .exit = pci_plx9050_exit,
2230 .vendor = PCI_VENDOR_ID_PLX,
2231 .device = PCI_DEVICE_ID_PLX_9050,
2232 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2233 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2234 .init = pci_plx9050_init,
2235 .setup = pci_default_setup,
2236 .exit = pci_plx9050_exit,
2239 .vendor = PCI_VENDOR_ID_PLX,
2240 .device = PCI_DEVICE_ID_PLX_9050,
2241 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2242 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2243 .init = pci_plx9050_init,
2244 .setup = pci_default_setup,
2245 .exit = pci_plx9050_exit,
2248 .vendor = PCI_VENDOR_ID_PLX,
2249 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2250 .subvendor = PCI_VENDOR_ID_PLX,
2251 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2252 .init = pci_plx9050_init,
2253 .setup = pci_default_setup,
2254 .exit = pci_plx9050_exit,
2257 * SBS Technologies, Inc., PMC-OCTALPRO 232
2260 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2261 .device = PCI_DEVICE_ID_OCTPRO,
2262 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2263 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2269 * SBS Technologies, Inc., PMC-OCTALPRO 422
2272 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2273 .device = PCI_DEVICE_ID_OCTPRO,
2274 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2275 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2281 * SBS Technologies, Inc., P-Octal 232
2284 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2285 .device = PCI_DEVICE_ID_OCTPRO,
2286 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2287 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2293 * SBS Technologies, Inc., P-Octal 422
2296 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2297 .device = PCI_DEVICE_ID_OCTPRO,
2298 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2299 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2305 * SIIG cards - these may be called via parport_serial
2308 .vendor = PCI_VENDOR_ID_SIIG,
2309 .device = PCI_ANY_ID,
2310 .subvendor = PCI_ANY_ID,
2311 .subdevice = PCI_ANY_ID,
2312 .init = pci_siig_init,
2313 .setup = pci_siig_setup,
2319 .vendor = PCI_VENDOR_ID_TITAN,
2320 .device = PCI_DEVICE_ID_TITAN_400L,
2321 .subvendor = PCI_ANY_ID,
2322 .subdevice = PCI_ANY_ID,
2323 .setup = titan_400l_800l_setup,
2326 .vendor = PCI_VENDOR_ID_TITAN,
2327 .device = PCI_DEVICE_ID_TITAN_800L,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .setup = titan_400l_800l_setup,
2336 .vendor = PCI_VENDOR_ID_TIMEDIA,
2337 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2338 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2339 .subdevice = PCI_ANY_ID,
2340 .probe = pci_timedia_probe,
2341 .init = pci_timedia_init,
2342 .setup = pci_timedia_setup,
2345 .vendor = PCI_VENDOR_ID_TIMEDIA,
2346 .device = PCI_ANY_ID,
2347 .subvendor = PCI_ANY_ID,
2348 .subdevice = PCI_ANY_ID,
2349 .setup = pci_timedia_setup,
2352 * SUNIX (Timedia) cards
2353 * Do not "probe" for these cards as there is at least one combination
2354 * card that should be handled by parport_pc that doesn't match the
2355 * rule in pci_timedia_probe.
2356 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2357 * There are some boards with part number SER5037AL that report
2358 * subdevice ID 0x0002.
2361 .vendor = PCI_VENDOR_ID_SUNIX,
2362 .device = PCI_DEVICE_ID_SUNIX_1999,
2363 .subvendor = PCI_VENDOR_ID_SUNIX,
2364 .subdevice = PCI_ANY_ID,
2365 .init = pci_timedia_init,
2366 .setup = pci_timedia_setup,
2372 .vendor = PCI_VENDOR_ID_EXAR,
2373 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2374 .subvendor = PCI_ANY_ID,
2375 .subdevice = PCI_ANY_ID,
2376 .setup = pci_xr17c154_setup,
2379 .vendor = PCI_VENDOR_ID_EXAR,
2380 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2381 .subvendor = PCI_ANY_ID,
2382 .subdevice = PCI_ANY_ID,
2383 .setup = pci_xr17c154_setup,
2386 .vendor = PCI_VENDOR_ID_EXAR,
2387 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2388 .subvendor = PCI_ANY_ID,
2389 .subdevice = PCI_ANY_ID,
2390 .setup = pci_xr17c154_setup,
2393 .vendor = PCI_VENDOR_ID_EXAR,
2394 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .setup = pci_xr17v35x_setup,
2400 .vendor = PCI_VENDOR_ID_EXAR,
2401 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2402 .subvendor = PCI_ANY_ID,
2403 .subdevice = PCI_ANY_ID,
2404 .setup = pci_xr17v35x_setup,
2407 .vendor = PCI_VENDOR_ID_EXAR,
2408 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2409 .subvendor = PCI_ANY_ID,
2410 .subdevice = PCI_ANY_ID,
2411 .setup = pci_xr17v35x_setup,
2414 .vendor = PCI_VENDOR_ID_EXAR,
2415 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2416 .subvendor = PCI_ANY_ID,
2417 .subdevice = PCI_ANY_ID,
2418 .setup = pci_xr17v35x_setup,
2421 .vendor = PCI_VENDOR_ID_EXAR,
2422 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2423 .subvendor = PCI_ANY_ID,
2424 .subdevice = PCI_ANY_ID,
2425 .setup = pci_xr17v35x_setup,
2431 .vendor = PCI_VENDOR_ID_XIRCOM,
2432 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2433 .subvendor = PCI_ANY_ID,
2434 .subdevice = PCI_ANY_ID,
2435 .init = pci_xircom_init,
2436 .setup = pci_default_setup,
2439 * Netmos cards - these may be called via parport_serial
2442 .vendor = PCI_VENDOR_ID_NETMOS,
2443 .device = PCI_ANY_ID,
2444 .subvendor = PCI_ANY_ID,
2445 .subdevice = PCI_ANY_ID,
2446 .init = pci_netmos_init,
2447 .setup = pci_netmos_9900_setup,
2450 * EndRun Technologies
2453 .vendor = PCI_VENDOR_ID_ENDRUN,
2454 .device = PCI_ANY_ID,
2455 .subvendor = PCI_ANY_ID,
2456 .subdevice = PCI_ANY_ID,
2457 .init = pci_endrun_init,
2458 .setup = pci_default_setup,
2461 * For Oxford Semiconductor Tornado based devices
2464 .vendor = PCI_VENDOR_ID_OXSEMI,
2465 .device = PCI_ANY_ID,
2466 .subvendor = PCI_ANY_ID,
2467 .subdevice = PCI_ANY_ID,
2468 .init = pci_oxsemi_tornado_init,
2469 .setup = pci_default_setup,
2472 .vendor = PCI_VENDOR_ID_MAINPINE,
2473 .device = PCI_ANY_ID,
2474 .subvendor = PCI_ANY_ID,
2475 .subdevice = PCI_ANY_ID,
2476 .init = pci_oxsemi_tornado_init,
2477 .setup = pci_default_setup,
2480 .vendor = PCI_VENDOR_ID_DIGI,
2481 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2482 .subvendor = PCI_SUBVENDOR_ID_IBM,
2483 .subdevice = PCI_ANY_ID,
2484 .init = pci_oxsemi_tornado_init,
2485 .setup = pci_default_setup,
2488 .vendor = PCI_VENDOR_ID_INTEL,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .init = pci_eg20t_init,
2493 .setup = pci_default_setup,
2496 .vendor = PCI_VENDOR_ID_INTEL,
2498 .subvendor = PCI_ANY_ID,
2499 .subdevice = PCI_ANY_ID,
2500 .init = pci_eg20t_init,
2501 .setup = pci_default_setup,
2504 .vendor = PCI_VENDOR_ID_INTEL,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .init = pci_eg20t_init,
2509 .setup = pci_default_setup,
2512 .vendor = PCI_VENDOR_ID_INTEL,
2514 .subvendor = PCI_ANY_ID,
2515 .subdevice = PCI_ANY_ID,
2516 .init = pci_eg20t_init,
2517 .setup = pci_default_setup,
2522 .subvendor = PCI_ANY_ID,
2523 .subdevice = PCI_ANY_ID,
2524 .init = pci_eg20t_init,
2525 .setup = pci_default_setup,
2530 .subvendor = PCI_ANY_ID,
2531 .subdevice = PCI_ANY_ID,
2532 .init = pci_eg20t_init,
2533 .setup = pci_default_setup,
2538 .subvendor = PCI_ANY_ID,
2539 .subdevice = PCI_ANY_ID,
2540 .init = pci_eg20t_init,
2541 .setup = pci_default_setup,
2546 .subvendor = PCI_ANY_ID,
2547 .subdevice = PCI_ANY_ID,
2548 .init = pci_eg20t_init,
2549 .setup = pci_default_setup,
2554 .subvendor = PCI_ANY_ID,
2555 .subdevice = PCI_ANY_ID,
2556 .init = pci_eg20t_init,
2557 .setup = pci_default_setup,
2560 * Cronyx Omega PCI (PLX-chip based)
2563 .vendor = PCI_VENDOR_ID_PLX,
2564 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2565 .subvendor = PCI_ANY_ID,
2566 .subdevice = PCI_ANY_ID,
2567 .setup = pci_omegapci_setup,
2569 /* WCH CH353 1S1P card (16550 clone) */
2571 .vendor = PCI_VENDOR_ID_WCH,
2572 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2573 .subvendor = PCI_ANY_ID,
2574 .subdevice = PCI_ANY_ID,
2575 .setup = pci_wch_ch353_setup,
2577 /* WCH CH353 2S1P card (16550 clone) */
2579 .vendor = PCI_VENDOR_ID_WCH,
2580 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2581 .subvendor = PCI_ANY_ID,
2582 .subdevice = PCI_ANY_ID,
2583 .setup = pci_wch_ch353_setup,
2585 /* WCH CH353 4S card (16550 clone) */
2587 .vendor = PCI_VENDOR_ID_WCH,
2588 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2589 .subvendor = PCI_ANY_ID,
2590 .subdevice = PCI_ANY_ID,
2591 .setup = pci_wch_ch353_setup,
2593 /* WCH CH353 2S1PF card (16550 clone) */
2595 .vendor = PCI_VENDOR_ID_WCH,
2596 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2597 .subvendor = PCI_ANY_ID,
2598 .subdevice = PCI_ANY_ID,
2599 .setup = pci_wch_ch353_setup,
2601 /* WCH CH352 2S card (16550 clone) */
2603 .vendor = PCI_VENDOR_ID_WCH,
2604 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2605 .subvendor = PCI_ANY_ID,
2606 .subdevice = PCI_ANY_ID,
2607 .setup = pci_wch_ch353_setup,
2609 /* WCH CH382 2S card (16850 clone) */
2611 .vendor = PCIE_VENDOR_ID_WCH,
2612 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2613 .subvendor = PCI_ANY_ID,
2614 .subdevice = PCI_ANY_ID,
2615 .setup = pci_wch_ch38x_setup,
2617 /* WCH CH382 2S1P card (16850 clone) */
2619 .vendor = PCIE_VENDOR_ID_WCH,
2620 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2621 .subvendor = PCI_ANY_ID,
2622 .subdevice = PCI_ANY_ID,
2623 .setup = pci_wch_ch38x_setup,
2625 /* WCH CH384 4S card (16850 clone) */
2627 .vendor = PCIE_VENDOR_ID_WCH,
2628 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2629 .subvendor = PCI_ANY_ID,
2630 .subdevice = PCI_ANY_ID,
2631 .setup = pci_wch_ch38x_setup,
2634 * ASIX devices with FIFO bug
2637 .vendor = PCI_VENDOR_ID_ASIX,
2638 .device = PCI_ANY_ID,
2639 .subvendor = PCI_ANY_ID,
2640 .subdevice = PCI_ANY_ID,
2641 .setup = pci_asix_setup,
2644 * Commtech, Inc. Fastcom adapters
2648 .vendor = PCI_VENDOR_ID_COMMTECH,
2649 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2650 .subvendor = PCI_ANY_ID,
2651 .subdevice = PCI_ANY_ID,
2652 .setup = pci_fastcom335_setup,
2655 .vendor = PCI_VENDOR_ID_COMMTECH,
2656 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2657 .subvendor = PCI_ANY_ID,
2658 .subdevice = PCI_ANY_ID,
2659 .setup = pci_fastcom335_setup,
2662 .vendor = PCI_VENDOR_ID_COMMTECH,
2663 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2664 .subvendor = PCI_ANY_ID,
2665 .subdevice = PCI_ANY_ID,
2666 .setup = pci_fastcom335_setup,
2669 .vendor = PCI_VENDOR_ID_COMMTECH,
2670 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2671 .subvendor = PCI_ANY_ID,
2672 .subdevice = PCI_ANY_ID,
2673 .setup = pci_fastcom335_setup,
2676 .vendor = PCI_VENDOR_ID_COMMTECH,
2677 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2678 .subvendor = PCI_ANY_ID,
2679 .subdevice = PCI_ANY_ID,
2680 .setup = pci_xr17v35x_setup,
2683 .vendor = PCI_VENDOR_ID_COMMTECH,
2684 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2685 .subvendor = PCI_ANY_ID,
2686 .subdevice = PCI_ANY_ID,
2687 .setup = pci_xr17v35x_setup,
2690 .vendor = PCI_VENDOR_ID_COMMTECH,
2691 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2692 .subvendor = PCI_ANY_ID,
2693 .subdevice = PCI_ANY_ID,
2694 .setup = pci_xr17v35x_setup,
2697 * Broadcom TruManage (NetXtreme)
2700 .vendor = PCI_VENDOR_ID_BROADCOM,
2701 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2702 .subvendor = PCI_ANY_ID,
2703 .subdevice = PCI_ANY_ID,
2704 .setup = pci_brcm_trumanage_setup,
2709 .subvendor = PCI_ANY_ID,
2710 .subdevice = PCI_ANY_ID,
2711 .setup = pci_fintek_setup,
2712 .init = pci_fintek_init,
2717 .subvendor = PCI_ANY_ID,
2718 .subdevice = PCI_ANY_ID,
2719 .setup = pci_fintek_setup,
2720 .init = pci_fintek_init,
2725 .subvendor = PCI_ANY_ID,
2726 .subdevice = PCI_ANY_ID,
2727 .setup = pci_fintek_setup,
2728 .init = pci_fintek_init,
2732 * Default "match everything" terminator entry
2735 .vendor = PCI_ANY_ID,
2736 .device = PCI_ANY_ID,
2737 .subvendor = PCI_ANY_ID,
2738 .subdevice = PCI_ANY_ID,
2739 .setup = pci_default_setup,
2743 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2745 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2748 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2750 struct pci_serial_quirk *quirk;
2752 for (quirk = pci_serial_quirks; ; quirk++)
2753 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2754 quirk_id_matches(quirk->device, dev->device) &&
2755 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2756 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2761 static inline int get_pci_irq(struct pci_dev *dev,
2762 const struct pciserial_board *board)
2764 if (board->flags & FL_NOIRQ)
2771 * This is the configuration table for all of the PCI serial boards
2772 * which we support. It is directly indexed by the pci_board_num_t enum
2773 * value, which is encoded in the pci_device_id PCI probe table's
2774 * driver_data member.
2776 * The makeup of these names are:
2777 * pbn_bn{_bt}_n_baud{_offsetinhex}
2779 * bn = PCI BAR number
2780 * bt = Index using PCI BARs
2781 * n = number of serial ports
2783 * offsetinhex = offset for each sequential port (in hex)
2785 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2787 * Please note: in theory if n = 1, _bt infix should make no difference.
2788 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2790 enum pci_board_num_t {
2807 pbn_b0_2_1152000_200,
2808 pbn_b0_4_1152000_200,
2809 pbn_b0_8_1152000_200,
2814 pbn_b0_2_1843200_200,
2815 pbn_b0_4_1843200_200,
2816 pbn_b0_8_1843200_200,
2890 * Board-specific versions.
2896 pbn_endrun_2_4000000,
2898 pbn_oxsemi_1_4000000,
2899 pbn_oxsemi_2_4000000,
2900 pbn_oxsemi_4_4000000,
2901 pbn_oxsemi_8_4000000,
2916 pbn_exar_ibm_saturn,
2922 pbn_ADDIDATA_PCIe_1_3906250,
2923 pbn_ADDIDATA_PCIe_2_3906250,
2924 pbn_ADDIDATA_PCIe_4_3906250,
2925 pbn_ADDIDATA_PCIe_8_3906250,
2926 pbn_ce4100_1_115200,
2930 pbn_NETMOS9900_2s_115200,
2937 pbn_pericom_PI7C9X7951,
2938 pbn_pericom_PI7C9X7952,
2939 pbn_pericom_PI7C9X7954,
2940 pbn_pericom_PI7C9X7958,
2944 * uart_offset - the space between channels
2945 * reg_shift - describes how the UART registers are mapped
2946 * to PCI memory by the card.
2947 * For example IER register on SBS, Inc. PMC-OctPro is located at
2948 * offset 0x10 from the UART base, while UART_IER is defined as 1
2949 * in include/linux/serial_reg.h,
2950 * see first lines of serial_in() and serial_out() in 8250.c
2953 static struct pciserial_board pci_boards[] = {
2957 .base_baud = 115200,
2960 [pbn_b0_1_115200] = {
2963 .base_baud = 115200,
2966 [pbn_b0_2_115200] = {
2969 .base_baud = 115200,
2972 [pbn_b0_4_115200] = {
2975 .base_baud = 115200,
2978 [pbn_b0_5_115200] = {
2981 .base_baud = 115200,
2984 [pbn_b0_8_115200] = {
2987 .base_baud = 115200,
2990 [pbn_b0_1_921600] = {
2993 .base_baud = 921600,
2996 [pbn_b0_2_921600] = {
2999 .base_baud = 921600,
3002 [pbn_b0_4_921600] = {
3005 .base_baud = 921600,
3009 [pbn_b0_2_1130000] = {
3012 .base_baud = 1130000,
3016 [pbn_b0_4_1152000] = {
3019 .base_baud = 1152000,
3023 [pbn_b0_2_1152000_200] = {
3026 .base_baud = 1152000,
3027 .uart_offset = 0x200,
3030 [pbn_b0_4_1152000_200] = {
3033 .base_baud = 1152000,
3034 .uart_offset = 0x200,
3037 [pbn_b0_8_1152000_200] = {
3040 .base_baud = 1152000,
3041 .uart_offset = 0x200,
3044 [pbn_b0_2_1843200] = {
3047 .base_baud = 1843200,
3050 [pbn_b0_4_1843200] = {
3053 .base_baud = 1843200,
3057 [pbn_b0_2_1843200_200] = {
3060 .base_baud = 1843200,
3061 .uart_offset = 0x200,
3063 [pbn_b0_4_1843200_200] = {
3066 .base_baud = 1843200,
3067 .uart_offset = 0x200,
3069 [pbn_b0_8_1843200_200] = {
3072 .base_baud = 1843200,
3073 .uart_offset = 0x200,
3075 [pbn_b0_1_4000000] = {
3078 .base_baud = 4000000,
3082 [pbn_b0_bt_1_115200] = {
3083 .flags = FL_BASE0|FL_BASE_BARS,
3085 .base_baud = 115200,
3088 [pbn_b0_bt_2_115200] = {
3089 .flags = FL_BASE0|FL_BASE_BARS,
3091 .base_baud = 115200,
3094 [pbn_b0_bt_4_115200] = {
3095 .flags = FL_BASE0|FL_BASE_BARS,
3097 .base_baud = 115200,
3100 [pbn_b0_bt_8_115200] = {
3101 .flags = FL_BASE0|FL_BASE_BARS,
3103 .base_baud = 115200,
3107 [pbn_b0_bt_1_460800] = {
3108 .flags = FL_BASE0|FL_BASE_BARS,
3110 .base_baud = 460800,
3113 [pbn_b0_bt_2_460800] = {
3114 .flags = FL_BASE0|FL_BASE_BARS,
3116 .base_baud = 460800,
3119 [pbn_b0_bt_4_460800] = {
3120 .flags = FL_BASE0|FL_BASE_BARS,
3122 .base_baud = 460800,
3126 [pbn_b0_bt_1_921600] = {
3127 .flags = FL_BASE0|FL_BASE_BARS,
3129 .base_baud = 921600,
3132 [pbn_b0_bt_2_921600] = {
3133 .flags = FL_BASE0|FL_BASE_BARS,
3135 .base_baud = 921600,
3138 [pbn_b0_bt_4_921600] = {
3139 .flags = FL_BASE0|FL_BASE_BARS,
3141 .base_baud = 921600,
3144 [pbn_b0_bt_8_921600] = {
3145 .flags = FL_BASE0|FL_BASE_BARS,
3147 .base_baud = 921600,
3151 [pbn_b1_1_115200] = {
3154 .base_baud = 115200,
3157 [pbn_b1_2_115200] = {
3160 .base_baud = 115200,
3163 [pbn_b1_4_115200] = {
3166 .base_baud = 115200,
3169 [pbn_b1_8_115200] = {
3172 .base_baud = 115200,
3175 [pbn_b1_16_115200] = {
3178 .base_baud = 115200,
3182 [pbn_b1_1_921600] = {
3185 .base_baud = 921600,
3188 [pbn_b1_2_921600] = {
3191 .base_baud = 921600,
3194 [pbn_b1_4_921600] = {
3197 .base_baud = 921600,
3200 [pbn_b1_8_921600] = {
3203 .base_baud = 921600,
3206 [pbn_b1_2_1250000] = {
3209 .base_baud = 1250000,
3213 [pbn_b1_bt_1_115200] = {
3214 .flags = FL_BASE1|FL_BASE_BARS,
3216 .base_baud = 115200,
3219 [pbn_b1_bt_2_115200] = {
3220 .flags = FL_BASE1|FL_BASE_BARS,
3222 .base_baud = 115200,
3225 [pbn_b1_bt_4_115200] = {
3226 .flags = FL_BASE1|FL_BASE_BARS,
3228 .base_baud = 115200,
3232 [pbn_b1_bt_2_921600] = {
3233 .flags = FL_BASE1|FL_BASE_BARS,
3235 .base_baud = 921600,
3239 [pbn_b1_1_1382400] = {
3242 .base_baud = 1382400,
3245 [pbn_b1_2_1382400] = {
3248 .base_baud = 1382400,
3251 [pbn_b1_4_1382400] = {
3254 .base_baud = 1382400,
3257 [pbn_b1_8_1382400] = {
3260 .base_baud = 1382400,
3264 [pbn_b2_1_115200] = {
3267 .base_baud = 115200,
3270 [pbn_b2_2_115200] = {
3273 .base_baud = 115200,
3276 [pbn_b2_4_115200] = {
3279 .base_baud = 115200,
3282 [pbn_b2_8_115200] = {
3285 .base_baud = 115200,
3289 [pbn_b2_1_460800] = {
3292 .base_baud = 460800,
3295 [pbn_b2_4_460800] = {
3298 .base_baud = 460800,
3301 [pbn_b2_8_460800] = {
3304 .base_baud = 460800,
3307 [pbn_b2_16_460800] = {
3310 .base_baud = 460800,
3314 [pbn_b2_1_921600] = {
3317 .base_baud = 921600,
3320 [pbn_b2_4_921600] = {
3323 .base_baud = 921600,
3326 [pbn_b2_8_921600] = {
3329 .base_baud = 921600,
3333 [pbn_b2_8_1152000] = {
3336 .base_baud = 1152000,
3340 [pbn_b2_bt_1_115200] = {
3341 .flags = FL_BASE2|FL_BASE_BARS,
3343 .base_baud = 115200,
3346 [pbn_b2_bt_2_115200] = {
3347 .flags = FL_BASE2|FL_BASE_BARS,
3349 .base_baud = 115200,
3352 [pbn_b2_bt_4_115200] = {
3353 .flags = FL_BASE2|FL_BASE_BARS,
3355 .base_baud = 115200,
3359 [pbn_b2_bt_2_921600] = {
3360 .flags = FL_BASE2|FL_BASE_BARS,
3362 .base_baud = 921600,
3365 [pbn_b2_bt_4_921600] = {
3366 .flags = FL_BASE2|FL_BASE_BARS,
3368 .base_baud = 921600,
3372 [pbn_b3_2_115200] = {
3375 .base_baud = 115200,
3378 [pbn_b3_4_115200] = {
3381 .base_baud = 115200,
3384 [pbn_b3_8_115200] = {
3387 .base_baud = 115200,
3391 [pbn_b4_bt_2_921600] = {
3394 .base_baud = 921600,
3397 [pbn_b4_bt_4_921600] = {
3400 .base_baud = 921600,
3403 [pbn_b4_bt_8_921600] = {
3406 .base_baud = 921600,
3411 * Entries following this are board-specific.
3420 .base_baud = 921600,
3421 .uart_offset = 0x400,
3425 .flags = FL_BASE2|FL_BASE_BARS,
3427 .base_baud = 921600,
3428 .uart_offset = 0x400,
3432 .flags = FL_BASE2|FL_BASE_BARS,
3434 .base_baud = 921600,
3435 .uart_offset = 0x400,
3439 /* I think this entry is broken - the first_offset looks wrong --rmk */
3440 [pbn_plx_romulus] = {
3443 .base_baud = 921600,
3444 .uart_offset = 8 << 2,
3446 .first_offset = 0x03,
3450 * EndRun Technologies
3451 * Uses the size of PCI Base region 0 to
3452 * signal now many ports are available
3453 * 2 port 952 Uart support
3455 [pbn_endrun_2_4000000] = {
3458 .base_baud = 4000000,
3459 .uart_offset = 0x200,
3460 .first_offset = 0x1000,
3464 * This board uses the size of PCI Base region 0 to
3465 * signal now many ports are available
3468 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3470 .base_baud = 115200,
3473 [pbn_oxsemi_1_4000000] = {
3476 .base_baud = 4000000,
3477 .uart_offset = 0x200,
3478 .first_offset = 0x1000,
3480 [pbn_oxsemi_2_4000000] = {
3483 .base_baud = 4000000,
3484 .uart_offset = 0x200,
3485 .first_offset = 0x1000,
3487 [pbn_oxsemi_4_4000000] = {
3490 .base_baud = 4000000,
3491 .uart_offset = 0x200,
3492 .first_offset = 0x1000,
3494 [pbn_oxsemi_8_4000000] = {
3497 .base_baud = 4000000,
3498 .uart_offset = 0x200,
3499 .first_offset = 0x1000,
3504 * EKF addition for i960 Boards form EKF with serial port.
3507 [pbn_intel_i960] = {
3510 .base_baud = 921600,
3511 .uart_offset = 8 << 2,
3513 .first_offset = 0x10000,
3516 .flags = FL_BASE0|FL_NOIRQ,
3518 .base_baud = 458333,
3521 .first_offset = 0x20178,
3525 * Computone - uses IOMEM.
3527 [pbn_computone_4] = {
3530 .base_baud = 921600,
3531 .uart_offset = 0x40,
3533 .first_offset = 0x200,
3535 [pbn_computone_6] = {
3538 .base_baud = 921600,
3539 .uart_offset = 0x40,
3541 .first_offset = 0x200,
3543 [pbn_computone_8] = {
3546 .base_baud = 921600,
3547 .uart_offset = 0x40,
3549 .first_offset = 0x200,
3554 .base_baud = 460800,
3559 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3560 * Only basic 16550A support.
3561 * XR17C15[24] are not tested, but they should work.
3563 [pbn_exar_XR17C152] = {
3566 .base_baud = 921600,
3567 .uart_offset = 0x200,
3569 [pbn_exar_XR17C154] = {
3572 .base_baud = 921600,
3573 .uart_offset = 0x200,
3575 [pbn_exar_XR17C158] = {
3578 .base_baud = 921600,
3579 .uart_offset = 0x200,
3581 [pbn_exar_XR17V352] = {
3584 .base_baud = 7812500,
3585 .uart_offset = 0x400,
3589 [pbn_exar_XR17V354] = {
3592 .base_baud = 7812500,
3593 .uart_offset = 0x400,
3597 [pbn_exar_XR17V358] = {
3600 .base_baud = 7812500,
3601 .uart_offset = 0x400,
3605 [pbn_exar_XR17V4358] = {
3608 .base_baud = 7812500,
3609 .uart_offset = 0x400,
3613 [pbn_exar_XR17V8358] = {
3616 .base_baud = 7812500,
3617 .uart_offset = 0x400,
3621 [pbn_exar_ibm_saturn] = {
3624 .base_baud = 921600,
3625 .uart_offset = 0x200,
3629 * PA Semi PWRficient PA6T-1682M on-chip UART
3631 [pbn_pasemi_1682M] = {
3634 .base_baud = 8333333,
3637 * National Instruments 843x
3642 .base_baud = 3686400,
3643 .uart_offset = 0x10,
3644 .first_offset = 0x800,
3649 .base_baud = 3686400,
3650 .uart_offset = 0x10,
3651 .first_offset = 0x800,
3656 .base_baud = 3686400,
3657 .uart_offset = 0x10,
3658 .first_offset = 0x800,
3663 .base_baud = 3686400,
3664 .uart_offset = 0x10,
3665 .first_offset = 0x800,
3668 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3670 [pbn_ADDIDATA_PCIe_1_3906250] = {
3673 .base_baud = 3906250,
3674 .uart_offset = 0x200,
3675 .first_offset = 0x1000,
3677 [pbn_ADDIDATA_PCIe_2_3906250] = {
3680 .base_baud = 3906250,
3681 .uart_offset = 0x200,
3682 .first_offset = 0x1000,
3684 [pbn_ADDIDATA_PCIe_4_3906250] = {
3687 .base_baud = 3906250,
3688 .uart_offset = 0x200,
3689 .first_offset = 0x1000,
3691 [pbn_ADDIDATA_PCIe_8_3906250] = {
3694 .base_baud = 3906250,
3695 .uart_offset = 0x200,
3696 .first_offset = 0x1000,
3698 [pbn_ce4100_1_115200] = {
3699 .flags = FL_BASE_BARS,
3701 .base_baud = 921600,
3705 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3706 * but is overridden by byt_set_termios.
3711 .base_baud = 2764800,
3712 .uart_offset = 0x80,
3718 .base_baud = 2764800,
3724 .base_baud = 115200,
3725 .uart_offset = 0x200,
3727 [pbn_NETMOS9900_2s_115200] = {
3730 .base_baud = 115200,
3732 [pbn_brcm_trumanage] = {
3736 .base_baud = 115200,
3741 .base_baud = 115200,
3742 .first_offset = 0x40,
3747 .base_baud = 115200,
3748 .first_offset = 0x40,
3753 .base_baud = 115200,
3754 .first_offset = 0x40,
3759 .base_baud = 115200,
3761 .first_offset = 0xC0,
3766 .base_baud = 115200,
3768 .first_offset = 0xC0,
3771 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3773 [pbn_pericom_PI7C9X7951] = {
3776 .base_baud = 921600,
3779 [pbn_pericom_PI7C9X7952] = {
3782 .base_baud = 921600,
3785 [pbn_pericom_PI7C9X7954] = {
3788 .base_baud = 921600,
3791 [pbn_pericom_PI7C9X7958] = {
3794 .base_baud = 921600,
3799 static const struct pci_device_id blacklist[] = {
3801 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3802 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3803 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3805 /* multi-io cards handled by parport_serial */
3806 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3807 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3808 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3809 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3811 /* Intel platforms with MID UART */
3812 { PCI_VDEVICE(INTEL, 0x081b), },
3813 { PCI_VDEVICE(INTEL, 0x081c), },
3814 { PCI_VDEVICE(INTEL, 0x081d), },
3815 { PCI_VDEVICE(INTEL, 0x1191), },
3816 { PCI_VDEVICE(INTEL, 0x19d8), },
3820 * Given a complete unknown PCI device, try to use some heuristics to
3821 * guess what the configuration might be, based on the pitiful PCI
3822 * serial specs. Returns 0 on success, 1 on failure.
3825 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3827 const struct pci_device_id *bldev;
3828 int num_iomem, num_port, first_port = -1, i;
3831 * If it is not a communications device or the programming
3832 * interface is greater than 6, give up.
3834 * (Should we try to make guesses for multiport serial devices
3837 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3838 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3839 (dev->class & 0xff) > 6)
3843 * Do not access blacklisted devices that are known not to
3844 * feature serial ports or are handled by other modules.
3846 for (bldev = blacklist;
3847 bldev < blacklist + ARRAY_SIZE(blacklist);
3849 if (dev->vendor == bldev->vendor &&
3850 dev->device == bldev->device)
3854 num_iomem = num_port = 0;
3855 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3856 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3858 if (first_port == -1)
3861 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3866 * If there is 1 or 0 iomem regions, and exactly one port,
3867 * use it. We guess the number of ports based on the IO
3870 if (num_iomem <= 1 && num_port == 1) {
3871 board->flags = first_port;
3872 board->num_ports = pci_resource_len(dev, first_port) / 8;
3877 * Now guess if we've got a board which indexes by BARs.
3878 * Each IO BAR should be 8 bytes, and they should follow
3883 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3884 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3885 pci_resource_len(dev, i) == 8 &&
3886 (first_port == -1 || (first_port + num_port) == i)) {
3888 if (first_port == -1)
3894 board->flags = first_port | FL_BASE_BARS;
3895 board->num_ports = num_port;
3903 serial_pci_matches(const struct pciserial_board *board,
3904 const struct pciserial_board *guessed)
3907 board->num_ports == guessed->num_ports &&
3908 board->base_baud == guessed->base_baud &&
3909 board->uart_offset == guessed->uart_offset &&
3910 board->reg_shift == guessed->reg_shift &&
3911 board->first_offset == guessed->first_offset;
3914 struct serial_private *
3915 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3917 struct uart_8250_port uart;
3918 struct serial_private *priv;
3919 struct pci_serial_quirk *quirk;
3920 int rc, nr_ports, i;
3922 nr_ports = board->num_ports;
3925 * Find an init and setup quirks.
3927 quirk = find_quirk(dev);
3930 * Run the new-style initialization function.
3931 * The initialization function returns:
3933 * 0 - use board->num_ports
3934 * >0 - number of ports
3937 rc = quirk->init(dev);
3946 priv = kzalloc(sizeof(struct serial_private) +
3947 sizeof(unsigned int) * nr_ports,
3950 priv = ERR_PTR(-ENOMEM);
3955 priv->quirk = quirk;
3957 memset(&uart, 0, sizeof(uart));
3958 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3959 uart.port.uartclk = board->base_baud * 16;
3960 uart.port.irq = get_pci_irq(dev, board);
3961 uart.port.dev = &dev->dev;
3963 for (i = 0; i < nr_ports; i++) {
3964 if (quirk->setup(priv, board, &uart, i))
3967 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3968 uart.port.iobase, uart.port.irq, uart.port.iotype);
3970 priv->line[i] = serial8250_register_8250_port(&uart);
3971 if (priv->line[i] < 0) {
3973 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3974 uart.port.iobase, uart.port.irq,
3975 uart.port.iotype, priv->line[i]);
3988 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3990 void pciserial_remove_ports(struct serial_private *priv)
3992 struct pci_serial_quirk *quirk;
3995 for (i = 0; i < priv->nr; i++)
3996 serial8250_unregister_port(priv->line[i]);
3998 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3999 if (priv->remapped_bar[i])
4000 iounmap(priv->remapped_bar[i]);
4001 priv->remapped_bar[i] = NULL;
4005 * Find the exit quirks.
4007 quirk = find_quirk(priv->dev);
4009 quirk->exit(priv->dev);
4013 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4015 void pciserial_suspend_ports(struct serial_private *priv)
4019 for (i = 0; i < priv->nr; i++)
4020 if (priv->line[i] >= 0)
4021 serial8250_suspend_port(priv->line[i]);
4024 * Ensure that every init quirk is properly torn down
4026 if (priv->quirk->exit)
4027 priv->quirk->exit(priv->dev);
4029 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4031 void pciserial_resume_ports(struct serial_private *priv)
4036 * Ensure that the board is correctly configured.
4038 if (priv->quirk->init)
4039 priv->quirk->init(priv->dev);
4041 for (i = 0; i < priv->nr; i++)
4042 if (priv->line[i] >= 0)
4043 serial8250_resume_port(priv->line[i]);
4045 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4048 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4049 * to the arrangement of serial ports on a PCI card.
4052 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4054 struct pci_serial_quirk *quirk;
4055 struct serial_private *priv;
4056 const struct pciserial_board *board;
4057 struct pciserial_board tmp;
4060 quirk = find_quirk(dev);
4062 rc = quirk->probe(dev);
4067 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4068 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4073 board = &pci_boards[ent->driver_data];
4075 rc = pci_enable_device(dev);
4076 pci_save_state(dev);
4080 if (ent->driver_data == pbn_default) {
4082 * Use a copy of the pci_board entry for this;
4083 * avoid changing entries in the table.
4085 memcpy(&tmp, board, sizeof(struct pciserial_board));
4089 * We matched one of our class entries. Try to
4090 * determine the parameters of this board.
4092 rc = serial_pci_guess_board(dev, &tmp);
4097 * We matched an explicit entry. If we are able to
4098 * detect this boards settings with our heuristic,
4099 * then we no longer need this entry.
4101 memcpy(&tmp, &pci_boards[pbn_default],
4102 sizeof(struct pciserial_board));
4103 rc = serial_pci_guess_board(dev, &tmp);
4104 if (rc == 0 && serial_pci_matches(board, &tmp))
4105 moan_device("Redundant entry in serial pci_table.",
4109 priv = pciserial_init_ports(dev, board);
4110 if (!IS_ERR(priv)) {
4111 pci_set_drvdata(dev, priv);
4118 pci_disable_device(dev);
4122 static void pciserial_remove_one(struct pci_dev *dev)
4124 struct serial_private *priv = pci_get_drvdata(dev);
4126 pciserial_remove_ports(priv);
4128 pci_disable_device(dev);
4131 #ifdef CONFIG_PM_SLEEP
4132 static int pciserial_suspend_one(struct device *dev)
4134 struct pci_dev *pdev = to_pci_dev(dev);
4135 struct serial_private *priv = pci_get_drvdata(pdev);
4138 pciserial_suspend_ports(priv);
4143 static int pciserial_resume_one(struct device *dev)
4145 struct pci_dev *pdev = to_pci_dev(dev);
4146 struct serial_private *priv = pci_get_drvdata(pdev);
4151 * The device may have been disabled. Re-enable it.
4153 err = pci_enable_device(pdev);
4154 /* FIXME: We cannot simply error out here */
4156 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4157 pciserial_resume_ports(priv);
4163 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4164 pciserial_resume_one);
4166 static struct pci_device_id serial_pci_tbl[] = {
4167 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4168 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4169 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4171 /* Advantech also use 0x3618 and 0xf618 */
4172 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4173 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4175 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4176 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4178 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4179 PCI_SUBVENDOR_ID_CONNECT_TECH,
4180 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4182 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4183 PCI_SUBVENDOR_ID_CONNECT_TECH,
4184 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4186 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4187 PCI_SUBVENDOR_ID_CONNECT_TECH,
4188 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4190 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4191 PCI_SUBVENDOR_ID_CONNECT_TECH,
4192 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4194 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4195 PCI_SUBVENDOR_ID_CONNECT_TECH,
4196 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4198 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4199 PCI_SUBVENDOR_ID_CONNECT_TECH,
4200 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4202 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4203 PCI_SUBVENDOR_ID_CONNECT_TECH,
4204 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4206 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4207 PCI_SUBVENDOR_ID_CONNECT_TECH,
4208 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4210 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4211 PCI_SUBVENDOR_ID_CONNECT_TECH,
4212 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4214 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4215 PCI_SUBVENDOR_ID_CONNECT_TECH,
4216 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4218 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4219 PCI_SUBVENDOR_ID_CONNECT_TECH,
4220 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4222 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4223 PCI_SUBVENDOR_ID_CONNECT_TECH,
4224 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4226 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4227 PCI_SUBVENDOR_ID_CONNECT_TECH,
4228 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4230 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4231 PCI_SUBVENDOR_ID_CONNECT_TECH,
4232 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4234 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4235 PCI_SUBVENDOR_ID_CONNECT_TECH,
4236 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4238 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4239 PCI_SUBVENDOR_ID_CONNECT_TECH,
4240 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4242 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4243 PCI_SUBVENDOR_ID_CONNECT_TECH,
4244 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4246 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4247 PCI_VENDOR_ID_AFAVLAB,
4248 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4250 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4251 PCI_SUBVENDOR_ID_CONNECT_TECH,
4252 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4253 pbn_b0_2_1843200_200 },
4254 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4255 PCI_SUBVENDOR_ID_CONNECT_TECH,
4256 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4257 pbn_b0_4_1843200_200 },
4258 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4259 PCI_SUBVENDOR_ID_CONNECT_TECH,
4260 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4261 pbn_b0_8_1843200_200 },
4262 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4263 PCI_SUBVENDOR_ID_CONNECT_TECH,
4264 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4265 pbn_b0_2_1843200_200 },
4266 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4267 PCI_SUBVENDOR_ID_CONNECT_TECH,
4268 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4269 pbn_b0_4_1843200_200 },
4270 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4271 PCI_SUBVENDOR_ID_CONNECT_TECH,
4272 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4273 pbn_b0_8_1843200_200 },
4274 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4275 PCI_SUBVENDOR_ID_CONNECT_TECH,
4276 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4277 pbn_b0_2_1843200_200 },
4278 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4279 PCI_SUBVENDOR_ID_CONNECT_TECH,
4280 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4281 pbn_b0_4_1843200_200 },
4282 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4283 PCI_SUBVENDOR_ID_CONNECT_TECH,
4284 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4285 pbn_b0_8_1843200_200 },
4286 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4287 PCI_SUBVENDOR_ID_CONNECT_TECH,
4288 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4289 pbn_b0_2_1843200_200 },
4290 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4291 PCI_SUBVENDOR_ID_CONNECT_TECH,
4292 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4293 pbn_b0_4_1843200_200 },
4294 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4295 PCI_SUBVENDOR_ID_CONNECT_TECH,
4296 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4297 pbn_b0_8_1843200_200 },
4298 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4299 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4300 0, 0, pbn_exar_ibm_saturn },
4302 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304 pbn_b2_bt_1_115200 },
4305 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307 pbn_b2_bt_2_115200 },
4308 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4310 pbn_b2_bt_4_115200 },
4311 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4313 pbn_b2_bt_2_115200 },
4314 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316 pbn_b2_bt_4_115200 },
4317 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4323 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4329 pbn_b2_bt_2_115200 },
4330 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 pbn_b2_bt_2_921600 },
4334 * VScom SPCOM800, from sl@s.pl
4336 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 /* Unknown card - subdevice 0x1584 */
4343 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4345 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4347 /* Unknown card - subdevice 0x1588 */
4348 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4350 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4352 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4353 PCI_SUBVENDOR_ID_KEYSPAN,
4354 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4356 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4363 PCI_VENDOR_ID_ESDGMBH,
4364 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4366 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4367 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4368 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4370 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4371 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4372 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4374 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4375 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4376 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4378 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4379 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4380 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4382 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4383 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4384 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4386 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4387 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4388 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4390 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4391 PCI_SUBVENDOR_ID_EXSYS,
4392 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4395 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4398 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4399 0x10b5, 0x106a, 0, 0,
4402 * EndRun Technologies. PCI express device range.
4403 * EndRun PTP/1588 has 2 Native UARTs.
4405 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_endrun_2_4000000 },
4409 * Quatech cards. These actually have configurable clocks but for
4410 * now we just use the default.
4412 * 100 series are RS232, 200 series RS422,
4414 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4423 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4473 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4476 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4477 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4480 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_b0_bt_2_921600 },
4485 * The below card is a little controversial since it is the
4486 * subject of a PCI vendor/device ID clash. (See
4487 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4488 * For now just used the hex ID 0x950a.
4490 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4491 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4492 0, 0, pbn_b0_2_115200 },
4493 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4494 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4495 0, 0, pbn_b0_2_115200 },
4496 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4500 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4502 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b0_bt_2_921600 },
4508 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 * Oxford Semiconductor Inc. Tornado PCI express device range.
4515 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_oxsemi_1_4000000 },
4524 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_oxsemi_1_4000000 },
4527 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_oxsemi_1_4000000 },
4536 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_oxsemi_1_4000000 },
4539 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_oxsemi_2_4000000 },
4554 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_oxsemi_2_4000000 },
4557 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 pbn_oxsemi_4_4000000 },
4560 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562 pbn_oxsemi_4_4000000 },
4563 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 pbn_oxsemi_8_4000000 },
4566 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_oxsemi_8_4000000 },
4569 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_oxsemi_1_4000000 },
4572 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_oxsemi_1_4000000 },
4575 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_oxsemi_1_4000000 },
4578 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_oxsemi_1_4000000 },
4581 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_oxsemi_1_4000000 },
4584 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_oxsemi_1_4000000 },
4587 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_oxsemi_1_4000000 },
4590 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_oxsemi_1_4000000 },
4593 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_oxsemi_1_4000000 },
4596 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_oxsemi_1_4000000 },
4599 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_oxsemi_1_4000000 },
4602 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_oxsemi_1_4000000 },
4605 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_oxsemi_1_4000000 },
4608 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_oxsemi_1_4000000 },
4611 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_oxsemi_1_4000000 },
4614 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_oxsemi_1_4000000 },
4617 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_oxsemi_1_4000000 },
4620 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_oxsemi_1_4000000 },
4623 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_oxsemi_1_4000000 },
4626 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_oxsemi_1_4000000 },
4629 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_oxsemi_1_4000000 },
4632 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_oxsemi_1_4000000 },
4635 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_oxsemi_1_4000000 },
4638 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_oxsemi_1_4000000 },
4641 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_oxsemi_1_4000000 },
4644 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_oxsemi_1_4000000 },
4648 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4650 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4651 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4652 pbn_oxsemi_1_4000000 },
4653 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4654 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4655 pbn_oxsemi_2_4000000 },
4656 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4657 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4658 pbn_oxsemi_4_4000000 },
4659 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4660 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4661 pbn_oxsemi_8_4000000 },
4664 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4666 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4667 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4668 pbn_oxsemi_2_4000000 },
4671 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4672 * from skokodyn@yahoo.com
4674 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4675 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4677 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4678 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4680 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4681 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4683 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4684 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4688 * Digitan DS560-558, from jimd@esoft.com
4690 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 * Titan Electronic cards
4696 * The 400L and 800L have a custom setup quirk.
4698 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_b1_bt_2_921600 },
4716 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_b0_bt_4_921600 },
4719 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_b0_bt_8_921600 },
4722 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_b4_bt_2_921600 },
4725 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 pbn_b4_bt_4_921600 },
4728 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_b4_bt_8_921600 },
4731 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_oxsemi_1_4000000 },
4743 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_oxsemi_2_4000000 },
4746 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_oxsemi_4_4000000 },
4749 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_oxsemi_8_4000000 },
4752 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_oxsemi_2_4000000 },
4755 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_oxsemi_2_4000000 },
4758 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_b0_bt_2_921600 },
4761 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_b2_bt_2_921600 },
4786 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b2_bt_2_921600 },
4789 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b2_bt_2_921600 },
4792 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 pbn_b2_bt_4_921600 },
4795 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797 pbn_b2_bt_4_921600 },
4798 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_b2_bt_4_921600 },
4801 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812 pbn_b0_bt_2_921600 },
4813 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815 pbn_b0_bt_2_921600 },
4816 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818 pbn_b0_bt_2_921600 },
4819 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4821 pbn_b0_bt_4_921600 },
4822 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4824 pbn_b0_bt_4_921600 },
4825 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4827 pbn_b0_bt_4_921600 },
4828 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830 pbn_b0_bt_8_921600 },
4831 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4833 pbn_b0_bt_8_921600 },
4834 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836 pbn_b0_bt_8_921600 },
4839 * Computone devices submitted by Doug McNash dmcnash@computone.com
4841 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4842 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4843 0, 0, pbn_computone_4 },
4844 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4845 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4846 0, 0, pbn_computone_8 },
4847 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4848 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4849 0, 0, pbn_computone_6 },
4851 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4855 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4856 pbn_b0_bt_1_921600 },
4861 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4862 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4863 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4864 pbn_b0_bt_1_921600 },
4866 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4867 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4868 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4869 pbn_b0_bt_1_921600 },
4872 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4874 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 pbn_b0_bt_8_115200 },
4877 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b0_bt_8_115200 },
4881 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883 pbn_b0_bt_2_115200 },
4884 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_b0_bt_2_115200 },
4887 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 pbn_b0_bt_2_115200 },
4890 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 pbn_b0_bt_2_115200 },
4893 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b0_bt_2_115200 },
4896 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b0_bt_4_460800 },
4899 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b0_bt_4_460800 },
4902 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b0_bt_2_460800 },
4905 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b0_bt_2_460800 },
4908 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_b0_bt_2_460800 },
4911 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 pbn_b0_bt_1_115200 },
4914 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 pbn_b0_bt_1_460800 },
4919 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4920 * Cards are identified by their subsystem vendor IDs, which
4921 * (in hex) match the model number.
4923 * Note that JC140x are RS422/485 cards which require ox950
4924 * ACR = 0x10, and as such are not currently fully supported.
4926 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4927 0x1204, 0x0004, 0, 0,
4929 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4930 0x1208, 0x0004, 0, 0,
4932 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4933 0x1402, 0x0002, 0, 0,
4934 pbn_b0_2_921600 }, */
4935 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4936 0x1404, 0x0004, 0, 0,
4937 pbn_b0_4_921600 }, */
4938 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4939 0x1208, 0x0004, 0, 0,
4942 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4943 0x1204, 0x0004, 0, 0,
4945 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4946 0x1208, 0x0004, 0, 0,
4948 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4949 0x1208, 0x0004, 0, 0,
4952 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4954 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4961 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 * RAStel 2 port modem, gerg@moreton.com.au
4968 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970 pbn_b2_bt_2_115200 },
4973 * EKF addition for i960 Boards form EKF with serial port
4975 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4976 0xE4BF, PCI_ANY_ID, 0, 0,
4980 * Xircom Cardbus/Ethernet combos
4982 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4988 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 * Untested PCI modems, sent in from various folks...
4997 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4999 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5000 0x1048, 0x1500, 0, 0,
5003 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5010 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5011 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5013 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5033 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5034 PCI_ANY_ID, PCI_ANY_ID,
5036 0, pbn_exar_XR17C152 },
5037 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5038 PCI_ANY_ID, PCI_ANY_ID,
5040 0, pbn_exar_XR17C154 },
5041 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5042 PCI_ANY_ID, PCI_ANY_ID,
5044 0, pbn_exar_XR17C158 },
5046 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5048 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5049 PCI_ANY_ID, PCI_ANY_ID,
5051 0, pbn_exar_XR17V352 },
5052 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5053 PCI_ANY_ID, PCI_ANY_ID,
5055 0, pbn_exar_XR17V354 },
5056 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5057 PCI_ANY_ID, PCI_ANY_ID,
5059 0, pbn_exar_XR17V358 },
5060 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5061 PCI_ANY_ID, PCI_ANY_ID,
5063 0, pbn_exar_XR17V4358 },
5064 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5065 PCI_ANY_ID, PCI_ANY_ID,
5067 0, pbn_exar_XR17V8358 },
5069 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5071 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5072 PCI_ANY_ID, PCI_ANY_ID,
5074 0, pbn_pericom_PI7C9X7951 },
5075 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5076 PCI_ANY_ID, PCI_ANY_ID,
5078 0, pbn_pericom_PI7C9X7952 },
5079 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5080 PCI_ANY_ID, PCI_ANY_ID,
5082 0, pbn_pericom_PI7C9X7954 },
5083 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5084 PCI_ANY_ID, PCI_ANY_ID,
5086 0, pbn_pericom_PI7C9X7958 },
5088 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5090 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5096 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5097 PCI_ANY_ID, PCI_ANY_ID,
5099 pbn_b1_bt_1_115200 },
5104 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5110 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5114 * Perle PCI-RAS cards
5116 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5117 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5118 0, 0, pbn_b2_4_921600 },
5119 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5120 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5121 0, 0, pbn_b2_8_921600 },
5124 * Mainpine series cards: Fairly standard layout but fools
5125 * parts of the autodetect in some cases and uses otherwise
5126 * unmatched communications subclasses in the PCI Express case
5129 { /* RockForceDUO */
5130 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5131 PCI_VENDOR_ID_MAINPINE, 0x0200,
5132 0, 0, pbn_b0_2_115200 },
5133 { /* RockForceQUATRO */
5134 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5135 PCI_VENDOR_ID_MAINPINE, 0x0300,
5136 0, 0, pbn_b0_4_115200 },
5137 { /* RockForceDUO+ */
5138 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5139 PCI_VENDOR_ID_MAINPINE, 0x0400,
5140 0, 0, pbn_b0_2_115200 },
5141 { /* RockForceQUATRO+ */
5142 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5143 PCI_VENDOR_ID_MAINPINE, 0x0500,
5144 0, 0, pbn_b0_4_115200 },
5146 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5147 PCI_VENDOR_ID_MAINPINE, 0x0600,
5148 0, 0, pbn_b0_2_115200 },
5150 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5151 PCI_VENDOR_ID_MAINPINE, 0x0700,
5152 0, 0, pbn_b0_4_115200 },
5153 { /* RockForceOCTO+ */
5154 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5155 PCI_VENDOR_ID_MAINPINE, 0x0800,
5156 0, 0, pbn_b0_8_115200 },
5157 { /* RockForceDUO+ */
5158 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5159 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5160 0, 0, pbn_b0_2_115200 },
5161 { /* RockForceQUARTRO+ */
5162 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5163 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5164 0, 0, pbn_b0_4_115200 },
5165 { /* RockForceOCTO+ */
5166 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5167 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5168 0, 0, pbn_b0_8_115200 },
5170 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5171 PCI_VENDOR_ID_MAINPINE, 0x2000,
5172 0, 0, pbn_b0_1_115200 },
5174 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5175 PCI_VENDOR_ID_MAINPINE, 0x2100,
5176 0, 0, pbn_b0_1_115200 },
5178 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5179 PCI_VENDOR_ID_MAINPINE, 0x2200,
5180 0, 0, pbn_b0_2_115200 },
5182 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5183 PCI_VENDOR_ID_MAINPINE, 0x2300,
5184 0, 0, pbn_b0_2_115200 },
5186 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5187 PCI_VENDOR_ID_MAINPINE, 0x2400,
5188 0, 0, pbn_b0_4_115200 },
5190 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5191 PCI_VENDOR_ID_MAINPINE, 0x2500,
5192 0, 0, pbn_b0_4_115200 },
5194 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5195 PCI_VENDOR_ID_MAINPINE, 0x2600,
5196 0, 0, pbn_b0_8_115200 },
5198 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5199 PCI_VENDOR_ID_MAINPINE, 0x2700,
5200 0, 0, pbn_b0_8_115200 },
5201 { /* IQ Express D1 */
5202 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5203 PCI_VENDOR_ID_MAINPINE, 0x3000,
5204 0, 0, pbn_b0_1_115200 },
5205 { /* IQ Express F1 */
5206 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5207 PCI_VENDOR_ID_MAINPINE, 0x3100,
5208 0, 0, pbn_b0_1_115200 },
5209 { /* IQ Express D2 */
5210 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5211 PCI_VENDOR_ID_MAINPINE, 0x3200,
5212 0, 0, pbn_b0_2_115200 },
5213 { /* IQ Express F2 */
5214 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5215 PCI_VENDOR_ID_MAINPINE, 0x3300,
5216 0, 0, pbn_b0_2_115200 },
5217 { /* IQ Express D4 */
5218 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5219 PCI_VENDOR_ID_MAINPINE, 0x3400,
5220 0, 0, pbn_b0_4_115200 },
5221 { /* IQ Express F4 */
5222 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5223 PCI_VENDOR_ID_MAINPINE, 0x3500,
5224 0, 0, pbn_b0_4_115200 },
5225 { /* IQ Express D8 */
5226 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5227 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5228 0, 0, pbn_b0_8_115200 },
5229 { /* IQ Express F8 */
5230 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5231 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5232 0, 0, pbn_b0_8_115200 },
5236 * PA Semi PA6T-1682M on-chip UART
5238 { PCI_VENDOR_ID_PASEMI, 0xa004,
5239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5243 * National Instruments
5245 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5248 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5251 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5253 pbn_b1_bt_4_115200 },
5254 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5256 pbn_b1_bt_2_115200 },
5257 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5259 pbn_b1_bt_4_115200 },
5260 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5262 pbn_b1_bt_2_115200 },
5263 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5266 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5269 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5271 pbn_b1_bt_4_115200 },
5272 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5274 pbn_b1_bt_2_115200 },
5275 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5277 pbn_b1_bt_4_115200 },
5278 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5280 pbn_b1_bt_2_115200 },
5281 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5284 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5287 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5290 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5293 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5296 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5299 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5302 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5305 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5308 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5311 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5314 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5319 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5321 { PCI_VENDOR_ID_ADDIDATA,
5322 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5329 { PCI_VENDOR_ID_ADDIDATA,
5330 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5337 { PCI_VENDOR_ID_ADDIDATA,
5338 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5345 { PCI_VENDOR_ID_AMCC,
5346 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5353 { PCI_VENDOR_ID_ADDIDATA,
5354 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5361 { PCI_VENDOR_ID_ADDIDATA,
5362 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5369 { PCI_VENDOR_ID_ADDIDATA,
5370 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5377 { PCI_VENDOR_ID_ADDIDATA,
5378 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5385 { PCI_VENDOR_ID_ADDIDATA,
5386 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5393 { PCI_VENDOR_ID_ADDIDATA,
5394 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5401 { PCI_VENDOR_ID_ADDIDATA,
5402 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5409 { PCI_VENDOR_ID_ADDIDATA,
5410 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5415 pbn_ADDIDATA_PCIe_4_3906250 },
5417 { PCI_VENDOR_ID_ADDIDATA,
5418 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5423 pbn_ADDIDATA_PCIe_2_3906250 },
5425 { PCI_VENDOR_ID_ADDIDATA,
5426 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5431 pbn_ADDIDATA_PCIe_1_3906250 },
5433 { PCI_VENDOR_ID_ADDIDATA,
5434 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5439 pbn_ADDIDATA_PCIe_8_3906250 },
5441 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5442 PCI_VENDOR_ID_IBM, 0x0299,
5443 0, 0, pbn_b0_bt_2_115200 },
5446 * other NetMos 9835 devices are most likely handled by the
5447 * parport_serial driver, check drivers/parport/parport_serial.c
5448 * before adding them here.
5451 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5453 0, 0, pbn_b0_1_115200 },
5455 /* the 9901 is a rebranded 9912 */
5456 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5458 0, 0, pbn_b0_1_115200 },
5460 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5462 0, 0, pbn_b0_1_115200 },
5464 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5466 0, 0, pbn_b0_1_115200 },
5468 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5470 0, 0, pbn_b0_1_115200 },
5472 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5474 0, 0, pbn_NETMOS9900_2s_115200 },
5477 * Best Connectivity and Rosewill PCI Multi I/O cards
5480 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5482 0, 0, pbn_b0_1_115200 },
5484 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5486 0, 0, pbn_b0_bt_2_115200 },
5488 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5490 0, 0, pbn_b0_bt_4_115200 },
5492 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5494 pbn_ce4100_1_115200 },
5495 /* Intel BayTrail */
5496 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5497 PCI_ANY_ID, PCI_ANY_ID,
5498 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5500 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5501 PCI_ANY_ID, PCI_ANY_ID,
5502 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5504 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5505 PCI_ANY_ID, PCI_ANY_ID,
5506 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5508 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5509 PCI_ANY_ID, PCI_ANY_ID,
5510 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5513 /* Intel Broadwell */
5514 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5515 PCI_ANY_ID, PCI_ANY_ID,
5516 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5518 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5519 PCI_ANY_ID, PCI_ANY_ID,
5520 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5526 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5532 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5537 * Broadcom TruManage
5539 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5541 pbn_brcm_trumanage },
5544 * AgeStar as-prs2-009
5546 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5547 PCI_ANY_ID, PCI_ANY_ID,
5548 0, 0, pbn_b0_bt_2_115200 },
5551 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5552 * so not listed here.
5554 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5555 PCI_ANY_ID, PCI_ANY_ID,
5556 0, 0, pbn_b0_bt_4_115200 },
5558 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5559 PCI_ANY_ID, PCI_ANY_ID,
5560 0, 0, pbn_b0_bt_2_115200 },
5562 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5563 PCI_ANY_ID, PCI_ANY_ID,
5564 0, 0, pbn_wch382_2 },
5566 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5567 PCI_ANY_ID, PCI_ANY_ID,
5568 0, 0, pbn_wch384_4 },
5571 * Commtech, Inc. Fastcom adapters
5573 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5574 PCI_ANY_ID, PCI_ANY_ID,
5576 0, pbn_b0_2_1152000_200 },
5577 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5578 PCI_ANY_ID, PCI_ANY_ID,
5580 0, pbn_b0_4_1152000_200 },
5581 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5582 PCI_ANY_ID, PCI_ANY_ID,
5584 0, pbn_b0_4_1152000_200 },
5585 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5586 PCI_ANY_ID, PCI_ANY_ID,
5588 0, pbn_b0_8_1152000_200 },
5589 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5590 PCI_ANY_ID, PCI_ANY_ID,
5592 0, pbn_exar_XR17V352 },
5593 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5594 PCI_ANY_ID, PCI_ANY_ID,
5596 0, pbn_exar_XR17V354 },
5597 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5598 PCI_ANY_ID, PCI_ANY_ID,
5600 0, pbn_exar_XR17V358 },
5602 /* Fintek PCI serial cards */
5603 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5604 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5605 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5608 * These entries match devices with class COMMUNICATION_SERIAL,
5609 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5611 { PCI_ANY_ID, PCI_ANY_ID,
5612 PCI_ANY_ID, PCI_ANY_ID,
5613 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5614 0xffff00, pbn_default },
5615 { PCI_ANY_ID, PCI_ANY_ID,
5616 PCI_ANY_ID, PCI_ANY_ID,
5617 PCI_CLASS_COMMUNICATION_MODEM << 8,
5618 0xffff00, pbn_default },
5619 { PCI_ANY_ID, PCI_ANY_ID,
5620 PCI_ANY_ID, PCI_ANY_ID,
5621 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5622 0xffff00, pbn_default },
5626 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5627 pci_channel_state_t state)
5629 struct serial_private *priv = pci_get_drvdata(dev);
5631 if (state == pci_channel_io_perm_failure)
5632 return PCI_ERS_RESULT_DISCONNECT;
5635 pciserial_suspend_ports(priv);
5637 pci_disable_device(dev);
5639 return PCI_ERS_RESULT_NEED_RESET;
5642 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5646 rc = pci_enable_device(dev);
5649 return PCI_ERS_RESULT_DISCONNECT;
5651 pci_restore_state(dev);
5652 pci_save_state(dev);
5654 return PCI_ERS_RESULT_RECOVERED;
5657 static void serial8250_io_resume(struct pci_dev *dev)
5659 struct serial_private *priv = pci_get_drvdata(dev);
5662 pciserial_resume_ports(priv);
5665 static const struct pci_error_handlers serial8250_err_handler = {
5666 .error_detected = serial8250_io_error_detected,
5667 .slot_reset = serial8250_io_slot_reset,
5668 .resume = serial8250_io_resume,
5671 static struct pci_driver serial_pci_driver = {
5673 .probe = pciserial_init_one,
5674 .remove = pciserial_remove_one,
5676 .pm = &pciserial_pm_ops,
5678 .id_table = serial_pci_tbl,
5679 .err_handler = &serial8250_err_handler,
5682 module_pci_driver(serial_pci_driver);
5684 MODULE_LICENSE("GPL");
5685 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5686 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);