drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  59                 u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_gadget_ep_cmd_params params;
  62         struct dwc3_trb                 *trb;
  63         struct dwc3_ep                  *dep;
  64
  65         int                             ret;
  66
  67         dep = dwc->eps[epnum];
  68         if (dep->flags & DWC3_EP_BUSY) {
  69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  70                 return 0;
  71         }
  72
  73         trb = &dwc->ep0_trb[dep->free_slot];
  74
  75         if (chain)
  76                 dep->free_slot++;
  77
  78         trb->bpl = lower_32_bits(buf_dma);
  79         trb->bph = upper_32_bits(buf_dma);
  80         trb->size = len;
  81         trb->ctrl = type;
  82
  83         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  84                         | DWC3_TRB_CTRL_ISP_IMI);
  85
  86         if (chain)
  87                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  88         else
  89                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  90                                 | DWC3_TRB_CTRL_LST);
  91
  92         if (chain)
  93                 return 0;
  94
  95         memset(&params, 0, sizeof(params));
  96         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  97         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  98
  99         trace_dwc3_prepare_trb(dep, trb);
 100
 101         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 102                         DWC3_DEPCMD_STARTTRANSFER, &params);
 103         if (ret < 0) {
 104                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 105                                 dep->name);
 106                 return ret;
 107         }
 108
 109         dep->flags |= DWC3_EP_BUSY;
 110         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 111                         dep->number);
 112
 113         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 114
 115         return 0;
 116 }
 117
 118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 119                 struct dwc3_request *req)
 120 {
 121         struct dwc3             *dwc = dep->dwc;
 122
 123         req->request.actual     = 0;
 124         req->request.status     = -EINPROGRESS;
 125         req->epnum              = dep->number;
 126
 127         list_add_tail(&req->list, &dep->request_list);
 128
 129         /*
 130          * Gadget driver might not be quick enough to queue a request
 131          * before we get a Transfer Not Ready event on this endpoint.
 132          *
 133          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 134          * flag is set, it's telling us that as soon as Gadget queues the
 135          * required request, we should kick the transfer here because the
 136          * IRQ we were waiting for is long gone.
 137          */
 138         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 139                 unsigned        direction;
 140
 141                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 142
 143                 if (dev_WARN(dwc->dev, dwc->ep0state != EP0_DATA_PHASE,
 144                                                 "Unexpected pending request\n"))
 145                         return 0;
 146
 147                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 148
 149                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 150                                 DWC3_EP0_DIR_IN);
 151
 152                 return 0;
 153         }
 154
 155         /*
 156          * In case gadget driver asked us to delay the STATUS phase,
 157          * handle it here.
 158          */
 159         if (dwc->delayed_status) {
 160                 unsigned        direction;
 161
 162                 direction = !dwc->ep0_expect_in;
 163                 dwc->delayed_status = false;
 164                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 165
 166                 if (dwc->ep0state == EP0_STATUS_PHASE)
 167                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 168                 else
 169                         dwc3_trace(trace_dwc3_ep0,
 170                                         "too early for delayed status");
 171
 172                 return 0;
 173         }
 174
 175         /*
 176          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 177          *
 178          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 179          * come before issueing Start Transfer command, but if we do, we will
 180          * miss situations where the host starts another SETUP phase instead of
 181          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 182          * Layer Compliance Suite.
 183          *
 184          * The problem surfaces due to the fact that in case of back-to-back
 185          * SETUP packets there will be no XferNotReady(DATA) generated and we
 186          * will be stuck waiting for XferNotReady(DATA) forever.
 187          *
 188          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 189          * it tells us to start Data Phase right away. It also mentions that if
 190          * we receive a SETUP phase instead of the DATA phase, core will issue
 191          * XferComplete for the DATA phase, before actually initiating it in
 192          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 193          * can only be used to print some debugging logs, as the core expects
 194          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 195          * just so it completes right away, without transferring anything and,
 196          * only then, we can go back to the SETUP phase.
 197          *
 198          * Because of this scenario, SNPS decided to change the programming
 199          * model of control transfers and support on-demand transfers only for
 200          * the STATUS phase. To fix the issue we have now, we will always wait
 201          * for gadget driver to queue the DATA phase's struct usb_request, then
 202          * start it right away.
 203          *
 204          * If we're actually in a 2-stage transfer, we will wait for
 205          * XferNotReady(STATUS).
 206          */
 207         if (dwc->three_stage_setup) {
 208                 unsigned        direction;
 209
 210                 direction = dwc->ep0_expect_in;
 211                 dwc->ep0state = EP0_DATA_PHASE;
 212
 213                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 214
 215                 dep->flags &= ~DWC3_EP0_DIR_IN;
 216         }
 217
 218         return 0;
 219 }
 220
 221 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 222                 gfp_t gfp_flags)
 223 {
 224         struct dwc3_request             *req = to_dwc3_request(request);
 225         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 226         struct dwc3                     *dwc = dep->dwc;
 227
 228         unsigned long                   flags;
 229
 230         int                             ret;
 231
 232         spin_lock_irqsave(&dwc->lock, flags);
 233         if (!dep->endpoint.desc) {
 234                 dwc3_trace(trace_dwc3_ep0,
 235                                 "trying to queue request %p to disabled %s",
 236                                 request, dep->name);
 237                 ret = -ESHUTDOWN;
 238                 goto out;
 239         }
 240
 241         /* we share one TRB for ep0/1 */
 242         if (!list_empty(&dep->request_list)) {
 243                 ret = -EBUSY;
 244                 goto out;
 245         }
 246
 247         dwc3_trace(trace_dwc3_ep0,
 248                         "queueing request %p to %s length %d state '%s'",
 249                         request, dep->name, request->length,
 250                         dwc3_ep0_state_string(dwc->ep0state));
 251
 252         ret = __dwc3_gadget_ep0_queue(dep, req);
 253
 254 out:
 255         spin_unlock_irqrestore(&dwc->lock, flags);
 256
 257         return ret;
 258 }
 259
 260 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 261 {
 262         struct dwc3_ep          *dep;
 263
 264         /* reinitialize physical ep1 */
 265         dep = dwc->eps[1];
 266         dep->flags = DWC3_EP_ENABLED;
 267
 268         /* stall is always issued on EP0 */
 269         dep = dwc->eps[0];
 270         __dwc3_gadget_ep_set_halt(dep, 1, false);
 271         dep->flags = DWC3_EP_ENABLED;
 272         dwc->delayed_status = false;
 273
 274         if (!list_empty(&dep->request_list)) {
 275                 struct dwc3_request     *req;
 276
 277                 req = next_request(&dep->request_list);
 278                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 279         }
 280
 281         dwc->ep0state = EP0_SETUP_PHASE;
 282         dwc3_ep0_out_start(dwc);
 283 }
 284
 285 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 286 {
 287         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 288         struct dwc3                     *dwc = dep->dwc;
 289
 290         dwc3_ep0_stall_and_restart(dwc);
 291
 292         return 0;
 293 }
 294
 295 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 296 {
 297         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 298         struct dwc3                     *dwc = dep->dwc;
 299         unsigned long                   flags;
 300         int                             ret;
 301
 302         spin_lock_irqsave(&dwc->lock, flags);
 303         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 304         spin_unlock_irqrestore(&dwc->lock, flags);
 305
 306         return ret;
 307 }
 308
 309 void dwc3_ep0_out_start(struct dwc3 *dwc)
 310 {
 311         int                             ret;
 312
 313         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 314                         DWC3_TRBCTL_CONTROL_SETUP, false);
 315         WARN_ON(ret < 0);
 316 }
 317
 318 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 319 {
 320         struct dwc3_ep          *dep;
 321         u32                     windex = le16_to_cpu(wIndex_le);
 322         u32                     epnum;
 323
 324         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 325         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 326                 epnum |= 1;
 327
 328         dep = dwc->eps[epnum];
 329         if (dep->flags & DWC3_EP_ENABLED)
 330                 return dep;
 331
 332         return NULL;
 333 }
 334
 335 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 336 {
 337 }
 338 /*
 339  * ch 9.4.5
 340  */
 341 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 342                 struct usb_ctrlrequest *ctrl)
 343 {
 344         struct dwc3_ep          *dep;
 345         u32                     recip;
 346         u32                     reg;
 347         u16                     usb_status = 0;
 348         __le16                  *response_pkt;
 349
 350         recip = ctrl->bRequestType & USB_RECIP_MASK;
 351         switch (recip) {
 352         case USB_RECIP_DEVICE:
 353                 /*
 354                  * LTM will be set once we know how to set this in HW.
 355                  */
 356                 usb_status |= dwc->gadget.is_selfpowered;
 357
 358                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 359                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 360                         if (reg & DWC3_DCTL_INITU1ENA)
 361                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 362                         if (reg & DWC3_DCTL_INITU2ENA)
 363                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 364                 }
 365
 366                 break;
 367
 368         case USB_RECIP_INTERFACE:
 369                 /*
 370                  * Function Remote Wake Capable D0
 371                  * Function Remote Wakeup       D1
 372                  */
 373                 break;
 374
 375         case USB_RECIP_ENDPOINT:
 376                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 377                 if (!dep)
 378                         return -EINVAL;
 379
 380                 if (dep->flags & DWC3_EP_STALL)
 381                         usb_status = 1 << USB_ENDPOINT_HALT;
 382                 break;
 383         default:
 384                 return -EINVAL;
 385         }
 386
 387         response_pkt = (__le16 *) dwc->setup_buf;
 388         *response_pkt = cpu_to_le16(usb_status);
 389
 390         dep = dwc->eps[0];
 391         dwc->ep0_usb_req.dep = dep;
 392         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 393         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 394         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 395
 396         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 397 }
 398
 399 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 400                 struct usb_ctrlrequest *ctrl, int set)
 401 {
 402         struct dwc3_ep          *dep;
 403         u32                     recip;
 404         u32                     wValue;
 405         u32                     wIndex;
 406         u32                     reg;
 407         int                     ret;
 408         enum usb_device_state   state;
 409
 410         wValue = le16_to_cpu(ctrl->wValue);
 411         wIndex = le16_to_cpu(ctrl->wIndex);
 412         recip = ctrl->bRequestType & USB_RECIP_MASK;
 413         state = dwc->gadget.state;
 414
 415         switch (recip) {
 416         case USB_RECIP_DEVICE:
 417
 418                 switch (wValue) {
 419                 case USB_DEVICE_REMOTE_WAKEUP:
 420                         break;
 421                 /*
 422                  * 9.4.1 says only only for SS, in AddressState only for
 423                  * default control pipe
 424                  */
 425                 case USB_DEVICE_U1_ENABLE:
 426                         if (state != USB_STATE_CONFIGURED)
 427                                 return -EINVAL;
 428                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 429                                 return -EINVAL;
 430
 431                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 432                         if (set)
 433                                 reg |= DWC3_DCTL_INITU1ENA;
 434                         else
 435                                 reg &= ~DWC3_DCTL_INITU1ENA;
 436                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 437                         break;
 438
 439                 case USB_DEVICE_U2_ENABLE:
 440                         if (state != USB_STATE_CONFIGURED)
 441                                 return -EINVAL;
 442                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 443                                 return -EINVAL;
 444
 445                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 446                         if (set)
 447                                 reg |= DWC3_DCTL_INITU2ENA;
 448                         else
 449                                 reg &= ~DWC3_DCTL_INITU2ENA;
 450                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 451                         break;
 452
 453                 case USB_DEVICE_LTM_ENABLE:
 454                         return -EINVAL;
 455
 456                 case USB_DEVICE_TEST_MODE:
 457                         if ((wIndex & 0xff) != 0)
 458                                 return -EINVAL;
 459                         if (!set)
 460                                 return -EINVAL;
 461
 462                         dwc->test_mode_nr = wIndex >> 8;
 463                         dwc->test_mode = true;
 464                         break;
 465                 default:
 466                         return -EINVAL;
 467                 }
 468                 break;
 469
 470         case USB_RECIP_INTERFACE:
 471                 switch (wValue) {
 472                 case USB_INTRF_FUNC_SUSPEND:
 473                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 474                                 /* XXX enable Low power suspend */
 475                                 ;
 476                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 477                                 /* XXX enable remote wakeup */
 478                                 ;
 479                         break;
 480                 default:
 481                         return -EINVAL;
 482                 }
 483                 break;
 484
 485         case USB_RECIP_ENDPOINT:
 486                 switch (wValue) {
 487                 case USB_ENDPOINT_HALT:
 488                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 489                         if (!dep)
 490                                 return -EINVAL;
 491                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 492                                 break;
 493                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 494                         if (ret)
 495                                 return -EINVAL;
 496                         break;
 497                 default:
 498                         return -EINVAL;
 499                 }
 500                 break;
 501
 502         default:
 503                 return -EINVAL;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 510 {
 511         enum usb_device_state state = dwc->gadget.state;
 512         u32 addr;
 513         u32 reg;
 514
 515         addr = le16_to_cpu(ctrl->wValue);
 516         if (addr > 127) {
 517                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 518                 return -EINVAL;
 519         }
 520
 521         if (state == USB_STATE_CONFIGURED) {
 522                 dwc3_trace(trace_dwc3_ep0,
 523                                 "trying to set address when configured");
 524                 return -EINVAL;
 525         }
 526
 527         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 528         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 529         reg |= DWC3_DCFG_DEVADDR(addr);
 530         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 531
 532         if (addr)
 533                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 534         else
 535                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 536
 537         return 0;
 538 }
 539
 540 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 541 {
 542         int ret;
 543
 544         spin_unlock(&dwc->lock);
 545         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 546         spin_lock(&dwc->lock);
 547         return ret;
 548 }
 549
 550 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 551 {
 552         enum usb_device_state state = dwc->gadget.state;
 553         u32 cfg;
 554         int ret;
 555         u32 reg;
 556
 557         dwc->start_config_issued = false;
 558         cfg = le16_to_cpu(ctrl->wValue);
 559
 560         switch (state) {
 561         case USB_STATE_DEFAULT:
 562                 return -EINVAL;
 563
 564         case USB_STATE_ADDRESS:
 565                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 566                 /* if the cfg matches and the cfg is non zero */
 567                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 568
 569                         /*
 570                          * only change state if set_config has already
 571                          * been processed. If gadget driver returns
 572                          * USB_GADGET_DELAYED_STATUS, we will wait
 573                          * to change the state on the next usb_ep_queue()
 574                          */
 575                         if (ret == 0)
 576                                 usb_gadget_set_state(&dwc->gadget,
 577                                                 USB_STATE_CONFIGURED);
 578
 579                         /*
 580                          * Enable transition to U1/U2 state when
 581                          * nothing is pending from application.
 582                          */
 583                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 584                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 585                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 586
 587                         dwc->resize_fifos = true;
 588                         dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
 589                 }
 590                 break;
 591
 592         case USB_STATE_CONFIGURED:
 593                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 594                 if (!cfg && !ret)
 595                         usb_gadget_set_state(&dwc->gadget,
 596                                         USB_STATE_ADDRESS);
 597                 break;
 598         default:
 599                 ret = -EINVAL;
 600         }
 601         return ret;
 602 }
 603
 604 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 605 {
 606         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 607         struct dwc3     *dwc = dep->dwc;
 608
 609         u32             param = 0;
 610         u32             reg;
 611
 612         struct timing {
 613                 u8      u1sel;
 614                 u8      u1pel;
 615                 u16     u2sel;
 616                 u16     u2pel;
 617         } __packed timing;
 618
 619         int             ret;
 620
 621         memcpy(&timing, req->buf, sizeof(timing));
 622
 623         dwc->u1sel = timing.u1sel;
 624         dwc->u1pel = timing.u1pel;
 625         dwc->u2sel = le16_to_cpu(timing.u2sel);
 626         dwc->u2pel = le16_to_cpu(timing.u2pel);
 627
 628         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 629         if (reg & DWC3_DCTL_INITU2ENA)
 630                 param = dwc->u2pel;
 631         if (reg & DWC3_DCTL_INITU1ENA)
 632                 param = dwc->u1pel;
 633
 634         /*
 635          * According to Synopsys Databook, if parameter is
 636          * greater than 125, a value of zero should be
 637          * programmed in the register.
 638          */
 639         if (param > 125)
 640                 param = 0;
 641
 642         /* now that we have the time, issue DGCMD Set Sel */
 643         ret = dwc3_send_gadget_generic_command(dwc,
 644                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 645         WARN_ON(ret < 0);
 646 }
 647
 648 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 649 {
 650         struct dwc3_ep  *dep;
 651         enum usb_device_state state = dwc->gadget.state;
 652         u16             wLength;
 653         u16             wValue;
 654
 655         if (state == USB_STATE_DEFAULT)
 656                 return -EINVAL;
 657
 658         wValue = le16_to_cpu(ctrl->wValue);
 659         wLength = le16_to_cpu(ctrl->wLength);
 660
 661         if (wLength != 6) {
 662                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 663                                 wLength);
 664                 return -EINVAL;
 665         }
 666
 667         /*
 668          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 669          * queue a usb_request for 6 bytes.
 670          *
 671          * Remember, though, this controller can't handle non-wMaxPacketSize
 672          * aligned transfers on the OUT direction, so we queue a request for
 673          * wMaxPacketSize instead.
 674          */
 675         dep = dwc->eps[0];
 676         dwc->ep0_usb_req.dep = dep;
 677         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 678         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 679         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 680
 681         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 682 }
 683
 684 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 685 {
 686         u16             wLength;
 687         u16             wValue;
 688         u16             wIndex;
 689
 690         wValue = le16_to_cpu(ctrl->wValue);
 691         wLength = le16_to_cpu(ctrl->wLength);
 692         wIndex = le16_to_cpu(ctrl->wIndex);
 693
 694         if (wIndex || wLength)
 695                 return -EINVAL;
 696
 697         /*
 698          * REVISIT It's unclear from Databook what to do with this
 699          * value. For now, just cache it.
 700          */
 701         dwc->isoch_delay = wValue;
 702
 703         return 0;
 704 }
 705
 706 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 707 {
 708         int ret;
 709
 710         switch (ctrl->bRequest) {
 711         case USB_REQ_GET_STATUS:
 712                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 713                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 714                 break;
 715         case USB_REQ_CLEAR_FEATURE:
 716                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 717                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 718                 break;
 719         case USB_REQ_SET_FEATURE:
 720                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 721                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 722                 break;
 723         case USB_REQ_SET_ADDRESS:
 724                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 725                 ret = dwc3_ep0_set_address(dwc, ctrl);
 726                 break;
 727         case USB_REQ_SET_CONFIGURATION:
 728                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 729                 ret = dwc3_ep0_set_config(dwc, ctrl);
 730                 break;
 731         case USB_REQ_SET_SEL:
 732                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 733                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 734                 break;
 735         case USB_REQ_SET_ISOCH_DELAY:
 736                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 737                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 738                 break;
 739         case USB_REQ_SET_INTERFACE:
 740                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_INTERFACE");
 741                 dwc->start_config_issued = false;
 742                 /* Fall through */
 743         default:
 744                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 745                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 746                 break;
 747         }
 748
 749         return ret;
 750 }
 751
 752 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 753                 const struct dwc3_event_depevt *event)
 754 {
 755         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 756         int ret = -EINVAL;
 757         u32 len;
 758
 759         if (!dwc->gadget_driver)
 760                 goto out;
 761
 762         trace_dwc3_ctrl_req(ctrl);
 763
 764         len = le16_to_cpu(ctrl->wLength);
 765         if (!len) {
 766                 dwc->three_stage_setup = false;
 767                 dwc->ep0_expect_in = false;
 768                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 769         } else {
 770                 dwc->three_stage_setup = true;
 771                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 772                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 773         }
 774
 775         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 776                 ret = dwc3_ep0_std_request(dwc, ctrl);
 777         else
 778                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 779
 780         if (ret == USB_GADGET_DELAYED_STATUS)
 781                 dwc->delayed_status = true;
 782
 783 out:
 784         if (ret < 0)
 785                 dwc3_ep0_stall_and_restart(dwc);
 786 }
 787
 788 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 789                 const struct dwc3_event_depevt *event)
 790 {
 791         struct dwc3_request     *r = NULL;
 792         struct usb_request      *ur;
 793         struct dwc3_trb         *trb;
 794         struct dwc3_ep          *ep0;
 795         unsigned                transfer_size = 0;
 796         unsigned                maxp;
 797         unsigned                remaining_ur_length;
 798         void                    *buf;
 799         u32                     transferred = 0;
 800         u32                     status;
 801         u32                     length;
 802         u8                      epnum;
 803
 804         epnum = event->endpoint_number;
 805         ep0 = dwc->eps[0];
 806
 807         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 808
 809         trb = dwc->ep0_trb;
 810
 811         trace_dwc3_complete_trb(ep0, trb);
 812
 813         r = next_request(&ep0->request_list);
 814         if (!r)
 815                 return;
 816
 817         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 818         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 819                 dwc->setup_packet_pending = true;
 820
 821                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 822
 823                 if (r)
 824                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 825
 826                 return;
 827         }
 828
 829         ur = &r->request;
 830         buf = ur->buf;
 831         remaining_ur_length = ur->length;
 832
 833         length = trb->size & DWC3_TRB_SIZE_MASK;
 834
 835         maxp = ep0->endpoint.maxpacket;
 836
 837         if (dwc->ep0_bounced) {
 838                 /*
 839                  * Handle the first TRB before handling the bounce buffer if
 840                  * the request length is greater than the bounce buffer size
 841                  */
 842                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 843                         transfer_size = ALIGN(ur->length - maxp, maxp);
 844                         transferred = transfer_size - length;
 845                         buf = (u8 *)buf + transferred;
 846                         ur->actual += transferred;
 847                         remaining_ur_length -= transferred;
 848
 849                         trb++;
 850                         length = trb->size & DWC3_TRB_SIZE_MASK;
 851
 852                         ep0->free_slot = 0;
 853                 }
 854
 855                 transfer_size = roundup((ur->length - transfer_size),
 856                                         maxp);
 857
 858                 transferred = min_t(u32, remaining_ur_length,
 859                                     transfer_size - length);
 860                 memcpy(buf, dwc->ep0_bounce, transferred);
 861         } else {
 862                 transferred = ur->length - length;
 863         }
 864
 865         ur->actual += transferred;
 866
 867         if ((epnum & 1) && ur->actual < ur->length) {
 868                 /* for some reason we did not get everything out */
 869
 870                 dwc3_ep0_stall_and_restart(dwc);
 871         } else {
 872                 dwc3_gadget_giveback(ep0, r, 0);
 873
 874                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 875                                 ur->length && ur->zero) {
 876                         int ret;
 877
 878                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 879
 880                         ret = dwc3_ep0_start_trans(dwc, epnum,
 881                                         dwc->ctrl_req_addr, 0,
 882                                         DWC3_TRBCTL_CONTROL_DATA, false);
 883                         WARN_ON(ret < 0);
 884                 }
 885         }
 886 }
 887
 888 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 889                 const struct dwc3_event_depevt *event)
 890 {
 891         struct dwc3_request     *r;
 892         struct dwc3_ep          *dep;
 893         struct dwc3_trb         *trb;
 894         u32                     status;
 895
 896         dep = dwc->eps[0];
 897         trb = dwc->ep0_trb;
 898
 899         trace_dwc3_complete_trb(dep, trb);
 900
 901         if (!list_empty(&dep->request_list)) {
 902                 r = next_request(&dep->request_list);
 903
 904                 dwc3_gadget_giveback(dep, r, 0);
 905         }
 906
 907         if (dwc->test_mode) {
 908                 int ret;
 909
 910                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 911                 if (ret < 0) {
 912                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 913                                         dwc->test_mode_nr);
 914                         dwc3_ep0_stall_and_restart(dwc);
 915                         return;
 916                 }
 917         }
 918
 919         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 920         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 921                 dwc->setup_packet_pending = true;
 922                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 923         }
 924
 925         dwc->ep0state = EP0_SETUP_PHASE;
 926         dwc3_ep0_out_start(dwc);
 927 }
 928
 929 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 930                         const struct dwc3_event_depevt *event)
 931 {
 932         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 933
 934         dep->flags &= ~DWC3_EP_BUSY;
 935         dep->resource_index = 0;
 936         dwc->setup_packet_pending = false;
 937
 938         switch (dwc->ep0state) {
 939         case EP0_SETUP_PHASE:
 940                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 941                 dwc3_ep0_inspect_setup(dwc, event);
 942                 break;
 943
 944         case EP0_DATA_PHASE:
 945                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 946                 dwc3_ep0_complete_data(dwc, event);
 947                 break;
 948
 949         case EP0_STATUS_PHASE:
 950                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 951                 dwc3_ep0_complete_status(dwc, event);
 952                 break;
 953         default:
 954                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 955         }
 956 }
 957
 958 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 959                 struct dwc3_ep *dep, struct dwc3_request *req)
 960 {
 961         int                     ret;
 962
 963         req->direction = !!dep->number;
 964
 965         if (req->request.length == 0) {
 966                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 967                                 dwc->ctrl_req_addr, 0,
 968                                 DWC3_TRBCTL_CONTROL_DATA, false);
 969         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 970                         && (dep->number == 0)) {
 971                 u32     transfer_size = 0;
 972                 u32     maxpacket;
 973
 974                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 975                                 dep->number);
 976                 if (ret) {
 977                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
 978                         return;
 979                 }
 980
 981                 maxpacket = dep->endpoint.maxpacket;
 982
 983                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 984                         transfer_size = ALIGN(req->request.length - maxpacket,
 985                                               maxpacket);
 986                         ret = dwc3_ep0_start_trans(dwc, dep->number,
 987                                                    req->request.dma,
 988                                                    transfer_size,
 989                                                    DWC3_TRBCTL_CONTROL_DATA,
 990                                                    true);
 991                 }
 992
 993                 transfer_size = roundup((req->request.length - transfer_size),
 994                                         maxpacket);
 995
 996                 dwc->ep0_bounced = true;
 997
 998                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 999                                 dwc->ep0_bounce_addr, transfer_size,
1000                                 DWC3_TRBCTL_CONTROL_DATA, false);
1001         } else {
1002                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1003                                 dep->number);
1004                 if (ret) {
1005                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1006                         return;
1007                 }
1008
1009                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1010                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1011                                 false);
1012         }
1013
1014         WARN_ON(ret < 0);
1015 }
1016
1017 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1018 {
1019         struct dwc3             *dwc = dep->dwc;
1020         u32                     type;
1021
1022         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1023                 : DWC3_TRBCTL_CONTROL_STATUS2;
1024
1025         return dwc3_ep0_start_trans(dwc, dep->number,
1026                         dwc->ctrl_req_addr, 0, type, false);
1027 }
1028
1029 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1030 {
1031         if (dwc->resize_fifos) {
1032                 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
1033                 dwc3_gadget_resize_tx_fifos(dwc);
1034                 dwc->resize_fifos = 0;
1035         }
1036
1037         WARN_ON(dwc3_ep0_start_control_status(dep));
1038 }
1039
1040 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1041                 const struct dwc3_event_depevt *event)
1042 {
1043         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1044
1045         __dwc3_ep0_do_control_status(dwc, dep);
1046 }
1047
1048 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1049 {
1050         struct dwc3_gadget_ep_cmd_params params;
1051         u32                     cmd;
1052         int                     ret;
1053
1054         if (!dep->resource_index)
1055                 return;
1056
1057         cmd = DWC3_DEPCMD_ENDTRANSFER;
1058         cmd |= DWC3_DEPCMD_CMDIOC;
1059         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1060         memset(&params, 0, sizeof(params));
1061         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1062         WARN_ON_ONCE(ret);
1063         dep->resource_index = 0;
1064 }
1065
1066 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1067                 const struct dwc3_event_depevt *event)
1068 {
1069         switch (event->status) {
1070         case DEPEVT_STATUS_CONTROL_DATA:
1071                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1072
1073                 /*
1074                  * We already have a DATA transfer in the controller's cache,
1075                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1076                  * it's for the wrong direction.
1077                  *
1078                  * In that case, we must issue END_TRANSFER command to the Data
1079                  * Phase we already have started and issue SetStall on the
1080                  * control endpoint.
1081                  */
1082                 if (dwc->ep0_expect_in != event->endpoint_number) {
1083                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1084
1085                         dwc3_trace(trace_dwc3_ep0,
1086                                         "Wrong direction for Data phase");
1087                         dwc3_ep0_end_control_data(dwc, dep);
1088                         dwc3_ep0_stall_and_restart(dwc);
1089                         return;
1090                 }
1091
1092                 break;
1093
1094         case DEPEVT_STATUS_CONTROL_STATUS:
1095                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1096                         return;
1097
1098                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1099
1100                 dwc->ep0state = EP0_STATUS_PHASE;
1101
1102                 if (dwc->delayed_status) {
1103                         WARN_ON_ONCE(event->endpoint_number != 1);
1104                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1105                         return;
1106                 }
1107
1108                 dwc3_ep0_do_control_status(dwc, event);
1109         }
1110 }
1111
1112 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1113                 const struct dwc3_event_depevt *event)
1114 {
1115         u8                      epnum = event->endpoint_number;
1116
1117         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1118                         dwc3_ep_event_string(event->endpoint_event),
1119                         epnum >> 1, (epnum & 1) ? "in" : "out",
1120                         dwc3_ep0_state_string(dwc->ep0state));
1121
1122         switch (event->endpoint_event) {
1123         case DWC3_DEPEVT_XFERCOMPLETE:
1124                 dwc3_ep0_xfer_complete(dwc, event);
1125                 break;
1126
1127         case DWC3_DEPEVT_XFERNOTREADY:
1128                 dwc3_ep0_xfernotready(dwc, event);
1129                 break;
1130
1131         case DWC3_DEPEVT_XFERINPROGRESS:
1132         case DWC3_DEPEVT_RXTXFIFOEVT:
1133         case DWC3_DEPEVT_STREAMEVT:
1134         case DWC3_DEPEVT_EPCMDCMPLT:
1135                 break;
1136         }
1137 }