drivers/usb/gadget/mv_u3d_core.c

   1 /*
   2  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/dmapool.h>
  12 #include <linux/kernel.h>
  13 #include <linux/delay.h>
  14 #include <linux/ioport.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/timer.h>
  20 #include <linux/list.h>
  21 #include <linux/notifier.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/device.h>
  25 #include <linux/usb/ch9.h>
  26 #include <linux/usb/gadget.h>
  27 #include <linux/pm.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/platform_data/mv_usb.h>
  32 #include <linux/clk.h>
  33
  34 #include "mv_u3d.h"
  35
  36 #define DRIVER_DESC             "Marvell PXA USB3.0 Device Controller driver"
  37
  38 static const char driver_name[] = "mv_u3d";
  39 static const char driver_desc[] = DRIVER_DESC;
  40
  41 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status);
  42 static void mv_u3d_stop_activity(struct mv_u3d *u3d,
  43                         struct usb_gadget_driver *driver);
  44
  45 /* for endpoint 0 operations */
  46 static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = {
  47         .bLength =              USB_DT_ENDPOINT_SIZE,
  48         .bDescriptorType =      USB_DT_ENDPOINT,
  49         .bEndpointAddress =     0,
  50         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  51         .wMaxPacketSize =       MV_U3D_EP0_MAX_PKT_SIZE,
  52 };
  53
  54 static void mv_u3d_ep0_reset(struct mv_u3d *u3d)
  55 {
  56         struct mv_u3d_ep *ep;
  57         u32 epxcr;
  58         int i;
  59
  60         for (i = 0; i < 2; i++) {
  61                 ep = &u3d->eps[i];
  62                 ep->u3d = u3d;
  63
  64                 /* ep0 ep context, ep0 in and out share the same ep context */
  65                 ep->ep_context = &u3d->ep_context[1];
  66         }
  67
  68         /* reset ep state machine */
  69         /* reset ep0 out */
  70         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
  71         epxcr |= MV_U3D_EPXCR_EP_INIT;
  72         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  73         udelay(5);
  74         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  75         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  76
  77         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  78                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  79                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  80                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  81                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  82         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1);
  83
  84         /* reset ep0 in */
  85         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
  86         epxcr |= MV_U3D_EPXCR_EP_INIT;
  87         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  88         udelay(5);
  89         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  90         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  91
  92         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  93                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  94                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  95                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  96                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  97         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1);
  98 }
  99
 100 static void mv_u3d_ep0_stall(struct mv_u3d *u3d)
 101 {
 102         u32 tmp;
 103         dev_dbg(u3d->dev, "%s\n", __func__);
 104
 105         /* set TX and RX to stall */
 106         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 107         tmp |= MV_U3D_EPXCR_EP_HALT;
 108         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 109
 110         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 111         tmp |= MV_U3D_EPXCR_EP_HALT;
 112         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 113
 114         /* update ep0 state */
 115         u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 116         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 117 }
 118
 119 static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index,
 120         struct mv_u3d_req *curr_req)
 121 {
 122         struct mv_u3d_trb       *curr_trb;
 123         dma_addr_t cur_deq_lo;
 124         struct mv_u3d_ep_context        *curr_ep_context;
 125         int trb_complete, actual, remaining_length = 0;
 126         int direction, ep_num;
 127         int retval = 0;
 128         u32 tmp, status, length;
 129
 130         curr_ep_context = &u3d->ep_context[index];
 131         direction = index % 2;
 132         ep_num = index / 2;
 133
 134         trb_complete = 0;
 135         actual = curr_req->req.length;
 136
 137         while (!list_empty(&curr_req->trb_list)) {
 138                 curr_trb = list_entry(curr_req->trb_list.next,
 139                                         struct mv_u3d_trb, trb_list);
 140                 if (!curr_trb->trb_hw->ctrl.own) {
 141                         dev_err(u3d->dev, "%s, TRB own error!\n",
 142                                 u3d->eps[index].name);
 143                         return 1;
 144                 }
 145
 146                 curr_trb->trb_hw->ctrl.own = 0;
 147                 if (direction == MV_U3D_EP_DIR_OUT) {
 148                         tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo);
 149                         cur_deq_lo =
 150                                 ioread32(&u3d->vuc_regs->rxst[ep_num].curdeqlo);
 151                 } else {
 152                         tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo);
 153                         cur_deq_lo =
 154                                 ioread32(&u3d->vuc_regs->txst[ep_num].curdeqlo);
 155                 }
 156
 157                 status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT;
 158                 length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK;
 159
 160                 if (status == MV_U3D_COMPLETE_SUCCESS ||
 161                         (status == MV_U3D_COMPLETE_SHORT_PACKET &&
 162                         direction == MV_U3D_EP_DIR_OUT)) {
 163                         remaining_length += length;
 164                         actual -= remaining_length;
 165                 } else {
 166                         dev_err(u3d->dev,
 167                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 168                                 index >> 1, direction ? "SEND" : "RECV",
 169                                 status);
 170                         retval = -EPROTO;
 171                 }
 172
 173                 list_del_init(&curr_trb->trb_list);
 174         }
 175         if (retval)
 176                 return retval;
 177
 178         curr_req->req.actual = actual;
 179         return 0;
 180 }
 181
 182 /*
 183  * mv_u3d_done() - retire a request; caller blocked irqs
 184  * @status : request status to be set, only works when
 185  * request is still in progress.
 186  */
 187 static
 188 void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status)
 189         __releases(&ep->udc->lock)
 190         __acquires(&ep->udc->lock)
 191 {
 192         struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d;
 193
 194         dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n");
 195         /* Removed the req from ep queue */
 196         list_del_init(&req->queue);
 197
 198         /* req.status should be set as -EINPROGRESS in ep_queue() */
 199         if (req->req.status == -EINPROGRESS)
 200                 req->req.status = status;
 201         else
 202                 status = req->req.status;
 203
 204         /* Free trb for the request */
 205         if (!req->chain)
 206                 dma_pool_free(u3d->trb_pool,
 207                         req->trb_head->trb_hw, req->trb_head->trb_dma);
 208         else {
 209                 dma_unmap_single(ep->u3d->gadget.dev.parent,
 210                         (dma_addr_t)req->trb_head->trb_dma,
 211                         req->trb_count * sizeof(struct mv_u3d_trb_hw),
 212                         DMA_BIDIRECTIONAL);
 213                 kfree(req->trb_head->trb_hw);
 214         }
 215         kfree(req->trb_head);
 216
 217         usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep));
 218
 219         if (status && (status != -ESHUTDOWN)) {
 220                 dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u",
 221                         ep->ep.name, &req->req, status,
 222                         req->req.actual, req->req.length);
 223         }
 224
 225         spin_unlock(&ep->u3d->lock);
 226         /*
 227          * complete() is from gadget layer,
 228          * eg fsg->bulk_in_complete()
 229          */
 230         if (req->req.complete)
 231                 req->req.complete(&ep->ep, &req->req);
 232
 233         spin_lock(&ep->u3d->lock);
 234 }
 235
 236 static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req)
 237 {
 238         u32 tmp, direction;
 239         struct mv_u3d *u3d;
 240         struct mv_u3d_ep_context *ep_context;
 241         int retval = 0;
 242
 243         u3d = ep->u3d;
 244         direction = mv_u3d_ep_dir(ep);
 245
 246         /* ep0 in and out share the same ep context slot 1*/
 247         if (ep->ep_num == 0)
 248                 ep_context = &(u3d->ep_context[1]);
 249         else
 250                 ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]);
 251
 252         /* check if the pipe is empty or not */
 253         if (!list_empty(&ep->queue)) {
 254                 dev_err(u3d->dev, "add trb to non-empty queue!\n");
 255                 retval = -ENOMEM;
 256                 WARN_ON(1);
 257         } else {
 258                 ep_context->rsvd0 = cpu_to_le32(1);
 259                 ep_context->rsvd1 = 0;
 260
 261                 /* Configure the trb address and set the DCS bit.
 262                  * Both DCS bit and own bit in trb should be set.
 263                  */
 264                 ep_context->trb_addr_lo =
 265                         cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE);
 266                 ep_context->trb_addr_hi = 0;
 267
 268                 /* Ensure that updates to the EP Context will
 269                  * occure before Ring Bell.
 270                  */
 271                 wmb();
 272
 273                 /* ring bell the ep */
 274                 if (ep->ep_num == 0)
 275                         tmp = 0x1;
 276                 else
 277                         tmp = ep->ep_num * 2
 278                                 + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1);
 279
 280                 iowrite32(tmp, &u3d->op_regs->doorbell);
 281         }
 282         return retval;
 283 }
 284
 285 static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req,
 286                                 unsigned *length, dma_addr_t *dma)
 287 {
 288         u32 temp;
 289         unsigned int direction;
 290         struct mv_u3d_trb *trb;
 291         struct mv_u3d_trb_hw *trb_hw;
 292         struct mv_u3d *u3d;
 293
 294         /* how big will this transfer be? */
 295         *length = req->req.length - req->req.actual;
 296         BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 297
 298         u3d = req->ep->u3d;
 299
 300         trb = kzalloc(sizeof(*trb), GFP_ATOMIC);
 301         if (!trb) {
 302                 dev_err(u3d->dev, "%s, trb alloc fail\n", __func__);
 303                 return NULL;
 304         }
 305
 306         /*
 307          * Be careful that no _GFP_HIGHMEM is set,
 308          * or we can not use dma_to_virt
 309          * cannot use GFP_KERNEL in spin lock
 310          */
 311         trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma);
 312         if (!trb_hw) {
 313                 kfree(trb);
 314                 dev_err(u3d->dev,
 315                         "%s, dma_pool_alloc fail\n", __func__);
 316                 return NULL;
 317         }
 318         trb->trb_dma = *dma;
 319         trb->trb_hw = trb_hw;
 320
 321         /* initialize buffer page pointers */
 322         temp = (u32)(req->req.dma + req->req.actual);
 323
 324         trb_hw->buf_addr_lo = cpu_to_le32(temp);
 325         trb_hw->buf_addr_hi = 0;
 326         trb_hw->trb_len = cpu_to_le32(*length);
 327         trb_hw->ctrl.own = 1;
 328
 329         if (req->ep->ep_num == 0)
 330                 trb_hw->ctrl.type = TYPE_DATA;
 331         else
 332                 trb_hw->ctrl.type = TYPE_NORMAL;
 333
 334         req->req.actual += *length;
 335
 336         direction = mv_u3d_ep_dir(req->ep);
 337         if (direction == MV_U3D_EP_DIR_IN)
 338                 trb_hw->ctrl.dir = 1;
 339         else
 340                 trb_hw->ctrl.dir = 0;
 341
 342         /* Enable interrupt for the last trb of a request */
 343         if (!req->req.no_interrupt)
 344                 trb_hw->ctrl.ioc = 1;
 345
 346         trb_hw->ctrl.chain = 0;
 347
 348         wmb();
 349         return trb;
 350 }
 351
 352 static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length,
 353                 struct mv_u3d_trb *trb, int *is_last)
 354 {
 355         u32 temp;
 356         unsigned int direction;
 357         struct mv_u3d *u3d;
 358
 359         /* how big will this transfer be? */
 360         *length = min(req->req.length - req->req.actual,
 361                         (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 362
 363         u3d = req->ep->u3d;
 364
 365         trb->trb_dma = 0;
 366
 367         /* initialize buffer page pointers */
 368         temp = (u32)(req->req.dma + req->req.actual);
 369
 370         trb->trb_hw->buf_addr_lo = cpu_to_le32(temp);
 371         trb->trb_hw->buf_addr_hi = 0;
 372         trb->trb_hw->trb_len = cpu_to_le32(*length);
 373         trb->trb_hw->ctrl.own = 1;
 374
 375         if (req->ep->ep_num == 0)
 376                 trb->trb_hw->ctrl.type = TYPE_DATA;
 377         else
 378                 trb->trb_hw->ctrl.type = TYPE_NORMAL;
 379
 380         req->req.actual += *length;
 381
 382         direction = mv_u3d_ep_dir(req->ep);
 383         if (direction == MV_U3D_EP_DIR_IN)
 384                 trb->trb_hw->ctrl.dir = 1;
 385         else
 386                 trb->trb_hw->ctrl.dir = 0;
 387
 388         /* zlp is needed if req->req.zero is set */
 389         if (req->req.zero) {
 390                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 391                         *is_last = 1;
 392                 else
 393                         *is_last = 0;
 394         } else if (req->req.length == req->req.actual)
 395                 *is_last = 1;
 396         else
 397                 *is_last = 0;
 398
 399         /* Enable interrupt for the last trb of a request */
 400         if (*is_last && !req->req.no_interrupt)
 401                 trb->trb_hw->ctrl.ioc = 1;
 402
 403         if (*is_last)
 404                 trb->trb_hw->ctrl.chain = 0;
 405         else {
 406                 trb->trb_hw->ctrl.chain = 1;
 407                 dev_dbg(u3d->dev, "chain trb\n");
 408         }
 409
 410         wmb();
 411
 412         return 0;
 413 }
 414
 415 /* generate TRB linked list for a request
 416  * usb controller only supports continous trb chain,
 417  * that trb structure physical address should be continous.
 418  */
 419 static int mv_u3d_req_to_trb(struct mv_u3d_req *req)
 420 {
 421         unsigned count;
 422         int is_last;
 423         struct mv_u3d_trb *trb;
 424         struct mv_u3d_trb_hw *trb_hw;
 425         struct mv_u3d *u3d;
 426         dma_addr_t dma;
 427         unsigned length;
 428         unsigned trb_num;
 429
 430         u3d = req->ep->u3d;
 431
 432         INIT_LIST_HEAD(&req->trb_list);
 433
 434         length = req->req.length - req->req.actual;
 435         /* normally the request transfer length is less than 16KB.
 436          * we use buil_trb_one() to optimize it.
 437          */
 438         if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) {
 439                 trb = mv_u3d_build_trb_one(req, &count, &dma);
 440                 list_add_tail(&trb->trb_list, &req->trb_list);
 441                 req->trb_head = trb;
 442                 req->trb_count = 1;
 443                 req->chain = 0;
 444         } else {
 445                 trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER;
 446                 if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER)
 447                         trb_num++;
 448
 449                 trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC);
 450                 if (!trb) {
 451                         dev_err(u3d->dev,
 452                                         "%s, trb alloc fail\n", __func__);
 453                         return -ENOMEM;
 454                 }
 455
 456                 trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC);
 457                 if (!trb_hw) {
 458                         kfree(trb);
 459                         dev_err(u3d->dev,
 460                                         "%s, trb_hw alloc fail\n", __func__);
 461                         return -ENOMEM;
 462                 }
 463
 464                 do {
 465                         trb->trb_hw = trb_hw;
 466                         if (mv_u3d_build_trb_chain(req, &count,
 467                                                 trb, &is_last)) {
 468                                 dev_err(u3d->dev,
 469                                         "%s, mv_u3d_build_trb_chain fail\n",
 470                                         __func__);
 471                                 return -EIO;
 472                         }
 473
 474                         list_add_tail(&trb->trb_list, &req->trb_list);
 475                         req->trb_count++;
 476                         trb++;
 477                         trb_hw++;
 478                 } while (!is_last);
 479
 480                 req->trb_head = list_entry(req->trb_list.next,
 481                                         struct mv_u3d_trb, trb_list);
 482                 req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent,
 483                                         req->trb_head->trb_hw,
 484                                         trb_num * sizeof(*trb_hw),
 485                                         DMA_BIDIRECTIONAL);
 486
 487                 req->chain = 1;
 488         }
 489
 490         return 0;
 491 }
 492
 493 static int
 494 mv_u3d_start_queue(struct mv_u3d_ep *ep)
 495 {
 496         struct mv_u3d *u3d = ep->u3d;
 497         struct mv_u3d_req *req;
 498         int ret;
 499
 500         if (!list_empty(&ep->req_list) && !ep->processing)
 501                 req = list_entry(ep->req_list.next, struct mv_u3d_req, list);
 502         else
 503                 return 0;
 504
 505         ep->processing = 1;
 506
 507         /* set up dma mapping */
 508         ret = usb_gadget_map_request(&u3d->gadget, &req->req,
 509                                         mv_u3d_ep_dir(ep));
 510         if (ret)
 511                 return ret;
 512
 513         req->req.status = -EINPROGRESS;
 514         req->req.actual = 0;
 515         req->trb_count = 0;
 516
 517         /* build trbs and push them to device queue */
 518         if (!mv_u3d_req_to_trb(req)) {
 519                 ret = mv_u3d_queue_trb(ep, req);
 520                 if (ret) {
 521                         ep->processing = 0;
 522                         return ret;
 523                 }
 524         } else {
 525                 ep->processing = 0;
 526                 dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__);
 527                 return -ENOMEM;
 528         }
 529
 530         /* irq handler advances the queue */
 531         if (req)
 532                 list_add_tail(&req->queue, &ep->queue);
 533
 534         return 0;
 535 }
 536
 537 static int mv_u3d_ep_enable(struct usb_ep *_ep,
 538                 const struct usb_endpoint_descriptor *desc)
 539 {
 540         struct mv_u3d *u3d;
 541         struct mv_u3d_ep *ep;
 542         struct mv_u3d_ep_context *ep_context;
 543         u16 max = 0;
 544         unsigned maxburst = 0;
 545         u32 epxcr, direction;
 546
 547         if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT)
 548                 return -EINVAL;
 549
 550         ep = container_of(_ep, struct mv_u3d_ep, ep);
 551         u3d = ep->u3d;
 552
 553         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN)
 554                 return -ESHUTDOWN;
 555
 556         direction = mv_u3d_ep_dir(ep);
 557         max = le16_to_cpu(desc->wMaxPacketSize);
 558
 559         if (!_ep->maxburst)
 560                 _ep->maxburst = 1;
 561         maxburst = _ep->maxburst;
 562
 563         /* Get the endpoint context address */
 564         ep_context = (struct mv_u3d_ep_context *)ep->ep_context;
 565
 566         /* Set the max burst size */
 567         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 568         case USB_ENDPOINT_XFER_BULK:
 569                 if (maxburst > 16) {
 570                         dev_dbg(u3d->dev,
 571                                 "max burst should not be greater "
 572                                 "than 16 on bulk ep\n");
 573                         maxburst = 1;
 574                         _ep->maxburst = maxburst;
 575                 }
 576                 dev_dbg(u3d->dev,
 577                         "maxburst: %d on bulk %s\n", maxburst, ep->name);
 578                 break;
 579         case USB_ENDPOINT_XFER_CONTROL:
 580                 /* control transfer only supports maxburst as one */
 581                 maxburst = 1;
 582                 _ep->maxburst = maxburst;
 583                 break;
 584         case USB_ENDPOINT_XFER_INT:
 585                 if (maxburst != 1) {
 586                         dev_dbg(u3d->dev,
 587                                 "max burst should be 1 on int ep "
 588                                 "if transfer size is not 1024\n");
 589                         maxburst = 1;
 590                         _ep->maxburst = maxburst;
 591                 }
 592                 break;
 593         case USB_ENDPOINT_XFER_ISOC:
 594                 if (maxburst != 1) {
 595                         dev_dbg(u3d->dev,
 596                                 "max burst should be 1 on isoc ep "
 597                                 "if transfer size is not 1024\n");
 598                         maxburst = 1;
 599                         _ep->maxburst = maxburst;
 600                 }
 601                 break;
 602         default:
 603                 goto en_done;
 604         }
 605
 606         ep->ep.maxpacket = max;
 607         ep->ep.desc = desc;
 608         ep->enabled = 1;
 609
 610         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 611         if (direction == MV_U3D_EP_DIR_OUT) {
 612                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 613                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 614                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 615                 udelay(5);
 616                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 617                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 618
 619                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 620                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 621                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 622                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 623                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 624         } else {
 625                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 626                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 627                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 628                 udelay(5);
 629                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 630                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 631
 632                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 633                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 634                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 635                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 636                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 637         }
 638
 639         return 0;
 640 en_done:
 641         return -EINVAL;
 642 }
 643
 644 static int  mv_u3d_ep_disable(struct usb_ep *_ep)
 645 {
 646         struct mv_u3d *u3d;
 647         struct mv_u3d_ep *ep;
 648         struct mv_u3d_ep_context *ep_context;
 649         u32 epxcr, direction;
 650         unsigned long flags;
 651
 652         if (!_ep)
 653                 return -EINVAL;
 654
 655         ep = container_of(_ep, struct mv_u3d_ep, ep);
 656         if (!ep->ep.desc)
 657                 return -EINVAL;
 658
 659         u3d = ep->u3d;
 660
 661         /* Get the endpoint context address */
 662         ep_context = ep->ep_context;
 663
 664         direction = mv_u3d_ep_dir(ep);
 665
 666         /* nuke all pending requests (does flush) */
 667         spin_lock_irqsave(&u3d->lock, flags);
 668         mv_u3d_nuke(ep, -ESHUTDOWN);
 669         spin_unlock_irqrestore(&u3d->lock, flags);
 670
 671         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 672         if (direction == MV_U3D_EP_DIR_OUT) {
 673                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 674                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 675                       | USB_ENDPOINT_XFERTYPE_MASK);
 676                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 677         } else {
 678                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 679                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 680                       | USB_ENDPOINT_XFERTYPE_MASK);
 681                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 682         }
 683
 684         ep->enabled = 0;
 685
 686         ep->ep.desc = NULL;
 687         return 0;
 688 }
 689
 690 static struct usb_request *
 691 mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 692 {
 693         struct mv_u3d_req *req = NULL;
 694
 695         req = kzalloc(sizeof *req, gfp_flags);
 696         if (!req)
 697                 return NULL;
 698
 699         INIT_LIST_HEAD(&req->queue);
 700
 701         return &req->req;
 702 }
 703
 704 static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req)
 705 {
 706         struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req);
 707
 708         kfree(req);
 709 }
 710
 711 static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep)
 712 {
 713         struct mv_u3d *u3d;
 714         u32 direction;
 715         struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep);
 716         unsigned int loops;
 717         u32 tmp;
 718
 719         /* if endpoint is not enabled, cannot flush endpoint */
 720         if (!ep->enabled)
 721                 return;
 722
 723         u3d = ep->u3d;
 724         direction = mv_u3d_ep_dir(ep);
 725
 726         /* ep0 need clear bit after flushing fifo. */
 727         if (!ep->ep_num) {
 728                 if (direction == MV_U3D_EP_DIR_OUT) {
 729                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 730                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 731                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 732                         udelay(10);
 733                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 734                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 735                 } else {
 736                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 737                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 738                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 739                         udelay(10);
 740                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 741                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 742                 }
 743                 return;
 744         }
 745
 746         if (direction == MV_U3D_EP_DIR_OUT) {
 747                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 748                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 749                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 750
 751                 /* Wait until flushing completed */
 752                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 753                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) &
 754                         MV_U3D_EPXCR_EP_FLUSH) {
 755                         /*
 756                          * EP_FLUSH bit should be cleared to indicate this
 757                          * operation is complete
 758                          */
 759                         if (loops == 0) {
 760                                 dev_dbg(u3d->dev,
 761                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 762                                     direction ? "in" : "out");
 763                                 return;
 764                         }
 765                         loops--;
 766                         udelay(LOOPS_USEC);
 767                 }
 768         } else {        /* EP_DIR_IN */
 769                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 770                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 771                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 772
 773                 /* Wait until flushing completed */
 774                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 775                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) &
 776                         MV_U3D_EPXCR_EP_FLUSH) {
 777                         /*
 778                         * EP_FLUSH bit should be cleared to indicate this
 779                         * operation is complete
 780                         */
 781                         if (loops == 0) {
 782                                 dev_dbg(u3d->dev,
 783                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 784                                     direction ? "in" : "out");
 785                                 return;
 786                         }
 787                         loops--;
 788                         udelay(LOOPS_USEC);
 789                 }
 790         }
 791 }
 792
 793 /* queues (submits) an I/O request to an endpoint */
 794 static int
 795 mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 796 {
 797         struct mv_u3d_ep *ep;
 798         struct mv_u3d_req *req;
 799         struct mv_u3d *u3d;
 800         unsigned long flags;
 801         int is_first_req = 0;
 802
 803         if (unlikely(!_ep || !_req))
 804                 return -EINVAL;
 805
 806         ep = container_of(_ep, struct mv_u3d_ep, ep);
 807         u3d = ep->u3d;
 808
 809         req = container_of(_req, struct mv_u3d_req, req);
 810
 811         if (!ep->ep_num
 812                 && u3d->ep0_state == MV_U3D_STATUS_STAGE
 813                 && !_req->length) {
 814                 dev_dbg(u3d->dev, "ep0 status stage\n");
 815                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 816                 return 0;
 817         }
 818
 819         dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n",
 820                         __func__, _ep->name, req);
 821
 822         /* catch various bogus parameters */
 823         if (!req->req.complete || !req->req.buf
 824                         || !list_empty(&req->queue)) {
 825                 dev_err(u3d->dev,
 826                         "%s, bad params, _req: 0x%p,"
 827                         "req->req.complete: 0x%p, req->req.buf: 0x%p,"
 828                         "list_empty: 0x%x\n",
 829                         __func__, _req,
 830                         req->req.complete, req->req.buf,
 831                         list_empty(&req->queue));
 832                 return -EINVAL;
 833         }
 834         if (unlikely(!ep->ep.desc)) {
 835                 dev_err(u3d->dev, "%s, bad ep\n", __func__);
 836                 return -EINVAL;
 837         }
 838         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 839                 if (req->req.length > ep->ep.maxpacket)
 840                         return -EMSGSIZE;
 841         }
 842
 843         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) {
 844                 dev_err(u3d->dev,
 845                         "bad params of driver/speed\n");
 846                 return -ESHUTDOWN;
 847         }
 848
 849         req->ep = ep;
 850
 851         /* Software list handles usb request. */
 852         spin_lock_irqsave(&ep->req_lock, flags);
 853         is_first_req = list_empty(&ep->req_list);
 854         list_add_tail(&req->list, &ep->req_list);
 855         spin_unlock_irqrestore(&ep->req_lock, flags);
 856         if (!is_first_req) {
 857                 dev_dbg(u3d->dev, "list is not empty\n");
 858                 return 0;
 859         }
 860
 861         dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n");
 862         spin_lock_irqsave(&u3d->lock, flags);
 863         mv_u3d_start_queue(ep);
 864         spin_unlock_irqrestore(&u3d->lock, flags);
 865         return 0;
 866 }
 867
 868 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 869 static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 870 {
 871         struct mv_u3d_ep *ep;
 872         struct mv_u3d_req *req;
 873         struct mv_u3d *u3d;
 874         struct mv_u3d_ep_context *ep_context;
 875         struct mv_u3d_req *next_req;
 876
 877         unsigned long flags;
 878         int ret = 0;
 879
 880         if (!_ep || !_req)
 881                 return -EINVAL;
 882
 883         ep = container_of(_ep, struct mv_u3d_ep, ep);
 884         u3d = ep->u3d;
 885
 886         spin_lock_irqsave(&ep->u3d->lock, flags);
 887
 888         /* make sure it's actually queued on this endpoint */
 889         list_for_each_entry(req, &ep->queue, queue) {
 890                 if (&req->req == _req)
 891                         break;
 892         }
 893         if (&req->req != _req) {
 894                 ret = -EINVAL;
 895                 goto out;
 896         }
 897
 898         /* The request is in progress, or completed but not dequeued */
 899         if (ep->queue.next == &req->queue) {
 900                 _req->status = -ECONNRESET;
 901                 mv_u3d_ep_fifo_flush(_ep);
 902
 903                 /* The request isn't the last request in this ep queue */
 904                 if (req->queue.next != &ep->queue) {
 905                         dev_dbg(u3d->dev,
 906                                 "it is the last request in this ep queue\n");
 907                         ep_context = ep->ep_context;
 908                         next_req = list_entry(req->queue.next,
 909                                         struct mv_u3d_req, queue);
 910
 911                         /* Point first TRB of next request to the EP context. */
 912                         iowrite32((unsigned long) next_req->trb_head,
 913                                         &ep_context->trb_addr_lo);
 914                 } else {
 915                         struct mv_u3d_ep_context *ep_context;
 916                         ep_context = ep->ep_context;
 917                         ep_context->trb_addr_lo = 0;
 918                         ep_context->trb_addr_hi = 0;
 919                 }
 920
 921         } else
 922                 WARN_ON(1);
 923
 924         mv_u3d_done(ep, req, -ECONNRESET);
 925
 926         /* remove the req from the ep req list */
 927         if (!list_empty(&ep->req_list)) {
 928                 struct mv_u3d_req *curr_req;
 929                 curr_req = list_entry(ep->req_list.next,
 930                                         struct mv_u3d_req, list);
 931                 if (curr_req == req) {
 932                         list_del_init(&req->list);
 933                         ep->processing = 0;
 934                 }
 935         }
 936
 937 out:
 938         spin_unlock_irqrestore(&ep->u3d->lock, flags);
 939         return ret;
 940 }
 941
 942 static void
 943 mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall)
 944 {
 945         u32 tmp;
 946         struct mv_u3d_ep *ep = u3d->eps;
 947
 948         dev_dbg(u3d->dev, "%s\n", __func__);
 949         if (direction == MV_U3D_EP_DIR_OUT) {
 950                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 951                 if (stall)
 952                         tmp |= MV_U3D_EPXCR_EP_HALT;
 953                 else
 954                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 955                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 956         } else {
 957                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 958                 if (stall)
 959                         tmp |= MV_U3D_EPXCR_EP_HALT;
 960                 else
 961                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 962                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 963         }
 964 }
 965
 966 static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 967 {
 968         struct mv_u3d_ep *ep;
 969         unsigned long flags = 0;
 970         int status = 0;
 971         struct mv_u3d *u3d;
 972
 973         ep = container_of(_ep, struct mv_u3d_ep, ep);
 974         u3d = ep->u3d;
 975         if (!ep->ep.desc) {
 976                 status = -EINVAL;
 977                 goto out;
 978         }
 979
 980         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 981                 status = -EOPNOTSUPP;
 982                 goto out;
 983         }
 984
 985         /*
 986          * Attempt to halt IN ep will fail if any transfer requests
 987          * are still queue
 988          */
 989         if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN)
 990                         && !list_empty(&ep->queue)) {
 991                 status = -EAGAIN;
 992                 goto out;
 993         }
 994
 995         spin_lock_irqsave(&ep->u3d->lock, flags);
 996         mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt);
 997         if (halt && wedge)
 998                 ep->wedge = 1;
 999         else if (!halt)
1000                 ep->wedge = 0;
1001         spin_unlock_irqrestore(&ep->u3d->lock, flags);
1002
1003         if (ep->ep_num == 0)
1004                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1005 out:
1006         return status;
1007 }
1008
1009 static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt)
1010 {
1011         return mv_u3d_ep_set_halt_wedge(_ep, halt, 0);
1012 }
1013
1014 static int mv_u3d_ep_set_wedge(struct usb_ep *_ep)
1015 {
1016         return mv_u3d_ep_set_halt_wedge(_ep, 1, 1);
1017 }
1018
1019 static struct usb_ep_ops mv_u3d_ep_ops = {
1020         .enable         = mv_u3d_ep_enable,
1021         .disable        = mv_u3d_ep_disable,
1022
1023         .alloc_request  = mv_u3d_alloc_request,
1024         .free_request   = mv_u3d_free_request,
1025
1026         .queue          = mv_u3d_ep_queue,
1027         .dequeue        = mv_u3d_ep_dequeue,
1028
1029         .set_wedge      = mv_u3d_ep_set_wedge,
1030         .set_halt       = mv_u3d_ep_set_halt,
1031         .fifo_flush     = mv_u3d_ep_fifo_flush,
1032 };
1033
1034 static void mv_u3d_controller_stop(struct mv_u3d *u3d)
1035 {
1036         u32 tmp;
1037
1038         if (!u3d->clock_gating && u3d->vbus_valid_detect)
1039                 iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID,
1040                                 &u3d->vuc_regs->intrenable);
1041         else
1042                 iowrite32(0, &u3d->vuc_regs->intrenable);
1043         iowrite32(~0x0, &u3d->vuc_regs->endcomplete);
1044         iowrite32(~0x0, &u3d->vuc_regs->trbunderrun);
1045         iowrite32(~0x0, &u3d->vuc_regs->trbcomplete);
1046         iowrite32(~0x0, &u3d->vuc_regs->linkchange);
1047         iowrite32(0x1, &u3d->vuc_regs->setuplock);
1048
1049         /* Reset the RUN bit in the command register to stop USB */
1050         tmp = ioread32(&u3d->op_regs->usbcmd);
1051         tmp &= ~MV_U3D_CMD_RUN_STOP;
1052         iowrite32(tmp, &u3d->op_regs->usbcmd);
1053         dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n",
1054                 ioread32(&u3d->op_regs->usbcmd));
1055 }
1056
1057 static void mv_u3d_controller_start(struct mv_u3d *u3d)
1058 {
1059         u32 usbintr;
1060         u32 temp;
1061
1062         /* enable link LTSSM state machine */
1063         temp = ioread32(&u3d->vuc_regs->ltssm);
1064         temp |= MV_U3D_LTSSM_PHY_INIT_DONE;
1065         iowrite32(temp, &u3d->vuc_regs->ltssm);
1066
1067         /* Enable interrupts */
1068         usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR |
1069                 MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE |
1070                 MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP |
1071                 (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0);
1072         iowrite32(usbintr, &u3d->vuc_regs->intrenable);
1073
1074         /* Enable ctrl ep */
1075         iowrite32(0x1, &u3d->vuc_regs->ctrlepenable);
1076
1077         /* Set the Run bit in the command register */
1078         iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd);
1079         dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n",
1080                 ioread32(&u3d->op_regs->usbcmd));
1081 }
1082
1083 static int mv_u3d_controller_reset(struct mv_u3d *u3d)
1084 {
1085         unsigned int loops;
1086         u32 tmp;
1087
1088         /* Stop the controller */
1089         tmp = ioread32(&u3d->op_regs->usbcmd);
1090         tmp &= ~MV_U3D_CMD_RUN_STOP;
1091         iowrite32(tmp, &u3d->op_regs->usbcmd);
1092
1093         /* Reset the controller to get default values */
1094         iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd);
1095
1096         /* wait for reset to complete */
1097         loops = LOOPS(MV_U3D_RESET_TIMEOUT);
1098         while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) {
1099                 if (loops == 0) {
1100                         dev_err(u3d->dev,
1101                                 "Wait for RESET completed TIMEOUT\n");
1102                         return -ETIMEDOUT;
1103                 }
1104                 loops--;
1105                 udelay(LOOPS_USEC);
1106         }
1107
1108         /* Configure the Endpoint Context Address */
1109         iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl);
1110         iowrite32(0, &u3d->op_regs->dcbaaph);
1111
1112         return 0;
1113 }
1114
1115 static int mv_u3d_enable(struct mv_u3d *u3d)
1116 {
1117         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1118         int retval;
1119
1120         if (u3d->active)
1121                 return 0;
1122
1123         if (!u3d->clock_gating) {
1124                 u3d->active = 1;
1125                 return 0;
1126         }
1127
1128         dev_dbg(u3d->dev, "enable u3d\n");
1129         clk_enable(u3d->clk);
1130         if (pdata->phy_init) {
1131                 retval = pdata->phy_init(u3d->phy_regs);
1132                 if (retval) {
1133                         dev_err(u3d->dev,
1134                                 "init phy error %d\n", retval);
1135                         clk_disable(u3d->clk);
1136                         return retval;
1137                 }
1138         }
1139         u3d->active = 1;
1140
1141         return 0;
1142 }
1143
1144 static void mv_u3d_disable(struct mv_u3d *u3d)
1145 {
1146         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1147         if (u3d->clock_gating && u3d->active) {
1148                 dev_dbg(u3d->dev, "disable u3d\n");
1149                 if (pdata->phy_deinit)
1150                         pdata->phy_deinit(u3d->phy_regs);
1151                 clk_disable(u3d->clk);
1152                 u3d->active = 0;
1153         }
1154 }
1155
1156 static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active)
1157 {
1158         struct mv_u3d *u3d;
1159         unsigned long flags;
1160         int retval = 0;
1161
1162         u3d = container_of(gadget, struct mv_u3d, gadget);
1163
1164         spin_lock_irqsave(&u3d->lock, flags);
1165
1166         u3d->vbus_active = (is_active != 0);
1167         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1168                 __func__, u3d->softconnect, u3d->vbus_active);
1169         /*
1170          * 1. external VBUS detect: we can disable/enable clock on demand.
1171          * 2. UDC VBUS detect: we have to enable clock all the time.
1172          * 3. No VBUS detect: we have to enable clock all the time.
1173          */
1174         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1175                 retval = mv_u3d_enable(u3d);
1176                 if (retval == 0) {
1177                         /*
1178                          * after clock is disabled, we lost all the register
1179                          *  context. We have to re-init registers
1180                          */
1181                         mv_u3d_controller_reset(u3d);
1182                         mv_u3d_ep0_reset(u3d);
1183                         mv_u3d_controller_start(u3d);
1184                 }
1185         } else if (u3d->driver && u3d->softconnect) {
1186                 if (!u3d->active)
1187                         goto out;
1188
1189                 /* stop all the transfer in queue*/
1190                 mv_u3d_stop_activity(u3d, u3d->driver);
1191                 mv_u3d_controller_stop(u3d);
1192                 mv_u3d_disable(u3d);
1193         }
1194
1195 out:
1196         spin_unlock_irqrestore(&u3d->lock, flags);
1197         return retval;
1198 }
1199
1200 /* constrain controller's VBUS power usage
1201  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1202  * reporting how much power the device may consume.  For example, this
1203  * could affect how quickly batteries are recharged.
1204  *
1205  * Returns zero on success, else negative errno.
1206  */
1207 static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1208 {
1209         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1210
1211         u3d->power = mA;
1212
1213         return 0;
1214 }
1215
1216 static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on)
1217 {
1218         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1219         unsigned long flags;
1220         int retval = 0;
1221
1222         spin_lock_irqsave(&u3d->lock, flags);
1223
1224         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1225                 __func__, u3d->softconnect, u3d->vbus_active);
1226         u3d->softconnect = (is_on != 0);
1227         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1228                 retval = mv_u3d_enable(u3d);
1229                 if (retval == 0) {
1230                         /*
1231                          * after clock is disabled, we lost all the register
1232                          *  context. We have to re-init registers
1233                          */
1234                         mv_u3d_controller_reset(u3d);
1235                         mv_u3d_ep0_reset(u3d);
1236                         mv_u3d_controller_start(u3d);
1237                 }
1238         } else if (u3d->driver && u3d->vbus_active) {
1239                 /* stop all the transfer in queue*/
1240                 mv_u3d_stop_activity(u3d, u3d->driver);
1241                 mv_u3d_controller_stop(u3d);
1242                 mv_u3d_disable(u3d);
1243         }
1244
1245         spin_unlock_irqrestore(&u3d->lock, flags);
1246
1247         return retval;
1248 }
1249
1250 static int mv_u3d_start(struct usb_gadget *g,
1251                 struct usb_gadget_driver *driver)
1252 {
1253         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1254         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1255         unsigned long flags;
1256
1257         if (u3d->driver)
1258                 return -EBUSY;
1259
1260         spin_lock_irqsave(&u3d->lock, flags);
1261
1262         if (!u3d->clock_gating) {
1263                 clk_enable(u3d->clk);
1264                 if (pdata->phy_init)
1265                         pdata->phy_init(u3d->phy_regs);
1266         }
1267
1268         /* hook up the driver ... */
1269         driver->driver.bus = NULL;
1270         u3d->driver = driver;
1271
1272         u3d->ep0_dir = USB_DIR_OUT;
1273
1274         spin_unlock_irqrestore(&u3d->lock, flags);
1275
1276         u3d->vbus_valid_detect = 1;
1277
1278         return 0;
1279 }
1280
1281 static int mv_u3d_stop(struct usb_gadget *g,
1282                 struct usb_gadget_driver *driver)
1283 {
1284         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1285         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1286         unsigned long flags;
1287
1288         u3d->vbus_valid_detect = 0;
1289         spin_lock_irqsave(&u3d->lock, flags);
1290
1291         /* enable clock to access controller register */
1292         clk_enable(u3d->clk);
1293         if (pdata->phy_init)
1294                 pdata->phy_init(u3d->phy_regs);
1295
1296         mv_u3d_controller_stop(u3d);
1297         /* stop all usb activities */
1298         u3d->gadget.speed = USB_SPEED_UNKNOWN;
1299         mv_u3d_stop_activity(u3d, driver);
1300         mv_u3d_disable(u3d);
1301
1302         if (pdata->phy_deinit)
1303                 pdata->phy_deinit(u3d->phy_regs);
1304         clk_disable(u3d->clk);
1305
1306         spin_unlock_irqrestore(&u3d->lock, flags);
1307
1308         u3d->driver = NULL;
1309
1310         return 0;
1311 }
1312
1313 /* device controller usb_gadget_ops structure */
1314 static const struct usb_gadget_ops mv_u3d_ops = {
1315         /* notify controller that VBUS is powered or not */
1316         .vbus_session   = mv_u3d_vbus_session,
1317
1318         /* constrain controller's VBUS power usage */
1319         .vbus_draw      = mv_u3d_vbus_draw,
1320
1321         .pullup         = mv_u3d_pullup,
1322         .udc_start      = mv_u3d_start,
1323         .udc_stop       = mv_u3d_stop,
1324 };
1325
1326 static int mv_u3d_eps_init(struct mv_u3d *u3d)
1327 {
1328         struct mv_u3d_ep        *ep;
1329         char name[14];
1330         int i;
1331
1332         /* initialize ep0, ep0 in/out use eps[1] */
1333         ep = &u3d->eps[1];
1334         ep->u3d = u3d;
1335         strncpy(ep->name, "ep0", sizeof(ep->name));
1336         ep->ep.name = ep->name;
1337         ep->ep.ops = &mv_u3d_ep_ops;
1338         ep->wedge = 0;
1339         ep->ep.maxpacket = MV_U3D_EP0_MAX_PKT_SIZE;
1340         ep->ep_num = 0;
1341         ep->ep.desc = &mv_u3d_ep0_desc;
1342         INIT_LIST_HEAD(&ep->queue);
1343         INIT_LIST_HEAD(&ep->req_list);
1344         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1345
1346         /* add ep0 ep_context */
1347         ep->ep_context = &u3d->ep_context[1];
1348
1349         /* initialize other endpoints */
1350         for (i = 2; i < u3d->max_eps * 2; i++) {
1351                 ep = &u3d->eps[i];
1352                 if (i & 1) {
1353                         snprintf(name, sizeof(name), "ep%din", i >> 1);
1354                         ep->direction = MV_U3D_EP_DIR_IN;
1355                 } else {
1356                         snprintf(name, sizeof(name), "ep%dout", i >> 1);
1357                         ep->direction = MV_U3D_EP_DIR_OUT;
1358                 }
1359                 ep->u3d = u3d;
1360                 strncpy(ep->name, name, sizeof(ep->name));
1361                 ep->ep.name = ep->name;
1362
1363                 ep->ep.ops = &mv_u3d_ep_ops;
1364                 ep->ep.maxpacket = (unsigned short) ~0;
1365                 ep->ep_num = i / 2;
1366
1367                 INIT_LIST_HEAD(&ep->queue);
1368                 list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list);
1369
1370                 INIT_LIST_HEAD(&ep->req_list);
1371                 spin_lock_init(&ep->req_lock);
1372                 ep->ep_context = &u3d->ep_context[i];
1373         }
1374
1375         return 0;
1376 }
1377
1378 /* delete all endpoint requests, called with spinlock held */
1379 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status)
1380 {
1381         /* endpoint fifo flush */
1382         mv_u3d_ep_fifo_flush(&ep->ep);
1383
1384         while (!list_empty(&ep->queue)) {
1385                 struct mv_u3d_req *req = NULL;
1386                 req = list_entry(ep->queue.next, struct mv_u3d_req, queue);
1387                 mv_u3d_done(ep, req, status);
1388         }
1389 }
1390
1391 /* stop all USB activities */
1392 static
1393 void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver)
1394 {
1395         struct mv_u3d_ep        *ep;
1396
1397         mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN);
1398
1399         list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) {
1400                 mv_u3d_nuke(ep, -ESHUTDOWN);
1401         }
1402
1403         /* report disconnect; the driver is already quiesced */
1404         if (driver) {
1405                 spin_unlock(&u3d->lock);
1406                 driver->disconnect(&u3d->gadget);
1407                 spin_lock(&u3d->lock);
1408         }
1409 }
1410
1411 static void mv_u3d_irq_process_error(struct mv_u3d *u3d)
1412 {
1413         /* Increment the error count */
1414         u3d->errors++;
1415         dev_err(u3d->dev, "%s\n", __func__);
1416 }
1417
1418 static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d)
1419 {
1420         u32 linkchange;
1421
1422         linkchange = ioread32(&u3d->vuc_regs->linkchange);
1423         iowrite32(linkchange, &u3d->vuc_regs->linkchange);
1424
1425         dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange);
1426
1427         if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) {
1428                 dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n",
1429                         ioread32(&u3d->vuc_regs->ltssmstate));
1430
1431                 u3d->usb_state = USB_STATE_DEFAULT;
1432                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1433                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
1434
1435                 /* set speed */
1436                 u3d->gadget.speed = USB_SPEED_SUPER;
1437         }
1438
1439         if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) {
1440                 dev_dbg(u3d->dev, "link suspend\n");
1441                 u3d->resume_state = u3d->usb_state;
1442                 u3d->usb_state = USB_STATE_SUSPENDED;
1443         }
1444
1445         if (linkchange & MV_U3D_LINK_CHANGE_RESUME) {
1446                 dev_dbg(u3d->dev, "link resume\n");
1447                 u3d->usb_state = u3d->resume_state;
1448                 u3d->resume_state = 0;
1449         }
1450
1451         if (linkchange & MV_U3D_LINK_CHANGE_WRESET) {
1452                 dev_dbg(u3d->dev, "warm reset\n");
1453                 u3d->usb_state = USB_STATE_POWERED;
1454         }
1455
1456         if (linkchange & MV_U3D_LINK_CHANGE_HRESET) {
1457                 dev_dbg(u3d->dev, "hot reset\n");
1458                 u3d->usb_state = USB_STATE_DEFAULT;
1459         }
1460
1461         if (linkchange & MV_U3D_LINK_CHANGE_INACT)
1462                 dev_dbg(u3d->dev, "inactive\n");
1463
1464         if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0)
1465                 dev_dbg(u3d->dev, "ss.disabled\n");
1466
1467         if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) {
1468                 dev_dbg(u3d->dev, "vbus invalid\n");
1469                 u3d->usb_state = USB_STATE_ATTACHED;
1470                 u3d->vbus_valid_detect = 1;
1471                 /* if external vbus detect is not supported,
1472                  * we handle it here.
1473                  */
1474                 if (!u3d->vbus) {
1475                         spin_unlock(&u3d->lock);
1476                         mv_u3d_vbus_session(&u3d->gadget, 0);
1477                         spin_lock(&u3d->lock);
1478                 }
1479         }
1480 }
1481
1482 static void mv_u3d_ch9setaddress(struct mv_u3d *u3d,
1483                                 struct usb_ctrlrequest *setup)
1484 {
1485         u32 tmp;
1486
1487         if (u3d->usb_state != USB_STATE_DEFAULT) {
1488                 dev_err(u3d->dev,
1489                         "%s, cannot setaddr in this state (%d)\n",
1490                         __func__, u3d->usb_state);
1491                 goto err;
1492         }
1493
1494         u3d->dev_addr = (u8)setup->wValue;
1495
1496         dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr);
1497
1498         if (u3d->dev_addr > 127) {
1499                 dev_err(u3d->dev,
1500                         "%s, u3d address is wrong (out of range)\n", __func__);
1501                 u3d->dev_addr = 0;
1502                 goto err;
1503         }
1504
1505         /* update usb state */
1506         u3d->usb_state = USB_STATE_ADDRESS;
1507
1508         /* set the new address */
1509         tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr);
1510         tmp &= ~0x7F;
1511         tmp |= (u32)u3d->dev_addr;
1512         iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr);
1513
1514         return;
1515 err:
1516         mv_u3d_ep0_stall(u3d);
1517 }
1518
1519 static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup)
1520 {
1521         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1522                 if (setup->bRequest == USB_REQ_SET_CONFIGURATION)
1523                         return 1;
1524
1525         return 0;
1526 }
1527
1528 static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num,
1529         struct usb_ctrlrequest *setup)
1530         __releases(&u3c->lock)
1531         __acquires(&u3c->lock)
1532 {
1533         bool delegate = false;
1534
1535         mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN);
1536
1537         dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1538                         setup->bRequestType, setup->bRequest,
1539                         setup->wValue, setup->wIndex, setup->wLength);
1540
1541         /* We process some stardard setup requests here */
1542         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1543                 switch (setup->bRequest) {
1544                 case USB_REQ_GET_STATUS:
1545                         delegate = true;
1546                         break;
1547
1548                 case USB_REQ_SET_ADDRESS:
1549                         mv_u3d_ch9setaddress(u3d, setup);
1550                         break;
1551
1552                 case USB_REQ_CLEAR_FEATURE:
1553                         delegate = true;
1554                         break;
1555
1556                 case USB_REQ_SET_FEATURE:
1557                         delegate = true;
1558                         break;
1559
1560                 default:
1561                         delegate = true;
1562                 }
1563         } else
1564                 delegate = true;
1565
1566         /* delegate USB standard requests to the gadget driver */
1567         if (delegate == true) {
1568                 /* USB requests handled by gadget */
1569                 if (setup->wLength) {
1570                         /* DATA phase from gadget, STATUS phase from u3d */
1571                         u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1572                                         ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT;
1573                         spin_unlock(&u3d->lock);
1574                         if (u3d->driver->setup(&u3d->gadget,
1575                                 &u3d->local_setup_buff) < 0) {
1576                                 dev_err(u3d->dev, "setup error!\n");
1577                                 mv_u3d_ep0_stall(u3d);
1578                         }
1579                         spin_lock(&u3d->lock);
1580                 } else {
1581                         /* no DATA phase, STATUS phase from gadget */
1582                         u3d->ep0_dir = MV_U3D_EP_DIR_IN;
1583                         u3d->ep0_state = MV_U3D_STATUS_STAGE;
1584                         spin_unlock(&u3d->lock);
1585                         if (u3d->driver->setup(&u3d->gadget,
1586                                 &u3d->local_setup_buff) < 0)
1587                                 mv_u3d_ep0_stall(u3d);
1588                         spin_lock(&u3d->lock);
1589                 }
1590
1591                 if (mv_u3d_is_set_configuration(setup)) {
1592                         dev_dbg(u3d->dev, "u3d configured\n");
1593                         u3d->usb_state = USB_STATE_CONFIGURED;
1594                 }
1595         }
1596 }
1597
1598 static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr)
1599 {
1600         struct mv_u3d_ep_context *epcontext;
1601
1602         epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN];
1603
1604         /* Copy the setup packet to local buffer */
1605         memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8);
1606 }
1607
1608 static void mv_u3d_irq_process_setup(struct mv_u3d *u3d)
1609 {
1610         u32 tmp, i;
1611         /* Process all Setup packet received interrupts */
1612         tmp = ioread32(&u3d->vuc_regs->setuplock);
1613         if (tmp) {
1614                 for (i = 0; i < u3d->max_eps; i++) {
1615                         if (tmp & (1 << i)) {
1616                                 mv_u3d_get_setup_data(u3d, i,
1617                                         (u8 *)(&u3d->local_setup_buff));
1618                                 mv_u3d_handle_setup_packet(u3d, i,
1619                                         &u3d->local_setup_buff);
1620                         }
1621                 }
1622         }
1623
1624         iowrite32(tmp, &u3d->vuc_regs->setuplock);
1625 }
1626
1627 static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d)
1628 {
1629         u32 tmp, bit_pos;
1630         int i, ep_num = 0, direction = 0;
1631         struct mv_u3d_ep        *curr_ep;
1632         struct mv_u3d_req *curr_req, *temp_req;
1633         int status;
1634
1635         tmp = ioread32(&u3d->vuc_regs->endcomplete);
1636
1637         dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp);
1638         if (!tmp)
1639                 return;
1640         iowrite32(tmp, &u3d->vuc_regs->endcomplete);
1641
1642         for (i = 0; i < u3d->max_eps * 2; i++) {
1643                 ep_num = i >> 1;
1644                 direction = i % 2;
1645
1646                 bit_pos = 1 << (ep_num + 16 * direction);
1647
1648                 if (!(bit_pos & tmp))
1649                         continue;
1650
1651                 if (i == 0)
1652                         curr_ep = &u3d->eps[1];
1653                 else
1654                         curr_ep = &u3d->eps[i];
1655
1656                 /* remove req out of ep request list after completion */
1657                 dev_dbg(u3d->dev, "tr comp: check req_list\n");
1658                 spin_lock(&curr_ep->req_lock);
1659                 if (!list_empty(&curr_ep->req_list)) {
1660                         struct mv_u3d_req *req;
1661                         req = list_entry(curr_ep->req_list.next,
1662                                                 struct mv_u3d_req, list);
1663                         list_del_init(&req->list);
1664                         curr_ep->processing = 0;
1665                 }
1666                 spin_unlock(&curr_ep->req_lock);
1667
1668                 /* process the req queue until an uncomplete request */
1669                 list_for_each_entry_safe(curr_req, temp_req,
1670                         &curr_ep->queue, queue) {
1671                         status = mv_u3d_process_ep_req(u3d, i, curr_req);
1672                         if (status)
1673                                 break;
1674                         /* write back status to req */
1675                         curr_req->req.status = status;
1676
1677                         /* ep0 request completion */
1678                         if (ep_num == 0) {
1679                                 mv_u3d_done(curr_ep, curr_req, 0);
1680                                 break;
1681                         } else {
1682                                 mv_u3d_done(curr_ep, curr_req, status);
1683                         }
1684                 }
1685
1686                 dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n");
1687                 mv_u3d_start_queue(curr_ep);
1688         }
1689 }
1690
1691 static irqreturn_t mv_u3d_irq(int irq, void *dev)
1692 {
1693         struct mv_u3d *u3d = (struct mv_u3d *)dev;
1694         u32 status, intr;
1695         u32 bridgesetting;
1696         u32 trbunderrun;
1697
1698         spin_lock(&u3d->lock);
1699
1700         status = ioread32(&u3d->vuc_regs->intrcause);
1701         intr = ioread32(&u3d->vuc_regs->intrenable);
1702         status &= intr;
1703
1704         if (status == 0) {
1705                 spin_unlock(&u3d->lock);
1706                 dev_err(u3d->dev, "irq error!\n");
1707                 return IRQ_NONE;
1708         }
1709
1710         if (status & MV_U3D_USBINT_VBUS_VALID) {
1711                 bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting);
1712                 if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) {
1713                         /* write vbus valid bit of bridge setting to clear */
1714                         bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID;
1715                         iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting);
1716                         dev_dbg(u3d->dev, "vbus valid\n");
1717
1718                         u3d->usb_state = USB_STATE_POWERED;
1719                         u3d->vbus_valid_detect = 0;
1720                         /* if external vbus detect is not supported,
1721                          * we handle it here.
1722                          */
1723                         if (!u3d->vbus) {
1724                                 spin_unlock(&u3d->lock);
1725                                 mv_u3d_vbus_session(&u3d->gadget, 1);
1726                                 spin_lock(&u3d->lock);
1727                         }
1728                 } else
1729                         dev_err(u3d->dev, "vbus bit is not set\n");
1730         }
1731
1732         /* RX data is already in the 16KB FIFO.*/
1733         if (status & MV_U3D_USBINT_UNDER_RUN) {
1734                 trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun);
1735                 dev_err(u3d->dev, "under run, ep%d\n", trbunderrun);
1736                 iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun);
1737                 mv_u3d_irq_process_error(u3d);
1738         }
1739
1740         if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) {
1741                 /* write one to clear */
1742                 iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR
1743                         | MV_U3D_USBINT_TXDESC_ERR),
1744                         &u3d->vuc_regs->intrcause);
1745                 dev_err(u3d->dev, "desc err 0x%x\n", status);
1746                 mv_u3d_irq_process_error(u3d);
1747         }
1748
1749         if (status & MV_U3D_USBINT_LINK_CHG)
1750                 mv_u3d_irq_process_link_change(u3d);
1751
1752         if (status & MV_U3D_USBINT_TX_COMPLETE)
1753                 mv_u3d_irq_process_tr_complete(u3d);
1754
1755         if (status & MV_U3D_USBINT_RX_COMPLETE)
1756                 mv_u3d_irq_process_tr_complete(u3d);
1757
1758         if (status & MV_U3D_USBINT_SETUP)
1759                 mv_u3d_irq_process_setup(u3d);
1760
1761         spin_unlock(&u3d->lock);
1762         return IRQ_HANDLED;
1763 }
1764
1765 static int mv_u3d_remove(struct platform_device *dev)
1766 {
1767         struct mv_u3d *u3d = platform_get_drvdata(dev);
1768
1769         BUG_ON(u3d == NULL);
1770
1771         usb_del_gadget_udc(&u3d->gadget);
1772
1773         /* free memory allocated in probe */
1774         if (u3d->trb_pool)
1775                 dma_pool_destroy(u3d->trb_pool);
1776
1777         if (u3d->ep_context)
1778                 dma_free_coherent(&dev->dev, u3d->ep_context_size,
1779                         u3d->ep_context, u3d->ep_context_dma);
1780
1781         kfree(u3d->eps);
1782
1783         if (u3d->irq)
1784                 free_irq(u3d->irq, u3d);
1785
1786         if (u3d->cap_regs)
1787                 iounmap(u3d->cap_regs);
1788         u3d->cap_regs = NULL;
1789
1790         kfree(u3d->status_req);
1791
1792         clk_put(u3d->clk);
1793
1794         kfree(u3d);
1795
1796         return 0;
1797 }
1798
1799 static int mv_u3d_probe(struct platform_device *dev)
1800 {
1801         struct mv_u3d *u3d = NULL;
1802         struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev);
1803         int retval = 0;
1804         struct resource *r;
1805         size_t size;
1806
1807         if (!dev_get_platdata(&dev->dev)) {
1808                 dev_err(&dev->dev, "missing platform_data\n");
1809                 retval = -ENODEV;
1810                 goto err_pdata;
1811         }
1812
1813         u3d = kzalloc(sizeof(*u3d), GFP_KERNEL);
1814         if (!u3d) {
1815                 dev_err(&dev->dev, "failed to allocate memory for u3d\n");
1816                 retval = -ENOMEM;
1817                 goto err_alloc_private;
1818         }
1819
1820         spin_lock_init(&u3d->lock);
1821
1822         platform_set_drvdata(dev, u3d);
1823
1824         u3d->dev = &dev->dev;
1825         u3d->vbus = pdata->vbus;
1826
1827         u3d->clk = clk_get(&dev->dev, NULL);
1828         if (IS_ERR(u3d->clk)) {
1829                 retval = PTR_ERR(u3d->clk);
1830                 goto err_get_clk;
1831         }
1832
1833         r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs");
1834         if (!r) {
1835                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1836                 retval = -ENODEV;
1837                 goto err_get_cap_regs;
1838         }
1839
1840         u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *)
1841                 ioremap(r->start, resource_size(r));
1842         if (!u3d->cap_regs) {
1843                 dev_err(&dev->dev, "failed to map I/O memory\n");
1844                 retval = -EBUSY;
1845                 goto err_map_cap_regs;
1846         } else {
1847                 dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n",
1848                         (unsigned long) r->start,
1849                         (unsigned long) u3d->cap_regs);
1850         }
1851
1852         /* we will access controller register, so enable the u3d controller */
1853         clk_enable(u3d->clk);
1854
1855         if (pdata->phy_init) {
1856                 retval = pdata->phy_init(u3d->phy_regs);
1857                 if (retval) {
1858                         dev_err(&dev->dev, "init phy error %d\n", retval);
1859                         goto err_u3d_enable;
1860                 }
1861         }
1862
1863         u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs
1864                 + MV_U3D_USB3_OP_REGS_OFFSET);
1865
1866         u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs
1867                 + ioread32(&u3d->cap_regs->vuoff));
1868
1869         u3d->max_eps = 16;
1870
1871         /*
1872          * some platform will use usb to download image, it may not disconnect
1873          * usb gadget before loading kernel. So first stop u3d here.
1874          */
1875         mv_u3d_controller_stop(u3d);
1876         iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause);
1877
1878         if (pdata->phy_deinit)
1879                 pdata->phy_deinit(u3d->phy_regs);
1880         clk_disable(u3d->clk);
1881
1882         size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2;
1883         size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1)
1884                 & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1);
1885         u3d->ep_context = dma_alloc_coherent(&dev->dev, size,
1886                                         &u3d->ep_context_dma, GFP_KERNEL);
1887         if (!u3d->ep_context) {
1888                 dev_err(&dev->dev, "allocate ep context memory failed\n");
1889                 retval = -ENOMEM;
1890                 goto err_alloc_ep_context;
1891         }
1892         u3d->ep_context_size = size;
1893
1894         /* create TRB dma_pool resource */
1895         u3d->trb_pool = dma_pool_create("u3d_trb",
1896                         &dev->dev,
1897                         sizeof(struct mv_u3d_trb_hw),
1898                         MV_U3D_TRB_ALIGNMENT,
1899                         MV_U3D_DMA_BOUNDARY);
1900
1901         if (!u3d->trb_pool) {
1902                 retval = -ENOMEM;
1903                 goto err_alloc_trb_pool;
1904         }
1905
1906         size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2;
1907         u3d->eps = kzalloc(size, GFP_KERNEL);
1908         if (!u3d->eps) {
1909                 dev_err(&dev->dev, "allocate ep memory failed\n");
1910                 retval = -ENOMEM;
1911                 goto err_alloc_eps;
1912         }
1913
1914         /* initialize ep0 status request structure */
1915         u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL);
1916         if (!u3d->status_req) {
1917                 dev_err(&dev->dev, "allocate status_req memory failed\n");
1918                 retval = -ENOMEM;
1919                 goto err_alloc_status_req;
1920         }
1921         INIT_LIST_HEAD(&u3d->status_req->queue);
1922
1923         /* allocate a small amount of memory to get valid address */
1924         u3d->status_req->req.buf = (char *)u3d->status_req
1925                                         + sizeof(struct mv_u3d_req);
1926         u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf);
1927
1928         u3d->resume_state = USB_STATE_NOTATTACHED;
1929         u3d->usb_state = USB_STATE_ATTACHED;
1930         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1931         u3d->remote_wakeup = 0;
1932
1933         r = platform_get_resource(dev, IORESOURCE_IRQ, 0);
1934         if (!r) {
1935                 dev_err(&dev->dev, "no IRQ resource defined\n");
1936                 retval = -ENODEV;
1937                 goto err_get_irq;
1938         }
1939         u3d->irq = r->start;
1940         if (request_irq(u3d->irq, mv_u3d_irq,
1941                 IRQF_SHARED, driver_name, u3d)) {
1942                 u3d->irq = 0;
1943                 dev_err(&dev->dev, "Request irq %d for u3d failed\n",
1944                         u3d->irq);
1945                 retval = -ENODEV;
1946                 goto err_request_irq;
1947         }
1948
1949         /* initialize gadget structure */
1950         u3d->gadget.ops = &mv_u3d_ops;  /* usb_gadget_ops */
1951         u3d->gadget.ep0 = &u3d->eps[1].ep;      /* gadget ep0 */
1952         INIT_LIST_HEAD(&u3d->gadget.ep_list);   /* ep_list */
1953         u3d->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
1954
1955         /* the "gadget" abstracts/virtualizes the controller */
1956         u3d->gadget.name = driver_name;         /* gadget name */
1957
1958         mv_u3d_eps_init(u3d);
1959
1960         /* external vbus detection */
1961         if (u3d->vbus) {
1962                 u3d->clock_gating = 1;
1963                 dev_err(&dev->dev, "external vbus detection\n");
1964         }
1965
1966         if (!u3d->clock_gating)
1967                 u3d->vbus_active = 1;
1968
1969         /* enable usb3 controller vbus detection */
1970         u3d->vbus_valid_detect = 1;
1971
1972         retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget);
1973         if (retval)
1974                 goto err_unregister;
1975
1976         dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n",
1977                 u3d->clock_gating ? "with" : "without");
1978
1979         return 0;
1980
1981 err_unregister:
1982         free_irq(u3d->irq, u3d);
1983 err_request_irq:
1984 err_get_irq:
1985         kfree(u3d->status_req);
1986 err_alloc_status_req:
1987         kfree(u3d->eps);
1988 err_alloc_eps:
1989         dma_pool_destroy(u3d->trb_pool);
1990 err_alloc_trb_pool:
1991         dma_free_coherent(&dev->dev, u3d->ep_context_size,
1992                 u3d->ep_context, u3d->ep_context_dma);
1993 err_alloc_ep_context:
1994         if (pdata->phy_deinit)
1995                 pdata->phy_deinit(u3d->phy_regs);
1996         clk_disable(u3d->clk);
1997 err_u3d_enable:
1998         iounmap(u3d->cap_regs);
1999 err_map_cap_regs:
2000 err_get_cap_regs:
2001 err_get_clk:
2002         clk_put(u3d->clk);
2003         kfree(u3d);
2004 err_alloc_private:
2005 err_pdata:
2006         return retval;
2007 }
2008
2009 #ifdef CONFIG_PM_SLEEP
2010 static int mv_u3d_suspend(struct device *dev)
2011 {
2012         struct mv_u3d *u3d = dev_get_drvdata(dev);
2013
2014         /*
2015          * only cable is unplugged, usb can suspend.
2016          * So do not care about clock_gating == 1, it is handled by
2017          * vbus session.
2018          */
2019         if (!u3d->clock_gating) {
2020                 mv_u3d_controller_stop(u3d);
2021
2022                 spin_lock_irq(&u3d->lock);
2023                 /* stop all usb activities */
2024                 mv_u3d_stop_activity(u3d, u3d->driver);
2025                 spin_unlock_irq(&u3d->lock);
2026
2027                 mv_u3d_disable(u3d);
2028         }
2029
2030         return 0;
2031 }
2032
2033 static int mv_u3d_resume(struct device *dev)
2034 {
2035         struct mv_u3d *u3d = dev_get_drvdata(dev);
2036         int retval;
2037
2038         if (!u3d->clock_gating) {
2039                 retval = mv_u3d_enable(u3d);
2040                 if (retval)
2041                         return retval;
2042
2043                 if (u3d->driver && u3d->softconnect) {
2044                         mv_u3d_controller_reset(u3d);
2045                         mv_u3d_ep0_reset(u3d);
2046                         mv_u3d_controller_start(u3d);
2047                 }
2048         }
2049
2050         return 0;
2051 }
2052 #endif
2053
2054 static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume);
2055
2056 static void mv_u3d_shutdown(struct platform_device *dev)
2057 {
2058         struct mv_u3d *u3d = platform_get_drvdata(dev);
2059         u32 tmp;
2060
2061         tmp = ioread32(&u3d->op_regs->usbcmd);
2062         tmp &= ~MV_U3D_CMD_RUN_STOP;
2063         iowrite32(tmp, &u3d->op_regs->usbcmd);
2064 }
2065
2066 static struct platform_driver mv_u3d_driver = {
2067         .probe          = mv_u3d_probe,
2068         .remove         = mv_u3d_remove,
2069         .shutdown       = mv_u3d_shutdown,
2070         .driver         = {
2071                 .owner  = THIS_MODULE,
2072                 .name   = "mv-u3d",
2073                 .pm     = &mv_u3d_pm_ops,
2074         },
2075 };
2076
2077 module_platform_driver(mv_u3d_driver);
2078 MODULE_ALIAS("platform:mv-u3d");
2079 MODULE_DESCRIPTION(DRIVER_DESC);
2080 MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>");
2081 MODULE_LICENSE("GPL");