drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h

   1 /*
   2  * ti_hdmi_4xxx_ip.h
   3  *
   4  * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
   5  *
   6  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef _HDMI_TI_4xxx_H_
  22 #define _HDMI_TI_4xxx_H_
  23
  24 #include <linux/string.h>
  25 #include <video/omapdss.h>
  26 #include "ti_hdmi.h"
  27
  28 /* HDMI Wrapper */
  29
  30 #define HDMI_WP_REVISION                        0x0
  31 #define HDMI_WP_SYSCONFIG                       0x10
  32 #define HDMI_WP_IRQSTATUS_RAW                   0x24
  33 #define HDMI_WP_IRQSTATUS                       0x28
  34 #define HDMI_WP_PWR_CTRL                        0x40
  35 #define HDMI_WP_IRQENABLE_SET                   0x2C
  36 #define HDMI_WP_IRQENABLE_CLR                   0x30
  37 #define HDMI_WP_VIDEO_CFG                       0x50
  38 #define HDMI_WP_VIDEO_SIZE                      0x60
  39 #define HDMI_WP_VIDEO_TIMING_H                  0x68
  40 #define HDMI_WP_VIDEO_TIMING_V                  0x6C
  41 #define HDMI_WP_WP_CLK                          0x70
  42 #define HDMI_WP_AUDIO_CFG                       0x80
  43 #define HDMI_WP_AUDIO_CFG2                      0x84
  44 #define HDMI_WP_AUDIO_CTRL                      0x88
  45 #define HDMI_WP_AUDIO_DATA                      0x8C
  46
  47 /* HDMI IP Core System */
  48
  49 #define HDMI_CORE_SYS_VND_IDL                   0x0
  50 #define HDMI_CORE_SYS_DEV_IDL                   0x8
  51 #define HDMI_CORE_SYS_DEV_IDH                   0xC
  52 #define HDMI_CORE_SYS_DEV_REV                   0x10
  53 #define HDMI_CORE_SYS_SRST                      0x14
  54 #define HDMI_CORE_CTRL1                         0x20
  55 #define HDMI_CORE_SYS_SYS_STAT                  0x24
  56 #define HDMI_CORE_SYS_DE_DLY                    0xC8
  57 #define HDMI_CORE_SYS_DE_CTRL                   0xCC
  58 #define HDMI_CORE_SYS_DE_TOP                    0xD0
  59 #define HDMI_CORE_SYS_DE_CNTL                   0xD8
  60 #define HDMI_CORE_SYS_DE_CNTH                   0xDC
  61 #define HDMI_CORE_SYS_DE_LINL                   0xE0
  62 #define HDMI_CORE_SYS_DE_LINH_1                 0xE4
  63 #define HDMI_CORE_SYS_VID_ACEN                  0x124
  64 #define HDMI_CORE_SYS_VID_MODE                  0x128
  65 #define HDMI_CORE_SYS_INTR_STATE                0x1C0
  66 #define HDMI_CORE_SYS_INTR1                     0x1C4
  67 #define HDMI_CORE_SYS_INTR2                     0x1C8
  68 #define HDMI_CORE_SYS_INTR3                     0x1CC
  69 #define HDMI_CORE_SYS_INTR4                     0x1D0
  70 #define HDMI_CORE_SYS_UMASK1                    0x1D4
  71 #define HDMI_CORE_SYS_TMDS_CTRL                 0x208
  72
  73 #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
  74 #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
  75 #define HDMI_CORE_CTRL1_BSEL_24BITBUS   0x1
  76 #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
  77
  78 /* HDMI DDC E-DID */
  79 #define HDMI_CORE_DDC_ADDR                      0x3B4
  80 #define HDMI_CORE_DDC_SEGM                      0x3B8
  81 #define HDMI_CORE_DDC_OFFSET                    0x3BC
  82 #define HDMI_CORE_DDC_COUNT1                    0x3C0
  83 #define HDMI_CORE_DDC_COUNT2                    0x3C4
  84 #define HDMI_CORE_DDC_STATUS                    0x3C8
  85 #define HDMI_CORE_DDC_CMD                       0x3CC
  86 #define HDMI_CORE_DDC_DATA                      0x3D0
  87
  88 /* HDMI IP Core Audio Video */
  89
  90 #define HDMI_CORE_AV_ACR_CTRL                   0x4
  91 #define HDMI_CORE_AV_FREQ_SVAL                  0x8
  92 #define HDMI_CORE_AV_N_SVAL1                    0xC
  93 #define HDMI_CORE_AV_N_SVAL2                    0x10
  94 #define HDMI_CORE_AV_N_SVAL3                    0x14
  95 #define HDMI_CORE_AV_CTS_SVAL1                  0x18
  96 #define HDMI_CORE_AV_CTS_SVAL2                  0x1C
  97 #define HDMI_CORE_AV_CTS_SVAL3                  0x20
  98 #define HDMI_CORE_AV_CTS_HVAL1                  0x24
  99 #define HDMI_CORE_AV_CTS_HVAL2                  0x28
 100 #define HDMI_CORE_AV_CTS_HVAL3                  0x2C
 101 #define HDMI_CORE_AV_AUD_MODE                   0x50
 102 #define HDMI_CORE_AV_SPDIF_CTRL                 0x54
 103 #define HDMI_CORE_AV_HW_SPDIF_FS                0x60
 104 #define HDMI_CORE_AV_SWAP_I2S                   0x64
 105 #define HDMI_CORE_AV_SPDIF_ERTH                 0x6C
 106 #define HDMI_CORE_AV_I2S_IN_MAP                 0x70
 107 #define HDMI_CORE_AV_I2S_IN_CTRL                0x74
 108 #define HDMI_CORE_AV_I2S_CHST0                  0x78
 109 #define HDMI_CORE_AV_I2S_CHST1                  0x7C
 110 #define HDMI_CORE_AV_I2S_CHST2                  0x80
 111 #define HDMI_CORE_AV_I2S_CHST4                  0x84
 112 #define HDMI_CORE_AV_I2S_CHST5                  0x88
 113 #define HDMI_CORE_AV_ASRC                       0x8C
 114 #define HDMI_CORE_AV_I2S_IN_LEN                 0x90
 115 #define HDMI_CORE_AV_HDMI_CTRL                  0xBC
 116 #define HDMI_CORE_AV_AUDO_TXSTAT                0xC0
 117 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1           0xCC
 118 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2           0xD0
 119 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3           0xD4
 120 #define HDMI_CORE_AV_TEST_TXCTRL                0xF0
 121 #define HDMI_CORE_AV_DPD                        0xF4
 122 #define HDMI_CORE_AV_PB_CTRL1                   0xF8
 123 #define HDMI_CORE_AV_PB_CTRL2                   0xFC
 124 #define HDMI_CORE_AV_AVI_TYPE                   0x100
 125 #define HDMI_CORE_AV_AVI_VERS                   0x104
 126 #define HDMI_CORE_AV_AVI_LEN                    0x108
 127 #define HDMI_CORE_AV_AVI_CHSUM                  0x10C
 128 #define HDMI_CORE_AV_AVI_DBYTE(n)               (n * 4 + 0x110)
 129 #define HDMI_CORE_AV_SPD_TYPE                   0x180
 130 #define HDMI_CORE_AV_SPD_VERS                   0x184
 131 #define HDMI_CORE_AV_SPD_LEN                    0x188
 132 #define HDMI_CORE_AV_SPD_CHSUM                  0x18C
 133 #define HDMI_CORE_AV_SPD_DBYTE(n)               (n * 4 + 0x190)
 134 #define HDMI_CORE_AV_AUDIO_TYPE                 0x200
 135 #define HDMI_CORE_AV_AUDIO_VERS                 0x204
 136 #define HDMI_CORE_AV_AUDIO_LEN                  0x208
 137 #define HDMI_CORE_AV_AUDIO_CHSUM                0x20C
 138 #define HDMI_CORE_AV_AUD_DBYTE(n)               (n * 4 + 0x210)
 139 #define HDMI_CORE_AV_MPEG_TYPE                  0x280
 140 #define HDMI_CORE_AV_MPEG_VERS                  0x284
 141 #define HDMI_CORE_AV_MPEG_LEN                   0x288
 142 #define HDMI_CORE_AV_MPEG_CHSUM                 0x28C
 143 #define HDMI_CORE_AV_MPEG_DBYTE(n)              (n * 4 + 0x290)
 144 #define HDMI_CORE_AV_GEN_DBYTE(n)               (n * 4 + 0x300)
 145 #define HDMI_CORE_AV_CP_BYTE1                   0x37C
 146 #define HDMI_CORE_AV_GEN2_DBYTE(n)              (n * 4 + 0x380)
 147 #define HDMI_CORE_AV_CEC_ADDR_ID                0x3FC
 148
 149 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE           0x4
 150 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE          0x4
 151 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE          0x4
 152 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE           0x4
 153
 154 #define HDMI_CORE_AV_AVI_DBYTE_NELEMS           15
 155 #define HDMI_CORE_AV_SPD_DBYTE_NELEMS           27
 156 #define HDMI_CORE_AV_AUD_DBYTE_NELEMS           10
 157 #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS          27
 158 #define HDMI_CORE_AV_GEN_DBYTE_NELEMS           31
 159 #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS          31
 160
 161 /* PLL */
 162
 163 #define PLLCTRL_PLL_CONTROL                     0x0
 164 #define PLLCTRL_PLL_STATUS                      0x4
 165 #define PLLCTRL_PLL_GO                          0x8
 166 #define PLLCTRL_CFG1                            0xC
 167 #define PLLCTRL_CFG2                            0x10
 168 #define PLLCTRL_CFG3                            0x14
 169 #define PLLCTRL_CFG4                            0x20
 170
 171 /* HDMI PHY */
 172
 173 #define HDMI_TXPHY_TX_CTRL                      0x0
 174 #define HDMI_TXPHY_DIGITAL_CTRL                 0x4
 175 #define HDMI_TXPHY_POWER_CTRL                   0x8
 176 #define HDMI_TXPHY_PAD_CFG_CTRL                 0xC
 177
 178 #define REG_FLD_MOD(base, idx, val, start, end) \
 179         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
 180                                                         val, start, end))
 181 #define REG_GET(base, idx, start, end) \
 182         FLD_GET(hdmi_read_reg(base, idx), start, end)
 183
 184 enum hdmi_phy_pwr {
 185         HDMI_PHYPWRCMD_OFF = 0,
 186         HDMI_PHYPWRCMD_LDOON = 1,
 187         HDMI_PHYPWRCMD_TXON = 2
 188 };
 189
 190 enum hdmi_core_inputbus_width {
 191         HDMI_INPUT_8BIT = 0,
 192         HDMI_INPUT_10BIT = 1,
 193         HDMI_INPUT_12BIT = 2
 194 };
 195
 196 enum hdmi_core_dither_trunc {
 197         HDMI_OUTPUTTRUNCATION_8BIT = 0,
 198         HDMI_OUTPUTTRUNCATION_10BIT = 1,
 199         HDMI_OUTPUTTRUNCATION_12BIT = 2,
 200         HDMI_OUTPUTDITHER_8BIT = 3,
 201         HDMI_OUTPUTDITHER_10BIT = 4,
 202         HDMI_OUTPUTDITHER_12BIT = 5
 203 };
 204
 205 enum hdmi_core_deepcolor_ed {
 206         HDMI_DEEPCOLORPACKECTDISABLE = 0,
 207         HDMI_DEEPCOLORPACKECTENABLE = 1
 208 };
 209
 210 enum hdmi_core_packet_mode {
 211         HDMI_PACKETMODERESERVEDVALUE = 0,
 212         HDMI_PACKETMODE24BITPERPIXEL = 4,
 213         HDMI_PACKETMODE30BITPERPIXEL = 5,
 214         HDMI_PACKETMODE36BITPERPIXEL = 6,
 215         HDMI_PACKETMODE48BITPERPIXEL = 7
 216 };
 217
 218 enum hdmi_core_tclkselclkmult {
 219         HDMI_FPLL05IDCK = 0,
 220         HDMI_FPLL10IDCK = 1,
 221         HDMI_FPLL20IDCK = 2,
 222         HDMI_FPLL40IDCK = 3
 223 };
 224
 225 enum hdmi_core_packet_ctrl {
 226         HDMI_PACKETENABLE = 1,
 227         HDMI_PACKETDISABLE = 0,
 228         HDMI_PACKETREPEATON = 1,
 229         HDMI_PACKETREPEATOFF = 0
 230 };
 231
 232 /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
 233 enum hdmi_core_infoframe {
 234         HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
 235         HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
 236         HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
 237         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
 238         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
 239         HDMI_INFOFRAME_AVI_DB1B_NO = 0,
 240         HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
 241         HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
 242         HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
 243         HDMI_INFOFRAME_AVI_DB1S_0 = 0,
 244         HDMI_INFOFRAME_AVI_DB1S_1 = 1,
 245         HDMI_INFOFRAME_AVI_DB1S_2 = 2,
 246         HDMI_INFOFRAME_AVI_DB2C_NO = 0,
 247         HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
 248         HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
 249         HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
 250         HDMI_INFOFRAME_AVI_DB2M_NO = 0,
 251         HDMI_INFOFRAME_AVI_DB2M_43 = 1,
 252         HDMI_INFOFRAME_AVI_DB2M_169 = 2,
 253         HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
 254         HDMI_INFOFRAME_AVI_DB2R_43 = 9,
 255         HDMI_INFOFRAME_AVI_DB2R_169 = 10,
 256         HDMI_INFOFRAME_AVI_DB2R_149 = 11,
 257         HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
 258         HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
 259         HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
 260         HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
 261         HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
 262         HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
 263         HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
 264         HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
 265         HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
 266         HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
 267         HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
 268         HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
 269         HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
 270         HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
 271         HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
 272         HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
 273         HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
 274         HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
 275         HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
 276         HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
 277         HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
 278 };
 279
 280 enum hdmi_packing_mode {
 281         HDMI_PACK_10b_RGB_YUV444 = 0,
 282         HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
 283         HDMI_PACK_20b_YUV422 = 2,
 284         HDMI_PACK_ALREADYPACKED = 7
 285 };
 286
 287 enum hdmi_core_audio_layout {
 288         HDMI_AUDIO_LAYOUT_2CH = 0,
 289         HDMI_AUDIO_LAYOUT_8CH = 1
 290 };
 291
 292 enum hdmi_core_cts_mode {
 293         HDMI_AUDIO_CTS_MODE_HW = 0,
 294         HDMI_AUDIO_CTS_MODE_SW = 1
 295 };
 296
 297 enum hdmi_stereo_channels {
 298         HDMI_AUDIO_STEREO_NOCHANNELS = 0,
 299         HDMI_AUDIO_STEREO_ONECHANNEL = 1,
 300         HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
 301         HDMI_AUDIO_STEREO_THREECHANNELS = 3,
 302         HDMI_AUDIO_STEREO_FOURCHANNELS = 4
 303 };
 304
 305 enum hdmi_audio_type {
 306         HDMI_AUDIO_TYPE_LPCM = 0,
 307         HDMI_AUDIO_TYPE_IEC = 1
 308 };
 309
 310 enum hdmi_audio_justify {
 311         HDMI_AUDIO_JUSTIFY_LEFT = 0,
 312         HDMI_AUDIO_JUSTIFY_RIGHT = 1
 313 };
 314
 315 enum hdmi_audio_sample_order {
 316         HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
 317         HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
 318 };
 319
 320 enum hdmi_audio_samples_perword {
 321         HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
 322         HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
 323 };
 324
 325 enum hdmi_audio_sample_size {
 326         HDMI_AUDIO_SAMPLE_16BITS = 0,
 327         HDMI_AUDIO_SAMPLE_24BITS = 1
 328 };
 329
 330 enum hdmi_audio_transf_mode {
 331         HDMI_AUDIO_TRANSF_DMA = 0,
 332         HDMI_AUDIO_TRANSF_IRQ = 1
 333 };
 334
 335 enum hdmi_audio_blk_strt_end_sig {
 336         HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
 337         HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
 338 };
 339
 340 enum hdmi_audio_i2s_config {
 341         HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
 342         HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
 343         HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
 344         HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
 345         HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
 346         HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
 347         HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
 348         HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
 349         HDMI_AUDIO_I2S_SD0_EN = 1,
 350         HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
 351         HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
 352         HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
 353 };
 354
 355 enum hdmi_audio_mclk_mode {
 356         HDMI_AUDIO_MCLK_128FS = 0,
 357         HDMI_AUDIO_MCLK_256FS = 1,
 358         HDMI_AUDIO_MCLK_384FS = 2,
 359         HDMI_AUDIO_MCLK_512FS = 3,
 360         HDMI_AUDIO_MCLK_768FS = 4,
 361         HDMI_AUDIO_MCLK_1024FS = 5,
 362         HDMI_AUDIO_MCLK_1152FS = 6,
 363         HDMI_AUDIO_MCLK_192FS = 7
 364 };
 365
 366 struct hdmi_core_video_config {
 367         enum hdmi_core_inputbus_width   ip_bus_width;
 368         enum hdmi_core_dither_trunc     op_dither_truc;
 369         enum hdmi_core_deepcolor_ed     deep_color_pkt;
 370         enum hdmi_core_packet_mode      pkt_mode;
 371         enum hdmi_core_hdmi_dvi         hdmi_dvi;
 372         enum hdmi_core_tclkselclkmult   tclk_sel_clkmult;
 373 };
 374
 375 struct hdmi_core_packet_enable_repeat {
 376         u32     audio_pkt;
 377         u32     audio_pkt_repeat;
 378         u32     avi_infoframe;
 379         u32     avi_infoframe_repeat;
 380         u32     gen_cntrl_pkt;
 381         u32     gen_cntrl_pkt_repeat;
 382         u32     generic_pkt;
 383         u32     generic_pkt_repeat;
 384 };
 385
 386 struct hdmi_video_format {
 387         enum hdmi_packing_mode  packing_mode;
 388         u32                     y_res;  /* Line per panel */
 389         u32                     x_res;  /* pixel per line */
 390 };
 391
 392 struct hdmi_audio_format {
 393         enum hdmi_stereo_channels               stereo_channels;
 394         u8                                      active_chnnls_msk;
 395         enum hdmi_audio_type                    type;
 396         enum hdmi_audio_justify                 justification;
 397         enum hdmi_audio_sample_order            sample_order;
 398         enum hdmi_audio_samples_perword         samples_per_word;
 399         enum hdmi_audio_sample_size             sample_size;
 400         enum hdmi_audio_blk_strt_end_sig        en_sig_blk_strt_end;
 401 };
 402
 403 struct hdmi_audio_dma {
 404         u8                              transfer_size;
 405         u8                              block_size;
 406         enum hdmi_audio_transf_mode     mode;
 407         u16                             fifo_threshold;
 408 };
 409
 410 struct hdmi_core_audio_i2s_config {
 411         u8 in_length_bits;
 412         u8 justification;
 413         u8 sck_edge_mode;
 414         u8 vbit;
 415         u8 direction;
 416         u8 shift;
 417         u8 active_sds;
 418 };
 419
 420 struct hdmi_core_audio_config {
 421         struct hdmi_core_audio_i2s_config       i2s_cfg;
 422         struct snd_aes_iec958                   *iec60958_cfg;
 423         bool                                    fs_override;
 424         u32                                     n;
 425         u32                                     cts;
 426         u32                                     aud_par_busclk;
 427         enum hdmi_core_audio_layout             layout;
 428         enum hdmi_core_cts_mode                 cts_mode;
 429         bool                                    use_mclk;
 430         enum hdmi_audio_mclk_mode               mclk_mode;
 431         bool                                    en_acr_pkt;
 432         bool                                    en_dsd_audio;
 433         bool                                    en_parallel_aud_input;
 434         bool                                    en_spdif;
 435 };
 436
 437 #endif