include/linux/irqchip/arm-gic.h

   1 /*
   2  *  include/linux/irqchip/arm-gic.h
   3  *
   4  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef __LINUX_IRQCHIP_ARM_GIC_H
  11 #define __LINUX_IRQCHIP_ARM_GIC_H
  12
  13 #define GIC_CPU_CTRL                    0x00
  14 #define GIC_CPU_PRIMASK                 0x04
  15 #define GIC_CPU_BINPOINT                0x08
  16 #define GIC_CPU_INTACK                  0x0c
  17 #define GIC_CPU_EOI                     0x10
  18 #define GIC_CPU_RUNNINGPRI              0x14
  19 #define GIC_CPU_HIGHPRI                 0x18
  20
  21 #define GIC_DIST_CTRL                   0x000
  22 #define GIC_DIST_CTR                    0x004
  23 #define GIC_DIST_IGROUP                 0x080
  24 #define GIC_DIST_ENABLE_SET             0x100
  25 #define GIC_DIST_ENABLE_CLEAR           0x180
  26 #define GIC_DIST_PENDING_SET            0x200
  27 #define GIC_DIST_PENDING_CLEAR          0x280
  28 #define GIC_DIST_ACTIVE_SET             0x300
  29 #define GIC_DIST_ACTIVE_CLEAR           0x380
  30 #define GIC_DIST_PRI                    0x400
  31 #define GIC_DIST_TARGET                 0x800
  32 #define GIC_DIST_CONFIG                 0xc00
  33 #define GIC_DIST_SOFTINT                0xf00
  34 #define GIC_DIST_SGI_PENDING_CLEAR      0xf10
  35 #define GIC_DIST_SGI_PENDING_SET        0xf20
  36
  37 #define GICH_HCR                        0x0
  38 #define GICH_VTR                        0x4
  39 #define GICH_VMCR                       0x8
  40 #define GICH_MISR                       0x10
  41 #define GICH_EISR0                      0x20
  42 #define GICH_EISR1                      0x24
  43 #define GICH_ELRSR0                     0x30
  44 #define GICH_ELRSR1                     0x34
  45 #define GICH_APR                        0xf0
  46 #define GICH_LR0                        0x100
  47
  48 #define GICH_HCR_EN                     (1 << 0)
  49 #define GICH_HCR_UIE                    (1 << 1)
  50
  51 #define GICH_LR_VIRTUALID               (0x3ff << 0)
  52 #define GICH_LR_PHYSID_CPUID_SHIFT      (10)
  53 #define GICH_LR_PHYSID_CPUID            (7 << GICH_LR_PHYSID_CPUID_SHIFT)
  54 #define GICH_LR_STATE                   (3 << 28)
  55 #define GICH_LR_PENDING_BIT             (1 << 28)
  56 #define GICH_LR_ACTIVE_BIT              (1 << 29)
  57 #define GICH_LR_EOI                     (1 << 19)
  58
  59 #define GICH_MISR_EOI                   (1 << 0)
  60 #define GICH_MISR_U                     (1 << 1)
  61
  62 #ifndef __ASSEMBLY__
  63
  64 struct device_node;
  65
  66 extern struct irq_chip gic_arch_extn;
  67
  68 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
  69                     u32 offset, struct device_node *);
  70 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
  71 void gic_cpu_if_down(void);
  72
  73 static inline void gic_init(unsigned int nr, int start,
  74                             void __iomem *dist , void __iomem *cpu)
  75 {
  76         gic_init_bases(nr, start, dist, cpu, 0, NULL);
  77 }
  78
  79 int gic_get_cpu_id(unsigned int cpu);
  80 void gic_migrate_target(unsigned int new_cpu_id);
  81
  82 #endif /* __ASSEMBLY */
  83
  84 #endif