2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 #ifndef LINUX_MMC_SDHCI_H
12 #define LINUX_MMC_SDHCI_H
14 #include <linux/scatterlist.h>
15 #include <linux/workqueue.h>
16 #include <linux/compiler.h>
17 #include <linux/types.h>
19 #include <linux/mmc/host.h>
22 /* Data set by hardware interface driver */
23 const char *hw_name; /* Hardware bus name */
25 unsigned int quirks; /* Deviations from spec. */
27 /* Controller doesn't honor resets unless we touch the clock register */
28 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
29 /* Controller has bad caps bits, but really supports DMA */
30 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
31 /* Controller doesn't like to be reset when there is no card inserted. */
32 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
33 /* Controller doesn't like clearing the power reg before a change */
34 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
35 /* Controller has flaky internal state so reset it on each ios change */
36 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
37 /* Controller has an unusable DMA engine */
38 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
39 /* Controller has an unusable ADMA engine */
40 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
41 /* Controller can only DMA from 32-bit aligned addresses */
42 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
43 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
44 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
45 /* Controller can only ADMA chunks that are a multiple of 32 bits */
46 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
47 /* Controller needs to be reset after each request to stay stable */
48 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
49 /* Controller needs voltage and power writes to happen separately */
50 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
51 /* Controller provides an incorrect timeout value for transfers */
52 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
53 /* Controller has an issue with buffer bits for small transfers */
54 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
55 /* Controller does not provide transfer-complete interrupt when not busy */
56 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
57 /* Controller has unreliable card detection */
58 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
59 /* Controller reports inverted write-protect state */
60 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
61 /* Controller has nonstandard clock management */
62 #define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
63 /* Controller does not like fast PIO transfers */
64 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
65 /* Controller losing signal/interrupt enable states after reset */
66 #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
67 /* Controller has to be forced to use block size of 2048 bytes */
68 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
69 /* Controller cannot do multi-block transfers */
70 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
71 /* Controller can only handle 1-bit data transfers */
72 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
73 /* Controller needs 10ms delay between applying power and clock */
74 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
75 /* Controller uses SDCLK instead of TMCLK for data timeouts */
76 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
77 /* Controller reports wrong base clock capability */
78 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
79 /* Controller cannot support End Attribute in NOP ADMA descriptor */
80 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
81 /* Controller is missing device caps. Use caps provided by host */
82 #define SDHCI_QUIRK_MISSING_CAPS (1<<27)
83 /* Controller uses Auto CMD12 command to stop the transfer */
84 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
85 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
86 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
87 /* Controller treats ADMA descriptors with length 0000h incorrectly */
88 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
89 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
90 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
92 unsigned int quirks2; /* More deviations from spec. */
94 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
95 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
96 /* The system physically doesn't support 1.8v, even if the host does */
97 #define SDHCI_QUIRK2_NO_1_8_V (1<<2)
98 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
99 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
100 /* Controller has a non-standard host control register */
101 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
103 int irq; /* Device IRQ */
104 void __iomem *ioaddr; /* Mapped address */
106 const struct sdhci_ops *ops; /* Low level hw interface */
108 struct regulator *vmmc; /* Power regulator (vmmc) */
109 struct regulator *vqmmc; /* Signaling regulator (vccq) */
112 struct mmc_host *mmc; /* MMC structure */
113 u64 dma_mask; /* custom DMA mask */
115 #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
116 struct led_classdev led; /* LED control */
120 spinlock_t lock; /* Mutex */
122 int flags; /* Host attributes */
123 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
124 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
125 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
126 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
127 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
128 #define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
129 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
130 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
131 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
132 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
133 #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
134 #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
136 unsigned int version; /* SDHCI spec. version */
138 unsigned int max_clk; /* Max possible freq (MHz) */
139 unsigned int timeout_clk; /* Timeout freq (KHz) */
140 unsigned int clk_mul; /* Clock Muliplier value */
142 unsigned int clock; /* Current clock (MHz) */
143 u8 pwr; /* Current voltage */
145 bool runtime_suspended; /* Host is runtime suspended */
146 bool bus_on; /* Bus power prevents runtime suspend */
148 struct mmc_request *mrq; /* Current request */
149 struct mmc_command *cmd; /* Current command */
150 struct mmc_data *data; /* Current data request */
151 unsigned int data_early:1; /* Data finished before cmd */
153 struct sg_mapping_iter sg_miter; /* SG state for PIO */
154 unsigned int blocks; /* remaining PIO blocks */
156 int sg_count; /* Mapped sg entries */
158 u8 *adma_desc; /* ADMA descriptor table */
159 u8 *align_buffer; /* Bounce buffer */
161 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
162 dma_addr_t align_addr; /* Mapped bounce buffer */
164 struct work_struct card_detect_work;
165 struct work_struct finish_work;
167 struct delayed_work timeout_work; /* Work for timeouts */
169 u32 caps; /* Alternative CAPABILITY_0 */
170 u32 caps1; /* Alternative CAPABILITY_1 */
172 unsigned int ocr_avail_sdio; /* OCR bit masks */
173 unsigned int ocr_avail_sd;
174 unsigned int ocr_avail_mmc;
175 u32 ocr_mask; /* available voltages */
177 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
178 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
180 unsigned int tuning_count; /* Timer count for re-tuning */
181 unsigned int tuning_mode; /* Re-tuning mode supported by host */
182 #define SDHCI_TUNING_MODE_1 0
183 struct delayed_work tuning_timeout_work; /* Work for tuning timeouts */
185 unsigned long private[0] ____cacheline_aligned;
187 #endif /* LINUX_MMC_SDHCI_H */