1 #include <linux/delay.h>
3 #include <linux/interrupt.h>
4 #include <linux/module.h>
5 #include <linux/regulator/consumer.h>
6 #include <linux/types.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/mfd/syscon.h>
15 #include <sound/soc.h>
16 #include <sound/soc-dapm.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include "msm8x16-wcd.h"
22 #include "msm8x16_wcd_registers.h"
24 #define MSM8X16_WCD_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
25 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
26 #define MSM8X16_WCD_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
27 SNDRV_PCM_FMTBIT_S24_LE)
29 #define TOMBAK_VERSION_1_0 0
30 #define TOMBAK_IS_1_0(ver) \
31 ((ver == TOMBAK_VERSION_1_0) ? 1 : 0)
33 #define HPHL_PA_DISABLE (0x01 << 1)
34 #define HPHR_PA_DISABLE (0x01 << 2)
35 #define EAR_PA_DISABLE (0x01 << 3)
36 #define SPKR_PA_DISABLE (0x01 << 4)
38 #define MICBIAS_DEFAULT_VAL 1800000
39 #define MICBIAS_MIN_VAL 1600000
40 #define MICBIAS_STEP_SIZE 50000
42 #define DEFAULT_BOOST_VOLTAGE 5000
43 #define MIN_BOOST_VOLTAGE 4000
44 #define MAX_BOOST_VOLTAGE 5550
45 #define BOOST_VOLTAGE_STEP 50
47 #define VOLTAGE_CONVERTER(value, min_value, step_size)\
48 ((value - min_value)/step_size);
56 static unsigned long rx_digital_gain_reg[] = {
57 MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
58 MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
59 MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
62 static unsigned long tx_digital_gain_reg[] = {
63 MSM8X16_WCD_A_CDC_TX1_VOL_CTL_GAIN,
64 MSM8X16_WCD_A_CDC_TX2_VOL_CTL_GAIN,
68 struct regmap *analog_map;
69 struct regmap *digital_map;
70 unsigned int analog_base;
76 bool ear_pa_boost_set;
80 struct regulator *vddio;
81 struct regulator *vdd_pa;
82 struct regulator *vdd_px;
83 struct regulator *vdd_cp;
84 struct regulator *vdd_mic_bias;
87 static int msm8x16_wcd_volatile(struct snd_soc_codec *codec, unsigned int reg)
89 return msm8x16_wcd_reg_readonly[reg];
92 static int msm8x16_wcd_readable(struct snd_soc_codec *ssc, unsigned int reg)
94 return msm8x16_wcd_reg_readable[reg];
97 static int __msm8x16_wcd_reg_write(struct snd_soc_codec *codec,
98 unsigned short reg, u8 val)
101 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
103 if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
104 ret = regmap_write(chip->analog_map,
105 chip->analog_base + reg, val);
106 } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
107 u32 temp = val & 0x000000FF;
108 u16 offset = (reg ^ 0x0200) & 0x0FFF;
110 ret = regmap_write(chip->digital_map, offset, temp);
116 static int msm8x16_wcd_write(struct snd_soc_codec *codec, unsigned int reg,
119 if (reg == SND_SOC_NOPM)
122 BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
123 if (!msm8x16_wcd_volatile(codec, reg))
124 msm8x16_wcd_reset_reg_defaults[reg] = value;
126 return __msm8x16_wcd_reg_write(codec, reg, (u8)value);
129 static int __msm8x16_wcd_reg_read(struct snd_soc_codec *codec,
134 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
136 if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
137 ret = regmap_read(chip->analog_map,
138 chip->analog_base + reg, &temp);
139 } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
141 u16 offset = (reg ^ 0x0200) & 0x0FFF;
143 ret = regmap_read(chip->digital_map, offset, &val);
149 "%s: codec read failed for reg 0x%x\n",
154 dev_dbg(codec->dev, "Read 0x%02x from 0x%x\n", temp, reg);
159 static unsigned int msm8x16_wcd_read(struct snd_soc_codec *codec,
164 if (reg == SND_SOC_NOPM)
167 BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
169 if (!msm8x16_wcd_volatile(codec, reg) &&
170 msm8x16_wcd_readable(codec, reg) &&
171 reg < codec->driver->reg_cache_size) {
172 return msm8x16_wcd_reset_reg_defaults[reg];
175 val = __msm8x16_wcd_reg_read(codec, reg);
180 static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults[] = {
181 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
182 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
183 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
186 static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults_2_0[] = {
187 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL3, 0x0F),
188 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS, 0x4B),
189 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x28),
190 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0x69),
191 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG, 0x01),
192 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL, 0x5F),
193 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO, 0x88),
194 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3, 0x0F),
195 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
196 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
197 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
200 static int msm8x16_wcd_bringup(struct snd_soc_codec *codec)
202 snd_soc_write(codec, MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL4, 0x01);
203 snd_soc_write(codec, MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL4, 0x01);
207 static const struct msm8x16_wcd_reg_mask_val
208 msm8x16_wcd_codec_reg_init_val[] = {
210 /* Initialize current threshold to 350MA
211 * number of wait and run cycles to 4096
213 {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL, 0xFF, 0xD1},
214 {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT, 0xFF, 0xFF},
217 static void msm8x16_wcd_codec_init_reg(struct snd_soc_codec *codec)
221 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_codec_reg_init_val); i++)
222 snd_soc_update_bits(codec,
223 msm8x16_wcd_codec_reg_init_val[i].reg,
224 msm8x16_wcd_codec_reg_init_val[i].mask,
225 msm8x16_wcd_codec_reg_init_val[i].val);
228 static void msm8x16_wcd_update_reg_defaults(struct snd_soc_codec *codec)
231 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
233 if (TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev)) {
234 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults); i++)
235 snd_soc_write(codec, msm8x16_wcd_reg_defaults[i].reg,
236 msm8x16_wcd_reg_defaults[i].val);
238 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults_2_0); i++)
240 msm8x16_wcd_reg_defaults_2_0[i].reg,
241 msm8x16_wcd_reg_defaults_2_0[i].val);
245 static int msm8x16_wcd_device_up(struct snd_soc_codec *codec)
249 dev_dbg(codec->dev, "%s: device up!\n", __func__);
250 msm8x16_wcd_bringup(codec);
252 for (reg = 0; reg < ARRAY_SIZE(msm8x16_wcd_reset_reg_defaults); reg++)
253 if (msm8x16_wcd_reg_readable[reg])
254 msm8x16_wcd_write(codec,
255 reg, msm8x16_wcd_reset_reg_defaults[reg]);
257 /* delay is required to make sure sound card state updated */
258 usleep_range(5000, 5100);
260 msm8x16_wcd_codec_init_reg(codec);
261 msm8x16_wcd_update_reg_defaults(codec);
266 static int msm8x16_wcd_codec_enable_clock_block(struct snd_soc_codec *codec,
269 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
270 unsigned long mclk_rate;
273 snd_soc_update_bits(codec,
274 MSM8X16_WCD_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
275 snd_soc_update_bits(codec,
276 MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x03);
277 snd_soc_update_bits(codec,
278 MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
279 snd_soc_update_bits(codec,
280 MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
281 snd_soc_update_bits(codec,
282 MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
284 mclk_rate = clk_get_rate(msm8x16_wcd->mclk);
286 if (mclk_rate == 12288000)
287 snd_soc_update_bits(codec,
288 MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x00);
289 else if (mclk_rate == 9600000)
290 snd_soc_update_bits(codec,
291 MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x01);
293 snd_soc_update_bits(codec,
294 MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
295 snd_soc_update_bits(codec,
296 MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
302 #define MICBIAS_EXT_BYP_CAP 0x00
303 #define MICBIAS_NO_EXT_BYP_CAP 0x01
305 static void msm8x16_wcd_configure_cap(struct snd_soc_codec *codec,
306 bool micbias1, bool micbias2)
309 // struct msm8916_asoc_mach_data *pdata = NULL;
310 //FIXME should come from DT
311 int micbias1_cap_mode = MICBIAS_EXT_BYP_CAP, micbias2_cap_mode = MICBIAS_NO_EXT_BYP_CAP;
313 //pdata = snd_soc_card_get_drvdata(codec->card);
315 pr_debug("\n %s: micbias1 %x micbias2 = %d\n", __func__, micbias1,
317 if (micbias1 && micbias2) {
318 if ((micbias1_cap_mode
319 == MICBIAS_EXT_BYP_CAP) ||
321 == MICBIAS_EXT_BYP_CAP))
322 snd_soc_update_bits(codec,
323 MSM8X16_WCD_A_ANALOG_MICB_1_EN,
324 0x40, (MICBIAS_EXT_BYP_CAP << 6));
326 snd_soc_update_bits(codec,
327 MSM8X16_WCD_A_ANALOG_MICB_1_EN,
328 0x40, (MICBIAS_NO_EXT_BYP_CAP << 6));
329 } else if (micbias2) {
330 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_EN,
331 0x40, (micbias2_cap_mode << 6));
332 } else if (micbias1) {
333 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_EN,
334 0x40, (micbias1_cap_mode << 6));
336 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_EN,
341 static int msm8x16_wcd_codec_probe(struct snd_soc_codec *codec)
343 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
346 snd_soc_codec_set_drvdata(codec, chip);
348 regulator_set_voltage(chip->vddio, 1800000, 1800000);
349 err = regulator_enable(chip->vddio);
351 dev_err(codec->dev, "failed to enable VDD regulator\n");
354 regulator_set_voltage(chip->vdd_pa, 1800000, 2200000);
355 err = regulator_enable(chip->vdd_pa);
357 dev_err(codec->dev, "failed to enable VDD regulator\n");
361 regulator_set_voltage(chip->vdd_mic_bias, 3075000, 3075000);
362 err = regulator_enable(chip->vdd_mic_bias);
364 dev_err(codec->dev, "failed to enable micbias regulator\n");
368 chip->pmic_rev = snd_soc_read(codec, MSM8X16_WCD_A_DIGITAL_REVISION1);
369 dev_info(codec->dev, "%s :PMIC REV: %d", __func__,
372 chip->codec_version = snd_soc_read(codec,
373 MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE);
374 dev_info(codec->dev, "%s :CODEC Version: %d", __func__,
375 chip->codec_version);
377 msm8x16_wcd_device_up(codec);
379 /* Set initial cap mode */
380 msm8x16_wcd_configure_cap(codec, false, false);
382 msm8x16_wcd_codec_enable_clock_block(codec, 1);
387 static int msm8x16_wcd_startup(struct snd_pcm_substream *substream,
388 struct snd_soc_dai *dai)
390 dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
392 substream->name, substream->stream);
396 static void msm8x16_wcd_shutdown(struct snd_pcm_substream *substream,
397 struct snd_soc_dai *dai)
399 dev_dbg(dai->codec->dev,
400 "%s(): substream = %s stream = %d\n", __func__,
401 substream->name, substream->stream);
404 static int msm8x16_wcd_set_interpolator_rate(struct snd_soc_dai *dai,
405 u8 rx_fs_rate_reg_val, u32 sample_rate)
410 static int msm8x16_wcd_set_decimator_rate(struct snd_soc_dai *dai,
411 u8 tx_fs_rate_reg_val, u32 sample_rate)
417 static int msm8x16_wcd_hw_params(struct snd_pcm_substream *substream,
418 struct snd_pcm_hw_params *params,
419 struct snd_soc_dai *dai)
421 u8 tx_fs_rate, rx_fs_rate;
424 dev_err(dai->codec->dev,
425 "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n",
426 __func__, dai->name, dai->id, params_rate(params),
427 params_channels(params), params_format(params));
429 switch (params_rate(params)) {
455 dev_err(dai->codec->dev,
456 "%s: Invalid sampling rate %d\n", __func__,
457 params_rate(params));
461 switch (substream->stream) {
462 case SNDRV_PCM_STREAM_CAPTURE:
463 snd_soc_update_bits(dai->codec,
464 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 0x07, tx_fs_rate);
465 ret = msm8x16_wcd_set_decimator_rate(dai, tx_fs_rate,
466 params_rate(params));
468 dev_err(dai->codec->dev,
469 "%s: set decimator rate failed %d\n", __func__,
474 case SNDRV_PCM_STREAM_PLAYBACK:
475 ret = msm8x16_wcd_set_interpolator_rate(dai, rx_fs_rate,
476 params_rate(params));
478 dev_err(dai->codec->dev,
479 "%s: set decimator rate failed %d\n", __func__,
485 dev_err(dai->codec->dev,
486 "%s: Invalid stream type %d\n", __func__,
491 switch (params_format(params)) {
492 case SNDRV_PCM_FORMAT_S16_LE:
493 snd_soc_update_bits(dai->codec,
494 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 0x20, 0x20);
495 snd_soc_update_bits(dai->codec,
496 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x20);
498 case SNDRV_PCM_FORMAT_S24_LE:
499 snd_soc_update_bits(dai->codec,
500 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 0x20, 0x00);
501 snd_soc_update_bits(dai->codec,
502 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x00);
505 dev_err(dai->dev, "%s: wrong format selected\n",
513 static int msm8x16_wcd_set_dai_sysclk(struct snd_soc_dai *dai,
514 int clk_id, unsigned int freq, int dir)
516 dev_dbg(dai->codec->dev, "%s\n", __func__);
520 static int msm8x16_wcd_set_channel_map(struct snd_soc_dai *dai,
521 unsigned int tx_num, unsigned int *tx_slot,
522 unsigned int rx_num, unsigned int *rx_slot)
525 dev_dbg(dai->codec->dev, "%s\n", __func__);
529 static int msm8x16_wcd_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
531 dev_dbg(dai->codec->dev, "%s\n", __func__);
536 static struct snd_soc_dai_ops msm8x16_wcd_dai_ops = {
537 .startup = msm8x16_wcd_startup,
538 .shutdown = msm8x16_wcd_shutdown,
539 .hw_params = msm8x16_wcd_hw_params,
540 .set_sysclk = msm8x16_wcd_set_dai_sysclk,
541 .set_fmt = msm8x16_wcd_set_dai_fmt,
542 .set_channel_map = msm8x16_wcd_set_channel_map,
545 static struct snd_soc_dai_driver msm8x16_wcd_codec_dai[] = {
547 .name = "msm8x16_wcd_i2s_rx1",
550 .stream_name = "AIF1 Playback",
551 .rates = MSM8X16_WCD_RATES,
552 .formats = MSM8X16_WCD_FORMATS,
558 .ops = &msm8x16_wcd_dai_ops,
561 .name = "msm8x16_wcd_i2s_tx1",
564 .stream_name = "AIF1 Capture",
565 .rates = MSM8X16_WCD_RATES,
566 .formats = MSM8X16_WCD_FORMATS,
572 .ops = &msm8x16_wcd_dai_ops,
576 static int msm8x16_wcd_codec_remove(struct snd_soc_codec *codec)
582 static int msm8x16_wcd_spk_boost_get(struct snd_kcontrol *kcontrol,
583 struct snd_ctl_elem_value *ucontrol)
585 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
586 struct wcd_chip *msm8x16_wcd = dev_get_drvdata(codec->dev);
588 if (msm8x16_wcd->spk_boost_set == false) {
589 ucontrol->value.integer.value[0] = 0;
590 } else if (msm8x16_wcd->spk_boost_set == true) {
591 ucontrol->value.integer.value[0] = 1;
593 dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n",
594 __func__, msm8x16_wcd->spk_boost_set);
598 dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n", __func__,
599 msm8x16_wcd->spk_boost_set);
603 static int msm8x16_wcd_spk_boost_set(struct snd_kcontrol *kcontrol,
604 struct snd_ctl_elem_value *ucontrol)
606 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
607 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
609 switch (ucontrol->value.integer.value[0]) {
611 msm8x16_wcd->spk_boost_set = false;
614 msm8x16_wcd->spk_boost_set = true;
619 dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n",
620 __func__, msm8x16_wcd->spk_boost_set);
624 static const char * const hph_text[] = {
628 static const struct soc_enum hph_enum =
629 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(hph_text), hph_text);
631 static const struct snd_kcontrol_new hphl_mux[] = {
632 SOC_DAPM_ENUM("HPHL", hph_enum)
635 static const struct snd_kcontrol_new hphr_mux[] = {
636 SOC_DAPM_ENUM("HPHR", hph_enum)
639 static const struct snd_kcontrol_new spkr_switch[] = {
640 SOC_DAPM_SINGLE("Switch",
641 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 7, 1, 0)
644 static void msm8x16_wcd_codec_enable_adc_block(struct snd_soc_codec *codec,
647 //struct msm8x16_wcd_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec);
649 dev_dbg(codec->dev, "%s %d\n", __func__, enable);
652 //wcd8x16->adc_count++;
653 snd_soc_update_bits(codec,
654 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL,
656 snd_soc_update_bits(codec,
657 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
660 //wcd8x16->adc_count--;
661 //if (!wcd8x16->adc_count) {
662 snd_soc_update_bits(codec,
663 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
665 snd_soc_update_bits(codec,
666 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL,
672 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
673 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
675 static const char * const rx_mix1_text[] = {
676 "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
679 static const char * const rx_mix2_text[] = {
680 "ZERO", "IIR1", "IIR2"
683 static const char * const dec_mux_text[] = {
684 "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
687 static const char * const adc2_mux_text[] = {
688 "ZERO", "INP2", "INP3"
691 static const char * const rdac2_mux_text[] = {
695 static const char * const iir_inp1_text[] = {
696 "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
699 static const char * const iir1_inp1_text[] = {
700 "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
703 static const struct soc_enum adc2_enum =
704 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
707 static const struct soc_enum rx_mix1_inp1_chain_enum =
708 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
711 static const struct soc_enum rx_mix1_inp2_chain_enum =
712 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
715 static const struct soc_enum rx_mix1_inp3_chain_enum =
716 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL,
719 static const struct soc_enum rx_mix2_inp1_chain_enum =
720 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL,
724 static const struct soc_enum rx2_mix1_inp1_chain_enum =
725 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
728 static const struct soc_enum rx2_mix1_inp2_chain_enum =
729 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
732 static const struct soc_enum rx2_mix1_inp3_chain_enum =
733 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
737 static const struct soc_enum rx2_mix2_inp1_chain_enum =
738 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL,
742 static const struct soc_enum rx3_mix1_inp1_chain_enum =
743 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
746 static const struct soc_enum rx3_mix1_inp2_chain_enum =
747 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
751 static const struct soc_enum dec1_mux_enum =
752 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL,
755 static const struct soc_enum dec2_mux_enum =
756 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL,
759 static const struct soc_enum rdac2_mux_enum =
760 SOC_ENUM_SINGLE(MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL,
761 0, 3, rdac2_mux_text);
763 static const struct soc_enum iir1_inp1_mux_enum =
764 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_EQ1_B1_CTL,
765 0, 6, iir_inp1_text);
767 static const struct soc_enum iir2_inp1_mux_enum =
768 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_EQ2_B1_CTL,
769 0, 6, iir_inp1_text);
770 static const struct snd_kcontrol_new iir2_inp1_mux =
771 SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
773 static const struct soc_enum rx3_mix1_inp3_chain_enum =
774 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
776 static const struct snd_kcontrol_new rx_mix1_inp1_mux =
777 SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
779 static const struct snd_kcontrol_new dec1_mux =
780 SOC_DAPM_ENUM("DEC1 MUX Mux", dec1_mux_enum);
782 static const struct snd_kcontrol_new dec2_mux =
783 SOC_DAPM_ENUM("DEC2 MUX Mux", dec2_mux_enum);
785 static const struct snd_kcontrol_new rdac2_mux =
786 SOC_DAPM_ENUM("RDAC2 MUX Mux", rdac2_mux_enum);
788 static const struct snd_kcontrol_new iir1_inp1_mux =
789 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
791 static const struct snd_kcontrol_new rx_mix1_inp2_mux =
792 SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
794 static const struct snd_kcontrol_new rx_mix1_inp3_mux =
795 SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
797 static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
798 SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
800 static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
801 SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
803 static const struct snd_kcontrol_new rx2_mix1_inp3_mux =
804 SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum);
806 static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
807 SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
809 static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
810 SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
812 static const struct snd_kcontrol_new rx3_mix1_inp3_mux =
813 SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum);
815 static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
816 SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
818 static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
819 SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
821 static const struct snd_kcontrol_new tx_adc2_mux =
822 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
824 static const char * const msm8x16_wcd_loopback_mode_ctrl_text[] = {
825 "DISABLE", "ENABLE"};
826 static const struct soc_enum msm8x16_wcd_loopback_mode_ctl_enum[] = {
827 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_loopback_mode_ctrl_text),
830 static int msm8x16_wcd_codec_enable_on_demand_supply(
831 struct snd_soc_dapm_widget *w,
832 struct snd_kcontrol *kcontrol, int event)
835 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
836 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
839 case SND_SOC_DAPM_PRE_PMU:
840 ret = regulator_enable(msm8x16_wcd->vdd_mic_bias);
842 dev_err(codec->dev, "%s: Failed to enable vdd micbias\n",
845 case SND_SOC_DAPM_POST_PMD:
846 ret = regulator_disable(msm8x16_wcd->vdd_mic_bias);
848 dev_err(codec->dev, "%s: Failed to disable vdd-micbias\n",
858 static const char * const msm8x16_wcd_ear_pa_boost_ctrl_text[] = {
859 "DISABLE", "ENABLE"};
860 static const struct soc_enum msm8x16_wcd_ear_pa_boost_ctl_enum[] = {
861 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_boost_ctrl_text),
864 static const char * const msm8x16_wcd_ear_pa_gain_text[] = {
865 "POS_6_DB", "POS_1P5_DB"};
866 static const struct soc_enum msm8x16_wcd_ear_pa_gain_enum[] = {
867 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_gain_text),
870 static const char * const msm8x16_wcd_spk_boost_ctrl_text[] = {
871 "DISABLE", "ENABLE"};
872 static const struct soc_enum msm8x16_wcd_spk_boost_ctl_enum[] = {
873 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_spk_boost_ctrl_text),
876 /*cut of frequency for high pass filter*/
877 static const char * const cf_text[] = {
878 "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
881 static const struct soc_enum cf_dec1_enum =
882 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
884 static const struct soc_enum cf_dec2_enum =
885 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
887 static const struct soc_enum cf_rxmix1_enum =
888 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX1_B4_CTL, 0, 3, cf_text);
890 static const struct soc_enum cf_rxmix2_enum =
891 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX2_B4_CTL, 0, 3, cf_text);
893 static const struct soc_enum cf_rxmix3_enum =
894 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX3_B4_CTL, 0, 3, cf_text);
896 static const struct snd_kcontrol_new msm8x16_wcd_snd_controls[] = {
898 SOC_ENUM_EXT("Speaker Boost", msm8x16_wcd_spk_boost_ctl_enum[0],
899 msm8x16_wcd_spk_boost_get, msm8x16_wcd_spk_boost_set),
901 SOC_SINGLE_TLV("ADC1 Volume", MSM8X16_WCD_A_ANALOG_TX_1_EN, 3,
903 SOC_SINGLE_TLV("ADC2 Volume", MSM8X16_WCD_A_ANALOG_TX_2_EN, 3,
905 SOC_SINGLE_TLV("ADC3 Volume", MSM8X16_WCD_A_ANALOG_TX_3_EN, 3,
908 SOC_SINGLE_SX_TLV("RX1 Digital Volume",
909 MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
910 0, -84, 40, digital_gain),
911 SOC_SINGLE_SX_TLV("RX2 Digital Volume",
912 MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
913 0, -84, 40, digital_gain),
914 SOC_SINGLE_SX_TLV("RX3 Digital Volume",
915 MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
916 0, -84, 40, digital_gain),
918 SOC_SINGLE("RX1 HPF Switch",
919 MSM8X16_WCD_A_CDC_RX1_B5_CTL, 2, 1, 0),
920 SOC_SINGLE("RX2 HPF Switch",
921 MSM8X16_WCD_A_CDC_RX2_B5_CTL, 2, 1, 0),
922 SOC_SINGLE("RX3 HPF Switch",
923 MSM8X16_WCD_A_CDC_RX3_B5_CTL, 2, 1, 0),
925 SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
926 SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
927 SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
930 static const struct snd_kcontrol_new ear_pa_switch[] = {
931 SOC_DAPM_SINGLE("Switch",
932 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 5, 1, 0)
935 static int msm8x16_wcd_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
936 struct snd_kcontrol *kcontrol, int event)
938 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
939 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
942 case SND_SOC_DAPM_PRE_PMU:
944 "%s: Sleeping 20ms after select EAR PA\n",
946 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
949 case SND_SOC_DAPM_POST_PMU:
951 "%s: Sleeping 20ms after enabling EAR PA\n",
953 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
955 usleep_range(7000, 7100);
956 snd_soc_update_bits(codec,
957 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
959 case SND_SOC_DAPM_PRE_PMD:
960 snd_soc_update_bits(codec,
961 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
963 msm8x16_wcd->mute_mask |= EAR_PA_DISABLE;
965 case SND_SOC_DAPM_POST_PMD:
967 "%s: Sleeping 7ms after disabling EAR PA\n",
969 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
971 usleep_range(7000, 7100);
973 * Reset pa select bit from ear to hph after ear pa
974 * is disabled to reduce ear turn off pop
976 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
983 static int msm8x16_wcd_codec_enable_adc(struct snd_soc_dapm_widget *w,
984 struct snd_kcontrol *kcontrol, int event)
986 //struct snd_soc_codec *codec = w->codec;
987 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
991 dev_dbg(codec->dev, "%s %d\n", __func__, event);
993 adc_reg = MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_2;
995 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_1_EN)
997 else if ((w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN) ||
998 (w->reg == MSM8X16_WCD_A_ANALOG_TX_3_EN))
1001 dev_err(codec->dev, "%s: Error, invalid adc register\n",
1007 case SND_SOC_DAPM_PRE_PMU:
1008 msm8x16_wcd_codec_enable_adc_block(codec, 1);
1009 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN)
1010 snd_soc_update_bits(codec,
1011 MSM8X16_WCD_A_ANALOG_MICB_1_CTL, 0x02, 0x02);
1013 * Add delay of 10 ms to give sufficient time for the voltage
1014 * to shoot up and settle so that the txfe init does not
1015 * happen when the input voltage is changing too much.
1017 usleep_range(10000, 10010);
1018 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
1019 1 << init_bit_shift);
1020 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_1_EN)
1021 snd_soc_update_bits(codec,
1022 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL,
1024 else if ((w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN) ||
1025 (w->reg == MSM8X16_WCD_A_ANALOG_TX_3_EN))
1026 snd_soc_update_bits(codec,
1027 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL,
1029 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1031 case SND_SOC_DAPM_POST_PMU:
1033 * Add delay of 12 ms before deasserting the init
1034 * to reduce the tx pop
1036 usleep_range(12000, 12010);
1037 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
1038 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1040 case SND_SOC_DAPM_POST_PMD:
1041 msm8x16_wcd_codec_enable_adc_block(codec, 0);
1042 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN)
1043 snd_soc_update_bits(codec,
1044 MSM8X16_WCD_A_ANALOG_MICB_1_CTL, 0x02, 0x00);
1045 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_1_EN)
1046 snd_soc_update_bits(codec,
1047 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL,
1049 else if ((w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN) ||
1050 (w->reg == MSM8X16_WCD_A_ANALOG_TX_3_EN))
1051 snd_soc_update_bits(codec,
1052 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL,
1060 static int msm8x16_wcd_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
1061 struct snd_kcontrol *kcontrol, int event)
1063 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1064 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1067 case SND_SOC_DAPM_PRE_PMU:
1068 snd_soc_update_bits(codec,
1069 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
1070 snd_soc_update_bits(codec,
1071 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01);
1072 if (!msm8x16_wcd->spk_boost_set)
1073 snd_soc_update_bits(codec,
1074 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x10);
1075 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1076 snd_soc_update_bits(codec,
1077 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0);
1078 if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
1079 snd_soc_update_bits(codec,
1080 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x01);
1082 case SND_SOC_DAPM_POST_PMU:
1083 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1084 if (msm8x16_wcd->spk_boost_set)
1085 snd_soc_update_bits(codec,
1086 MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0xEF);
1088 snd_soc_update_bits(codec,
1089 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
1090 snd_soc_update_bits(codec,
1091 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
1092 snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
1094 case SND_SOC_DAPM_PRE_PMD:
1095 snd_soc_update_bits(codec,
1096 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x01);
1098 msm8x16_wcd->mute_mask |= SPKR_PA_DISABLE;
1099 snd_soc_update_bits(codec, w->reg, 0x80, 0x00);
1100 if (msm8x16_wcd->spk_boost_set)
1101 snd_soc_update_bits(codec,
1102 MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0x00);
1104 snd_soc_update_bits(codec,
1105 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
1107 case SND_SOC_DAPM_POST_PMD:
1108 snd_soc_update_bits(codec,
1109 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0x00);
1110 if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
1111 snd_soc_update_bits(codec,
1112 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x00);
1113 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1114 snd_soc_update_bits(codec,
1115 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00);
1116 snd_soc_update_bits(codec,
1117 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
1123 static void msm8x16_wcd_micbias_2_enable(struct snd_soc_codec *codec, bool on)
1126 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_CTL,
1128 snd_soc_write(codec, MSM8X16_WCD_A_ANALOG_MICB_1_VAL,
1131 * Special headset needs MICBIAS as 2.7V so wait for
1132 * 50 msec for the MICBIAS to reach 2.7 volts.
1135 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_CTL,
1140 static s32 g_dmic_clk_cnt;
1141 static int msm8x16_wcd_codec_enable_dmic(struct snd_soc_dapm_widget *w,
1142 struct snd_kcontrol *kcontrol, int event)
1144 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1150 char *dec_num = strpbrk(w->name, "12");
1152 if (dec_num == NULL) {
1153 dev_err(codec->dev, "%s: Invalid DMIC\n", __func__);
1157 ret = kstrtouint(dec_num, 10, &dmic);
1160 "%s: Invalid DMIC line on the codec\n", __func__);
1168 dmic_clk_cnt = &g_dmic_clk_cnt;
1169 dmic_clk_reg = MSM8X16_WCD_A_CDC_CLK_DMIC_B1_CTL;
1171 "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n",
1172 __func__, event, dmic, *dmic_clk_cnt);
1175 dev_err(codec->dev, "%s: Invalid DMIC Selection\n", __func__);
1180 case SND_SOC_DAPM_PRE_PMU:
1182 if (*dmic_clk_cnt == 1) {
1183 snd_soc_update_bits(codec, dmic_clk_reg,
1185 snd_soc_update_bits(codec, dmic_clk_reg,
1186 dmic_clk_en, dmic_clk_en);
1189 snd_soc_update_bits(codec,
1190 MSM8X16_WCD_A_CDC_TX1_DMIC_CTL, 0x07, 0x01);
1192 snd_soc_update_bits(codec,
1193 MSM8X16_WCD_A_CDC_TX2_DMIC_CTL, 0x07, 0x01);
1195 case SND_SOC_DAPM_POST_PMD:
1197 if (*dmic_clk_cnt == 0)
1198 snd_soc_update_bits(codec, dmic_clk_reg,
1205 static int msm8x16_wcd_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1206 struct snd_kcontrol *kcontrol, int event)
1208 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1209 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1211 char *internal1_text = "Internal1";
1212 char *internal2_text = "Internal2";
1213 char *internal3_text = "Internal3";
1214 char *external2_text = "External2";
1215 char *external_text = "External";
1219 case MSM8X16_WCD_A_ANALOG_MICB_1_EN:
1220 case MSM8X16_WCD_A_ANALOG_MICB_2_EN:
1221 micb_int_reg = MSM8X16_WCD_A_ANALOG_MICB_1_INT_RBIAS;
1225 "%s: Error, invalid micbias register 0x%x\n",
1230 micbias2 = (snd_soc_read(codec, MSM8X16_WCD_A_ANALOG_MICB_2_EN) & 0x80);
1233 case SND_SOC_DAPM_PRE_PMU:
1234 if (strnstr(w->name, internal1_text, 30)) {
1235 snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x80);
1236 } else if (strnstr(w->name, internal2_text, 30)) {
1237 snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x10);
1238 snd_soc_update_bits(codec, w->reg, 0x60, 0x00);
1239 } else if (strnstr(w->name, internal3_text, 30)) {
1240 snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x2);
1242 if (!strnstr(w->name, external_text, 30))
1243 snd_soc_update_bits(codec,
1244 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 0x05, 0x04);
1245 if (w->reg == MSM8X16_WCD_A_ANALOG_MICB_1_EN)
1246 msm8x16_wcd_configure_cap(codec, true, micbias2);
1249 case SND_SOC_DAPM_POST_PMU:
1250 usleep_range(20000, 20100);
1251 if (strnstr(w->name, internal1_text, 30)) {
1252 snd_soc_update_bits(codec, micb_int_reg, 0x40, 0x40);
1253 } else if (strnstr(w->name, internal2_text, 30)) {
1254 snd_soc_update_bits(codec, micb_int_reg, 0x08, 0x08);
1255 msm8x16_wcd_micbias_2_enable(codec, true);
1257 msm8x16_wcd_configure_cap(codec, false, true);
1258 regmap_write(msm8x16_wcd->analog_map, 0xf144, 0x95);
1259 } else if (strnstr(w->name, internal3_text, 30)) {
1260 snd_soc_update_bits(codec, micb_int_reg, 0x01, 0x01);
1261 } else if (strnstr(w->name, external2_text, 30)) {
1262 msm8x16_wcd_micbias_2_enable(codec, true);
1265 case SND_SOC_DAPM_POST_PMD:
1266 if (strnstr(w->name, internal1_text, 30)) {
1267 snd_soc_update_bits(codec, micb_int_reg, 0xC0, 0x40);
1268 } else if (strnstr(w->name, internal2_text, 30)) {
1269 msm8x16_wcd_micbias_2_enable(codec, false);
1270 } else if (strnstr(w->name, internal3_text, 30)) {
1271 snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
1272 } else if (strnstr(w->name, external2_text, 30)) {
1274 * send micbias turn off event to mbhc driver and then
1275 * break, as no need to set MICB_1_EN register.
1277 msm8x16_wcd_micbias_2_enable(codec, false);
1280 if (w->reg == MSM8X16_WCD_A_ANALOG_MICB_1_EN)
1281 msm8x16_wcd_configure_cap(codec, false, micbias2);
1288 #define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30
1289 #define CF_MIN_3DB_4HZ 0x0
1290 #define CF_MIN_3DB_75HZ 0x1
1291 #define CF_MIN_3DB_150HZ 0x2
1293 static int msm8x16_wcd_codec_enable_dec(struct snd_soc_dapm_widget *w,
1294 struct snd_kcontrol *kcontrol, int event)
1296 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1297 unsigned int decimator;
1298 char *dec_name = NULL;
1299 char *widget_name = NULL;
1302 u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
1303 u8 dec_hpf_cut_of_freq;
1306 dev_dbg(codec->dev, "%s %d\n", __func__, event);
1308 widget_name = kstrndup(w->name, 15, GFP_KERNEL);
1313 dec_name = strsep(&widget_name, " ");
1317 "%s: Invalid decimator = %s\n", __func__, w->name);
1322 dec_num = strpbrk(dec_name, "12");
1323 if (dec_num == NULL) {
1324 dev_err(codec->dev, "%s: Invalid Decimator\n", __func__);
1329 ret = kstrtouint(dec_num, 10, &decimator);
1332 "%s: Invalid decimator = %s\n", __func__, dec_name);
1338 "%s(): widget = %s dec_name = %s decimator = %u\n", __func__,
1339 w->name, dec_name, decimator);
1341 if (w->reg == MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL) {
1342 dec_reset_reg = MSM8X16_WCD_A_CDC_CLK_TX_RESET_B1_CTL;
1345 dev_err(codec->dev, "%s: Error, incorrect dec\n", __func__);
1350 tx_vol_ctl_reg = MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG +
1351 32 * (decimator - 1);
1352 tx_mux_ctl_reg = MSM8X16_WCD_A_CDC_TX1_MUX_CTL +
1353 32 * (decimator - 1);
1356 case SND_SOC_DAPM_PRE_PMU:
1357 /* Enableable TX digital mute */
1358 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
1359 dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg);
1360 dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4;
1361 if ((dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ)) {
1363 /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */
1364 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
1365 CF_MIN_3DB_150HZ << 4);
1367 snd_soc_update_bits(codec,
1368 MSM8X16_WCD_A_ANALOG_TX_1_2_TXFE_CLKDIV,
1372 case SND_SOC_DAPM_POST_PMU:
1374 snd_soc_update_bits(codec, tx_mux_ctl_reg , 0x08, 0x00);
1375 /* apply the digital gain after the decimator is enabled*/
1376 if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg))
1377 snd_soc_write(codec,
1378 tx_digital_gain_reg[w->shift + offset],
1380 tx_digital_gain_reg[w->shift + offset])
1382 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
1384 case SND_SOC_DAPM_PRE_PMD:
1385 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
1387 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
1389 case SND_SOC_DAPM_POST_PMD:
1390 snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
1392 snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
1393 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
1394 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
1403 static int msm8x16_wcd_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
1404 struct snd_kcontrol *kcontrol,
1407 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1408 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1411 case SND_SOC_DAPM_POST_PMU:
1412 /* apply the digital gain after the interpolator is enabled*/
1413 if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
1414 snd_soc_write(codec,
1415 rx_digital_gain_reg[w->shift],
1417 rx_digital_gain_reg[w->shift])
1420 case SND_SOC_DAPM_POST_PMD:
1421 snd_soc_update_bits(codec,
1422 MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
1423 1 << w->shift, 1 << w->shift);
1424 snd_soc_update_bits(codec,
1425 MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
1426 1 << w->shift, 0x0);
1428 * disable the mute enabled during the PMD of this device
1430 if (msm8x16_wcd->mute_mask & HPHL_PA_DISABLE) {
1431 pr_debug("disabling HPHL mute\n");
1432 snd_soc_update_bits(codec,
1433 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1434 msm8x16_wcd->mute_mask &= ~(HPHL_PA_DISABLE);
1436 if (msm8x16_wcd->mute_mask & HPHR_PA_DISABLE) {
1437 pr_debug("disabling HPHR mute\n");
1438 snd_soc_update_bits(codec,
1439 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
1440 msm8x16_wcd->mute_mask &= ~(HPHR_PA_DISABLE);
1442 if (msm8x16_wcd->mute_mask & SPKR_PA_DISABLE) {
1443 pr_debug("disabling SPKR mute\n");
1444 snd_soc_update_bits(codec,
1445 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
1446 msm8x16_wcd->mute_mask &= ~(SPKR_PA_DISABLE);
1448 if (msm8x16_wcd->mute_mask & EAR_PA_DISABLE) {
1449 pr_debug("disabling EAR mute\n");
1450 snd_soc_update_bits(codec,
1451 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1452 msm8x16_wcd->mute_mask &= ~(EAR_PA_DISABLE);
1458 static int msm8x16_wcd_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
1459 struct snd_kcontrol *kcontrol, int event)
1461 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1462 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1465 case SND_SOC_DAPM_PRE_PMU:
1467 snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
1468 if (msm8x16_wcd->spk_boost_set) {
1469 snd_soc_update_bits(codec,
1470 MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
1472 snd_soc_update_bits(codec,
1473 MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
1475 snd_soc_update_bits(codec,
1476 MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
1478 snd_soc_update_bits(codec,
1479 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1481 snd_soc_update_bits(codec,
1482 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1484 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1485 snd_soc_update_bits(codec,
1486 MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
1488 } else if (msm8x16_wcd->ear_pa_boost_set) {
1489 snd_soc_update_bits(codec,
1490 MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
1492 snd_soc_update_bits(codec,
1493 MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
1495 snd_soc_update_bits(codec,
1496 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1498 snd_soc_update_bits(codec,
1499 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1501 snd_soc_update_bits(codec,
1502 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1504 snd_soc_update_bits(codec,
1505 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1508 snd_soc_update_bits(codec, w->reg, 1<<w->shift,
1512 case SND_SOC_DAPM_POST_PMD:
1513 if (msm8x16_wcd->spk_boost_set) {
1514 snd_soc_update_bits(codec,
1515 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1517 snd_soc_update_bits(codec,
1518 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1520 } else if (msm8x16_wcd->ear_pa_boost_set) {
1521 snd_soc_update_bits(codec,
1522 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1524 snd_soc_update_bits(codec,
1525 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1527 snd_soc_update_bits(codec,
1528 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1530 snd_soc_update_bits(codec,
1531 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1534 snd_soc_update_bits(codec, w->reg, 1<<w->shift, 0x00);
1541 static int msm8x16_wcd_codec_enable_rx_chain(struct snd_soc_dapm_widget *w,
1542 struct snd_kcontrol *kcontrol, int event)
1544 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1547 case SND_SOC_DAPM_POST_PMU:
1548 snd_soc_update_bits(codec,
1549 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1552 "%s: PMU:Sleeping 20ms after disabling mute\n",
1555 case SND_SOC_DAPM_POST_PMD:
1556 snd_soc_update_bits(codec,
1557 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1560 "%s: PMD:Sleeping 20ms after disabling mute\n",
1562 snd_soc_update_bits(codec, w->reg,
1563 1 << w->shift, 0x00);
1570 static int msm8x16_wcd_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
1571 struct snd_kcontrol *kcontrol, int event)
1573 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1574 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1577 case SND_SOC_DAPM_PRE_PMU:
1578 msm8x16_wcd->rx_bias_count++;
1579 if (msm8x16_wcd->rx_bias_count == 1)
1580 snd_soc_update_bits(codec,
1581 MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
1584 case SND_SOC_DAPM_POST_PMD:
1585 msm8x16_wcd->rx_bias_count--;
1586 if (msm8x16_wcd->rx_bias_count == 0)
1587 snd_soc_update_bits(codec,
1588 MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
1592 dev_dbg(codec->dev, "%s rx_bias_count = %d\n",
1593 __func__, msm8x16_wcd->rx_bias_count);
1597 static int msm8x16_wcd_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
1598 struct snd_kcontrol *kcontrol, int event)
1600 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1601 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1604 case SND_SOC_DAPM_PRE_PMU:
1605 if (!(strcmp(w->name, "EAR CP")))
1606 snd_soc_update_bits(codec,
1607 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1610 snd_soc_update_bits(codec,
1611 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1614 case SND_SOC_DAPM_POST_PMU:
1615 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1617 case SND_SOC_DAPM_POST_PMD:
1618 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1619 if (!(strcmp(w->name, "EAR CP")))
1620 snd_soc_update_bits(codec,
1621 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1624 snd_soc_update_bits(codec,
1625 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1627 if (msm8x16_wcd->rx_bias_count == 0)
1628 snd_soc_update_bits(codec,
1629 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1631 dev_dbg(codec->dev, "%s: rx_bias_count = %d\n",
1632 __func__, msm8x16_wcd->rx_bias_count);
1639 static int msm8x16_wcd_hphl_dac_event(struct snd_soc_dapm_widget *w,
1640 struct snd_kcontrol *kcontrol, int event)
1642 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1645 case SND_SOC_DAPM_PRE_PMU:
1646 snd_soc_update_bits(codec,
1647 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02);
1648 snd_soc_update_bits(codec,
1649 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
1650 snd_soc_update_bits(codec,
1651 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
1653 case SND_SOC_DAPM_POST_PMU:
1654 snd_soc_update_bits(codec,
1655 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x00);
1657 case SND_SOC_DAPM_POST_PMD:
1658 snd_soc_update_bits(codec,
1659 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
1660 snd_soc_update_bits(codec,
1661 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
1667 static int msm8x16_wcd_hph_pa_event(struct snd_soc_dapm_widget *w,
1668 struct snd_kcontrol *kcontrol, int event)
1670 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1671 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1674 case SND_SOC_DAPM_PRE_PMU:
1675 if (w->shift == 5) {
1676 snd_soc_update_bits(codec,
1677 MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x04);
1678 } else if (w->shift == 4) {
1679 snd_soc_update_bits(codec,
1680 MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x04);
1682 snd_soc_update_bits(codec,
1683 MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x20, 0x20);
1686 case SND_SOC_DAPM_POST_PMU:
1687 usleep_range(4000, 4100);
1689 snd_soc_update_bits(codec,
1690 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1691 else if (w->shift == 4)
1692 snd_soc_update_bits(codec,
1693 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
1694 usleep_range(10000, 10100);
1697 case SND_SOC_DAPM_PRE_PMD:
1698 if (w->shift == 5) {
1699 snd_soc_update_bits(codec,
1700 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
1702 msm8x16_wcd->mute_mask |= HPHL_PA_DISABLE;
1703 } else if (w->shift == 4) {
1704 snd_soc_update_bits(codec,
1705 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x01);
1707 msm8x16_wcd->mute_mask |= HPHR_PA_DISABLE;
1710 case SND_SOC_DAPM_POST_PMD:
1711 if (w->shift == 5) {
1712 snd_soc_update_bits(codec,
1713 MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x00);
1715 } else if (w->shift == 4) {
1716 snd_soc_update_bits(codec,
1717 MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x00);
1719 usleep_range(4000, 4100);
1721 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1722 snd_soc_update_bits(codec,
1723 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
1725 "%s: sleep 10 ms after %s PA disable.\n", __func__,
1727 usleep_range(10000, 10100);
1733 static const struct snd_soc_dapm_route audio_map[] = {
1734 {"RX_I2S_CLK", NULL, "CDC_CONN"},
1735 {"I2S RX1", NULL, "RX_I2S_CLK"},
1736 {"I2S RX2", NULL, "RX_I2S_CLK"},
1737 {"I2S RX3", NULL, "RX_I2S_CLK"},
1739 {"I2S TX1", NULL, "TX_I2S_CLK"},
1740 {"I2S TX2", NULL, "TX_I2S_CLK"},
1742 {"I2S TX1", NULL, "DEC1 MUX"},
1743 {"I2S TX2", NULL, "DEC2 MUX"},
1745 /* RDAC Connections */
1746 {"HPHR DAC", NULL, "RDAC2 MUX"},
1747 {"RDAC2 MUX", "RX1", "RX1 CHAIN"},
1748 {"RDAC2 MUX", "RX2", "RX2 CHAIN"},
1750 /* Earpiece (RX MIX1) */
1751 {"EAR", NULL, "EAR_S"},
1752 {"EAR_S", "Switch", "EAR PA"},
1753 {"EAR PA", NULL, "RX_BIAS"},
1754 {"EAR PA", NULL, "HPHL DAC"},
1755 {"EAR PA", NULL, "HPHR DAC"},
1756 {"EAR PA", NULL, "EAR CP"},
1758 /* Headset (RX MIX1 and RX MIX2) */
1759 {"HEADPHONE", NULL, "HPHL PA"},
1760 {"HEADPHONE", NULL, "HPHR PA"},
1762 {"HPHL PA", NULL, "HPHL"},
1763 {"HPHR PA", NULL, "HPHR"},
1764 {"HPHL", "Switch", "HPHL DAC"},
1765 {"HPHR", "Switch", "HPHR DAC"},
1766 {"HPHL PA", NULL, "CP"},
1767 {"HPHL PA", NULL, "RX_BIAS"},
1768 {"HPHR PA", NULL, "CP"},
1769 {"HPHR PA", NULL, "RX_BIAS"},
1770 {"HPHL DAC", NULL, "RX1 CHAIN"},
1772 {"SPK_OUT", NULL, "SPK PA"},
1773 {"SPK PA", NULL, "SPK_RX_BIAS"},
1774 {"SPK PA", NULL, "SPK DAC"},
1775 {"SPK DAC", "Switch", "RX3 CHAIN"},
1776 {"SPK DAC", NULL, "VDD_SPKDRV"},
1778 {"RX1 CHAIN", NULL, "RX1 CLK"},
1779 {"RX2 CHAIN", NULL, "RX2 CLK"},
1780 {"RX3 CHAIN", NULL, "RX3 CLK"},
1781 {"RX1 CHAIN", NULL, "RX1 MIX2"},
1782 {"RX2 CHAIN", NULL, "RX2 MIX2"},
1783 {"RX3 CHAIN", NULL, "RX3 MIX1"},
1785 {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
1786 {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
1787 {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
1788 {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
1789 {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
1790 {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
1791 {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
1792 {"RX1 MIX2", NULL, "RX1 MIX1"},
1793 {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
1794 {"RX2 MIX2", NULL, "RX2 MIX1"},
1795 {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
1797 {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
1798 {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
1799 {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
1800 {"RX1 MIX1 INP1", "IIR1", "IIR1"},
1801 {"RX1 MIX1 INP1", "IIR2", "IIR2"},
1802 {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
1803 {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
1804 {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
1805 {"RX1 MIX1 INP2", "IIR1", "IIR1"},
1806 {"RX1 MIX1 INP2", "IIR2", "IIR2"},
1807 {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
1808 {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
1809 {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
1811 {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
1812 {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
1813 {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
1814 {"RX2 MIX1 INP1", "IIR1", "IIR1"},
1815 {"RX2 MIX1 INP1", "IIR2", "IIR2"},
1816 {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
1817 {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
1818 {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
1819 {"RX2 MIX1 INP2", "IIR1", "IIR1"},
1820 {"RX2 MIX1 INP2", "IIR2", "IIR2"},
1822 {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
1823 {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
1824 {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
1825 {"RX3 MIX1 INP1", "IIR1", "IIR1"},
1826 {"RX3 MIX1 INP1", "IIR2", "IIR2"},
1827 {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
1828 {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
1829 {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
1830 {"RX3 MIX1 INP2", "IIR1", "IIR1"},
1831 {"RX3 MIX1 INP2", "IIR2", "IIR2"},
1833 {"RX1 MIX2 INP1", "IIR1", "IIR1"},
1834 {"RX2 MIX2 INP1", "IIR1", "IIR1"},
1835 {"RX1 MIX2 INP1", "IIR2", "IIR2"},
1836 {"RX2 MIX2 INP1", "IIR2", "IIR2"},
1838 /* Decimator Inputs */
1839 {"DEC1 MUX", "DMIC1", "DMIC1"},
1840 {"DEC1 MUX", "DMIC2", "DMIC2"},
1841 {"DEC1 MUX", "ADC1", "ADC1"},
1842 {"DEC1 MUX", "ADC2", "ADC2"},
1843 {"DEC1 MUX", "ADC3", "ADC3"},
1844 {"DEC1 MUX", NULL, "CDC_CONN"},
1846 {"DEC2 MUX", "DMIC1", "DMIC1"},
1847 {"DEC2 MUX", "DMIC2", "DMIC2"},
1848 {"DEC2 MUX", "ADC1", "ADC1"},
1849 {"DEC2 MUX", "ADC2", "ADC2"},
1850 {"DEC2 MUX", "ADC3", "ADC3"},
1851 {"DEC2 MUX", NULL, "CDC_CONN"},
1853 /* ADC Connections */
1854 {"ADC2", NULL, "ADC2 MUX"},
1855 {"ADC3", NULL, "ADC2 MUX"},
1856 {"ADC2 MUX", "INP2", "ADC2_INP2"},
1857 {"ADC2 MUX", "INP3", "ADC2_INP3"},
1859 {"ADC1", NULL, "AMIC1"},
1860 {"ADC2_INP2", NULL, "AMIC2"},
1861 {"ADC2_INP3", NULL, "AMIC3"},
1863 /* TODO: Fix this */
1864 {"IIR1", NULL, "IIR1 INP1 MUX"},
1865 {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
1866 {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
1867 {"IIR2", NULL, "IIR2 INP1 MUX"},
1868 {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
1869 {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
1870 {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
1871 {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
1872 {"MIC BIAS External", NULL, "INT_LDO_H"},
1873 {"MIC BIAS External2", NULL, "INT_LDO_H"},
1874 {"MIC BIAS Internal1", NULL, "MICBIAS_REGULATOR"},
1875 {"MIC BIAS Internal2", NULL, "MICBIAS_REGULATOR"},
1876 {"MIC BIAS External", NULL, "MICBIAS_REGULATOR"},
1877 {"MIC BIAS External2", NULL, "MICBIAS_REGULATOR"},
1880 static int msm8x16_wcd_hphr_dac_event(struct snd_soc_dapm_widget *w,
1881 struct snd_kcontrol *kcontrol, int event)
1883 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1886 case SND_SOC_DAPM_PRE_PMU:
1887 snd_soc_update_bits(codec,
1888 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02);
1889 snd_soc_update_bits(codec,
1890 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
1891 snd_soc_update_bits(codec,
1892 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
1894 case SND_SOC_DAPM_POST_PMU:
1895 snd_soc_update_bits(codec,
1896 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x00);
1898 case SND_SOC_DAPM_POST_PMD:
1899 snd_soc_update_bits(codec,
1900 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
1901 snd_soc_update_bits(codec,
1902 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00);
1908 static const struct snd_soc_dapm_widget msm8x16_wcd_dapm_widgets[] = {
1910 SND_SOC_DAPM_OUTPUT("EAR"),
1912 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
1913 0, 0, NULL, 0, msm8x16_wcd_codec_enable_ear_pa,
1914 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1915 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1916 SND_SOC_DAPM_MIXER("EAR_S", SND_SOC_NOPM, 0, 0,
1917 ear_pa_switch, ARRAY_SIZE(ear_pa_switch)),
1919 SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1921 SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1923 SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1925 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
1927 SND_SOC_DAPM_OUTPUT("HEADPHONE"),
1928 SND_SOC_DAPM_PGA_E("HPHL PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
1930 msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
1931 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
1932 SND_SOC_DAPM_POST_PMD),
1934 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, hphl_mux),
1936 SND_SOC_DAPM_MIXER_E("HPHL DAC",
1937 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
1938 0, msm8x16_wcd_hphl_dac_event,
1939 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1940 SND_SOC_DAPM_POST_PMD),
1942 SND_SOC_DAPM_PGA_E("HPHR PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
1944 msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
1945 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
1946 SND_SOC_DAPM_POST_PMD),
1947 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, hphr_mux),
1949 SND_SOC_DAPM_MIXER_E("HPHR DAC",
1950 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
1951 0, msm8x16_wcd_hphr_dac_event,
1952 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1953 SND_SOC_DAPM_POST_PMD),
1955 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
1956 spkr_switch, ARRAY_SIZE(spkr_switch)),
1959 SND_SOC_DAPM_OUTPUT("SPK_OUT"),
1961 SND_SOC_DAPM_PGA_E("SPK PA", MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL,
1962 6, 0, NULL, 0, msm8x16_wcd_codec_enable_spk_pa,
1963 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1964 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1966 SND_SOC_DAPM_MIXER_E("RX1 MIX1",
1967 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL, 0,
1968 msm8x16_wcd_codec_enable_interpolator,
1969 SND_SOC_DAPM_PRE_REG|
1970 SND_SOC_DAPM_POST_PMU |
1971 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD|
1972 SND_SOC_DAPM_POST_PMD),
1974 SND_SOC_DAPM_MIXER_E("RX2 MIX1",
1975 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL, 0,
1976 msm8x16_wcd_codec_enable_interpolator,
1977 SND_SOC_DAPM_PRE_REG|
1978 SND_SOC_DAPM_POST_PMU |
1979 SND_SOC_DAPM_POST_PMD),
1981 SND_SOC_DAPM_MIXER_E("RX1 MIX2",
1982 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
1983 0, msm8x16_wcd_codec_enable_interpolator,
1984 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1985 SND_SOC_DAPM_MIXER_E("RX2 MIX2",
1986 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
1987 0, msm8x16_wcd_codec_enable_interpolator,
1988 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1989 SND_SOC_DAPM_MIXER_E("RX3 MIX1",
1990 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
1991 0, msm8x16_wcd_codec_enable_interpolator,
1992 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1994 SND_SOC_DAPM_SUPPLY("RX1 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1996 SND_SOC_DAPM_SUPPLY("RX2 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1998 SND_SOC_DAPM_SUPPLY("RX3 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1999 2, 0, msm8x16_wcd_codec_enable_dig_clk, SND_SOC_DAPM_PRE_PMU |
2000 SND_SOC_DAPM_POST_PMD),
2001 SND_SOC_DAPM_MIXER_E("RX1 CHAIN", MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0, 0,
2003 msm8x16_wcd_codec_enable_rx_chain,
2004 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2005 SND_SOC_DAPM_MIXER_E("RX2 CHAIN", MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0, 0,
2007 msm8x16_wcd_codec_enable_rx_chain,
2008 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2009 SND_SOC_DAPM_MIXER_E("RX3 CHAIN", MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0, 0,
2011 msm8x16_wcd_codec_enable_rx_chain,
2012 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2014 SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
2016 SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
2018 SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
2021 SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
2022 &rx2_mix1_inp1_mux),
2023 SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
2024 &rx2_mix1_inp2_mux),
2025 SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
2026 &rx2_mix1_inp3_mux),
2028 SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
2029 &rx3_mix1_inp1_mux),
2030 SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
2031 &rx3_mix1_inp2_mux),
2032 SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
2033 &rx3_mix1_inp3_mux),
2035 SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
2036 &rx1_mix2_inp1_mux),
2037 SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
2038 &rx2_mix2_inp1_mux),
2040 SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM,
2041 ON_DEMAND_MICBIAS, 0,
2042 msm8x16_wcd_codec_enable_on_demand_supply,
2043 SND_SOC_DAPM_PRE_PMU |
2044 SND_SOC_DAPM_POST_PMD),
2046 SND_SOC_DAPM_SUPPLY("CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 0, 0,
2047 msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
2048 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2050 SND_SOC_DAPM_SUPPLY("EAR CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 4, 0,
2051 msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
2052 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2054 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM,
2055 0, 0, msm8x16_wcd_codec_enable_rx_bias,
2056 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2058 SND_SOC_DAPM_SUPPLY("SPK_RX_BIAS", SND_SOC_NOPM, 0, 0,
2059 msm8x16_wcd_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
2060 SND_SOC_DAPM_POST_PMD),
2064 SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, MSM8X16_WCD_A_CDC_CLK_OTHR_CTL,
2067 SND_SOC_DAPM_INPUT("AMIC1"),
2068 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1",
2069 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 7, 0,
2070 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2071 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2072 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2",
2073 MSM8X16_WCD_A_ANALOG_MICB_2_EN, 7, 0,
2074 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2075 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2076 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3",
2077 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 7, 0,
2078 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2079 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2080 SND_SOC_DAPM_ADC_E("ADC1", NULL, MSM8X16_WCD_A_ANALOG_TX_1_EN, 7, 0,
2081 msm8x16_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
2082 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2083 SND_SOC_DAPM_ADC_E("ADC2_INP2",
2084 NULL, MSM8X16_WCD_A_ANALOG_TX_2_EN, 7, 0,
2085 msm8x16_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
2086 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2087 SND_SOC_DAPM_ADC_E("ADC2_INP3",
2088 NULL, MSM8X16_WCD_A_ANALOG_TX_3_EN, 7, 0,
2089 msm8x16_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
2090 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2092 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2093 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2095 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
2098 SND_SOC_DAPM_SUPPLY("MIC BIAS External",
2099 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 7, 0,
2100 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2101 SND_SOC_DAPM_POST_PMD),
2103 SND_SOC_DAPM_SUPPLY("MIC BIAS External2",
2104 MSM8X16_WCD_A_ANALOG_MICB_2_EN, 7, 0,
2105 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_POST_PMU |
2106 SND_SOC_DAPM_POST_PMD),
2109 SND_SOC_DAPM_INPUT("AMIC3"),
2111 SND_SOC_DAPM_MUX_E("DEC1 MUX",
2112 MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
2113 &dec1_mux, msm8x16_wcd_codec_enable_dec,
2114 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2115 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2117 SND_SOC_DAPM_MUX_E("DEC2 MUX",
2118 MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
2119 &dec2_mux, msm8x16_wcd_codec_enable_dec,
2120 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2121 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2123 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
2125 SND_SOC_DAPM_INPUT("AMIC2"),
2127 SND_SOC_DAPM_AIF_OUT("I2S TX1", "AIF1 Capture", 0, SND_SOC_NOPM,
2129 SND_SOC_DAPM_AIF_OUT("I2S TX2", "AIF1 Capture", 0, SND_SOC_NOPM,
2131 SND_SOC_DAPM_AIF_OUT("I2S TX3", "AIF1 Capture", 0, SND_SOC_NOPM,
2135 /* Digital Mic Inputs */
2136 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2137 msm8x16_wcd_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
2138 SND_SOC_DAPM_POST_PMD),
2140 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
2141 msm8x16_wcd_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
2142 SND_SOC_DAPM_POST_PMD),
2145 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
2146 SND_SOC_DAPM_PGA("IIR1",
2147 MSM8X16_WCD_A_CDC_CLK_SD_CTL, 0, 0, NULL, 0),
2149 SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
2150 SND_SOC_DAPM_PGA("IIR2",
2151 MSM8X16_WCD_A_CDC_CLK_SD_CTL, 1, 0, NULL, 0),
2153 SND_SOC_DAPM_SUPPLY("RX_I2S_CLK",
2154 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 4, 0, NULL, 0),
2155 SND_SOC_DAPM_SUPPLY("TX_I2S_CLK",
2156 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 4, 0,
2160 static struct snd_soc_codec_driver msm8x16_wcd_codec = {
2161 .probe = msm8x16_wcd_codec_probe,
2162 .remove = msm8x16_wcd_codec_remove,
2163 .read = msm8x16_wcd_read,
2164 .write = msm8x16_wcd_write,
2165 .reg_cache_size = MSM8X16_WCD_CACHE_SIZE,
2166 .reg_cache_default = msm8x16_wcd_reset_reg_defaults,
2168 .controls = msm8x16_wcd_snd_controls,
2169 .num_controls = ARRAY_SIZE(msm8x16_wcd_snd_controls),
2170 .dapm_widgets = msm8x16_wcd_dapm_widgets,
2171 .num_dapm_widgets = ARRAY_SIZE(msm8x16_wcd_dapm_widgets),
2172 .dapm_routes = audio_map,
2173 .num_dapm_routes = ARRAY_SIZE(audio_map),
2176 static int msm8x16_wcd_codec_parse_dt(struct platform_device *pdev,
2177 struct wcd_chip *chip)
2179 struct device *dev = &pdev->dev;
2180 struct device_node *np = dev->of_node;
2184 ret = of_property_read_u32_array(np, "reg", res, 2);
2188 chip->analog_base = res[0];
2190 chip->digital_map = syscon_regmap_lookup_by_phandle(np, "digital");
2191 if (IS_ERR(chip->digital_map))
2192 return PTR_ERR(chip->digital_map);
2194 chip->vddio = devm_regulator_get(dev, "vddio");
2195 if (IS_ERR(chip->vddio)) {
2196 dev_err(dev, "Failed to get vdd supply\n");
2197 return PTR_ERR(chip->vddio);
2200 chip->vdd_pa = devm_regulator_get(dev, "vdd-pa");
2201 if (IS_ERR(chip->vdd_pa)) {
2202 dev_err(dev, "Failed to get vdd supply\n");
2203 return PTR_ERR(chip->vdd_pa);
2206 chip->vdd_mic_bias = devm_regulator_get(dev, "vdd-mic-bias");
2207 if (IS_ERR(chip->vdd_mic_bias)) {
2208 dev_err(dev, "Failed to get vdd micbias supply\n");
2209 return PTR_ERR(chip->vdd_mic_bias);
2212 chip->mclk = devm_clk_get(dev, "mclk");
2217 static int wcd_probe(struct platform_device *pdev)
2219 struct wcd_chip *chip;
2220 struct device *dev = &pdev->dev;
2223 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
2227 chip->analog_map = dev_get_regmap(dev->parent, NULL);
2228 if (!chip->analog_map)
2231 ret = msm8x16_wcd_codec_parse_dt(pdev, chip);
2232 if (IS_ERR_VALUE(ret))
2235 clk_set_rate(chip->mclk, 9600000);
2236 clk_prepare_enable(chip->mclk);
2238 dev_set_drvdata(dev, chip);
2240 return snd_soc_register_codec(dev, &msm8x16_wcd_codec,
2241 msm8x16_wcd_codec_dai,
2242 ARRAY_SIZE(msm8x16_wcd_codec_dai));
2245 static int wcd_remove(struct platform_device *pdev)
2247 snd_soc_unregister_codec(&pdev->dev);
2252 static const struct of_device_id wcd_match_table[] = {
2253 { .compatible = "qcom,apq8016-wcd-codec" },
2254 { .compatible = "qcom,msm8x16-wcd-codec" },
2257 MODULE_DEVICE_TABLE(of, wcd_match_table);
2259 static struct platform_driver wcd_driver = {
2261 .name = "msm8x16-wcd-codec",
2262 .of_match_table = wcd_match_table,
2265 .remove = wcd_remove,
2267 module_platform_driver(wcd_driver);
2269 MODULE_ALIAS("platform:spmi-wcd-codec");
2270 MODULE_DESCRIPTION("SPMI PMIC WCD codec driver");
2271 MODULE_LICENSE("GPL v2");