irqchip: mips-cpu: Prepare for non-legacy IRQ domains

The various struct irq_chip callbacks in the MIPS CPU interrupt
controller driver have been calculating the hardware interrupt number by
subtracting MIPS_CPU_IRQ_BASE from the virq number. This presumes a
linear mapping beginning from MIPS_CPU_IRQ_BASE, and this will not hold
once an IPI IRQ domain is introduced. Switch to using the hwirq field of
struct irq_data which already contains the hardware interrupt number
instead of attempting to calculate it.

Similarly, plat_irq_dispatch calculated the virq number by adding
MIPS_CPU_IRQ_BASE to the hardware interrupt number. Ready this for the
introduction of an IPI IRQ domain by instead using irq_linear_revmap.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index e6b413669e57083b09fdc87e5af89dc663889387..338de924b26951fbed06d605a738900fe2737e6f 100644 (file)
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -39,15 +39,17 @@
 #include <asm/mipsmtregs.h>
 #include <asm/setup.h>
 
+static struct irq_domain *irq_domain;
+
 static inline void unmask_mips_irq(struct irq_data *d)
 {
-       set_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+       set_c0_status(IE_SW0 << d->hwirq);
        irq_enable_hazard();
 }
 
 static inline void mask_mips_irq(struct irq_data *d)
 {
-       clear_c0_status(IE_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+       clear_c0_status(IE_SW0 << d->hwirq);
        irq_disable_hazard();
 }
 
@@ -70,7 +72,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
 {
        unsigned int vpflags = dvpe();
 
-       clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+       clear_c0_cause(C_SW0 << d->hwirq);
        evpe(vpflags);
        unmask_mips_irq(d);
        return 0;
@@ -83,7 +85,7 @@ static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
 static void mips_mt_cpu_irq_ack(struct irq_data *d)
 {
        unsigned int vpflags = dvpe();
-       clear_c0_cause(C_SW0 << (d->irq - MIPS_CPU_IRQ_BASE));
+       clear_c0_cause(C_SW0 << d->hwirq);
        evpe(vpflags);
        mask_mips_irq(d);
 }
@@ -103,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = {
 asmlinkage void __weak plat_irq_dispatch(void)
 {
        unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
+       unsigned int virq;
        int irq;
 
        if (!pending) {
@@ -113,7 +116,8 @@ asmlinkage void __weak plat_irq_dispatch(void)
        pending >>= CAUSEB_IP;
        while (pending) {
                irq = fls(pending) - 1;
-               do_IRQ(MIPS_CPU_IRQ_BASE + irq);
+               virq = irq_linear_revmap(irq_domain, irq);
+               do_IRQ(virq);
                pending &= ~BIT(irq);
        }
 }
@@ -145,15 +149,14 @@ static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
 
 static void __init __mips_cpu_irq_init(struct device_node *of_node)
 {
-       struct irq_domain *domain;
-
        /* Mask interrupts. */
        clear_c0_status(ST0_IM);
        clear_c0_cause(CAUSEF_IP);
 
-       domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
-                                      &mips_cpu_intc_irq_domain_ops, NULL);
-       if (!domain)
+       irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
+                                          &mips_cpu_intc_irq_domain_ops,
+                                          NULL);
+       if (!irq_domain)
                panic("Failed to add irqdomain for MIPS CPU");
 }