MLK-10009-7 PCI: imx6: Wait the clocks to stabilize after ref_en

For boards without a reset gpio we skip the delay between enabling
the pcie_ref_clk and touching the RC registers for configuration.
System would be hangs when the clocks are not yet settled in the DW
PCIe core. So we need to make sure that there is always an
appropriate delay between those two actions.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 233fe8a882649dfc4197b8ac58ff1dd0bdaed6e9..eac96fbc766fd6a6bd57ca41dd082b046489bfe5 100644 (file)
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
                goto err_pcie;
        }
 
-       /* allow the clocks to stabilize */
-       usleep_range(200, 500);
-
        /* power up core phy and enable ref clock */
        regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
                        IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+       /*
+        * the async reset input need ref clock to sync internally,
+        * when the ref clock comes after reset, internal synced
+        * reset time is too short , cannot meet the requirement.
+        * add one ~10us delay here.
+        */
+       udelay(10);
        regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
                        IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 
+       /* allow the clocks to stabilize */
+       usleep_range(200, 500);
+
        /* Some boards don't have PCIe reset GPIO. */
        if (gpio_is_valid(imx6_pcie->reset_gpio)) {
                gpio_set_value(imx6_pcie->reset_gpio, 0);