]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()
authorShawn Lin <shawn.lin@rock-chips.com>
Thu, 4 May 2017 02:24:49 +0000 (10:24 +0800)
committerBjorn Helgaas <bhelgaas@google.com>
Sun, 2 Jul 2017 23:45:55 +0000 (18:45 -0500)
Configuration accesses is also part of ATU settings, so let's keep all of
them inside rockchip_pcie_cfg_atu().

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/host/pcie-rockchip.c

index 8b22842ecff7c85824629e9985813ccb5e11070c..7aadf438c7541d42e780bf131a22698201f11035 100644 (file)
@@ -664,16 +664,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
        }
 
-       rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
-
-       rockchip_pcie_write(rockchip,
-                           (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
-                           PCIE_CORE_OB_REGION_ADDR0);
-       rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
-                           PCIE_CORE_OB_REGION_ADDR1);
-       rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
-       rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
-
        return 0;
 }
 
@@ -1163,6 +1153,17 @@ static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
        int err;
        int reg_no;
 
+       /* Configuration Accesses for region 0 */
+       rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
+
+       rockchip_pcie_write(rockchip,
+                           (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
+                           PCIE_CORE_OB_REGION_ADDR0);
+       rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
+                           PCIE_CORE_OB_REGION_ADDR1);
+       rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
+       rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
+
        for (reg_no = 0; reg_no < (rockchip->mem_size >> 20); reg_no++) {
                err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
                                                AXI_WRAPPER_MEM_WRITE,