Merge remote-tracking branch 'tegra/for-next'

Conflicts:
	MAINTAINERS

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index f8d1276d18afca4fd3960a79af12b4cd425e8cf9..09e740f58b274184f0cd22b282def431d037b6d9 100644 (file)
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -59,6 +59,14 @@ config ARCH_TEGRA_114_SOC
          Support for NVIDIA Tegra T114 processor family, based on the
          ARM CortexA15MP CPU
 
+config ARCH_TEGRA_124_SOC
+       bool "Enable support for Tegra124 family"
+       select ARM_L1_CACHE_SHIFT_6
+       select HAVE_ARM_ARCH_TIMER
+       help
+         Support for NVIDIA Tegra T124 processor family, based on the
+         ARM CortexA15MP CPU
+
 config TEGRA_AHB
        bool "Enable AHB driver for NVIDIA Tegra SoCs"
        default y

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 97eb48e977e553afa0d66b786a1091bbc2bdbd77..019bb175866294227f4197633d58d32a7b89004c 100644 (file)
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -35,5 +35,10 @@ obj-$(CONFIG_ARCH_TEGRA_114_SOC)     += pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)       += cpuidle-tegra114.o
 endif
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)       += sleep-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)       += pm-tegra30.o
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_TEGRA_124_SOC)       += cpuidle-tegra114.o
+endif
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)                += board-paz00.o

diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 0961dfcf83a4af4e2395f114a3608f6d35ac4349..7bc5d8d667fe166e119ae797f5f4eb04007096cc 100644 (file)
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -39,7 +39,9 @@ void __init tegra_cpuidle_init(void)
                        tegra30_cpuidle_init();
                break;
        case TEGRA114:
-               if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+       case TEGRA124:
+               if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                   IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                        tegra114_cpuidle_init();
                break;
        }

diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index 5348543382bfa292bded606815256e038281e75e..ce8ab8abf0616551416f5becbe8fcbd9317f6e18 100644 (file)
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
                break;
        case TEGRA30:
        case TEGRA114:
+       case TEGRA124:
                /* clear wfe bitmap */
                reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
                /* clear wfi bitmap */
@@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
                break;
        case TEGRA30:
        case TEGRA114:
+       case TEGRA124:
                /* clear wfe bitmap */
                reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
                /* clear wfi bitmap */

diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index fef1dc8305d3341d9a9f95b1176619495ae0ec1c..9a4e910c3796154c8fa6c167851a8f6b112265f3 100644 (file)
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -21,14 +21,26 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/export.h>
+#include <linux/random.h>
 #include <linux/tegra-soc.h>
 
 #include "fuse.h"
 #include "iomap.h"
 #include "apbio.h"
 
+/* Tegra20 only */
 #define FUSE_UID_LOW           0x108
 #define FUSE_UID_HIGH          0x10c
+
+/* Tegra30 and later */
+#define FUSE_VENDOR_CODE       0x200
+#define FUSE_FAB_CODE          0x204
+#define FUSE_LOT_CODE_0                0x208
+#define FUSE_LOT_CODE_1                0x20c
+#define FUSE_WAFER_ID          0x210
+#define FUSE_X_COORDINATE      0x214
+#define FUSE_Y_COORDINATE      0x218
+
 #define FUSE_SKU_INFO          0x110
 
 #define TEGRA20_FUSE_SPARE_BIT         0x200
@@ -112,21 +124,51 @@ u32 tegra_read_chipid(void)
        return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
 }
 
+static void __init tegra20_fuse_init_randomness(void)
+{
+       u32 randomness[2];
+
+       randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
+       randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);
+
+       add_device_randomness(randomness, sizeof(randomness));
+}
+
+/* Applies to Tegra30 or later */
+static void __init tegra30_fuse_init_randomness(void)
+{
+       u32 randomness[7];
+
+       randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
+       randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
+       randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
+       randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
+       randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
+       randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
+       randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);
+
+       add_device_randomness(randomness, sizeof(randomness));
+}
+
 void __init tegra_init_fuse(void)
 {
        u32 id;
+       u32 randomness[5];
 
        u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
        reg |= 1 << 28;
        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 
        reg = tegra_fuse_readl(FUSE_SKU_INFO);
+       randomness[0] = reg;
        tegra_sku_id = reg & 0xFF;
 
        reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
+       randomness[1] = reg;
        tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
 
        id = tegra_read_chipid();
+       randomness[2] = id;
        tegra_chip_id = (id >> 8) & 0xff;
 
        switch (tegra_chip_id) {
@@ -149,6 +191,18 @@ void __init tegra_init_fuse(void)
 
        tegra_revision = tegra_get_revision(id);
        tegra_init_speedo_data();
+       randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id;
+       randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id;
+
+       add_device_randomness(randomness, sizeof(randomness));
+       switch (tegra_chip_id) {
+       case TEGRA20:
+               tegra20_fuse_init_randomness();
+       case TEGRA30:
+       case TEGRA114:
+       default:
+               tegra30_fuse_init_randomness();
+       }
 
        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
                tegra_revision_name[tegra_revision],

diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index def79683bef62d2af19d6b17d8b93063c8b2d508..c01d04785d6716cc93a064bc812168e8eafb55b7 100644 (file)
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -29,6 +29,7 @@
 #define TEGRA20                0x20
 #define TEGRA30                0x30
 #define TEGRA114       0x35
+#define TEGRA124       0x40
 
 #ifndef __ASSEMBLY__
 enum tegra_revision {

diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 04de2e8609237fbd8133b4e8341a588db47c7a33..ff26af26bd0ce7b15d7a9308f3a36d240ec0a8a1 100644 (file)
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -57,4 +57,6 @@ void __init tegra_hotplug_init(void)
                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+       if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
+               tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }

diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index cbee57fc4fd86f1cb0bda0dbd543e9cf6f81a3b5..26b1c2ad0cebfd30a50573138808b7df17cd34cf 100644 (file)
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -105,6 +105,9 @@
 #define TEGRA_EMC1_BASE                        0x7001A800
 #define TEGRA_EMC1_SIZE                        SZ_2K
 
+#define TEGRA124_EMC_BASE              0x7001B000
+#define TEGRA124_EMC_SIZE              SZ_2K
+
 #define TEGRA_CSITE_BASE               0x70040000
 #define TEGRA_CSITE_SIZE               SZ_256K
 

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2d0203627fbb418a10357ffe0b922d907df7809a..eb72ae709124e4978167b2c38c96a63d44543b46 100644 (file)
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -176,6 +176,8 @@ static int tegra_boot_secondary(unsigned int cpu,
                return tegra30_boot_secondary(cpu, idle);
        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
                return tegra114_boot_secondary(cpu, idle);
+       if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
+               return tegra114_boot_secondary(cpu, idle);
 
        return -EINVAL;
 }

diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 36ed88af1cc14ca0f41938b473a4a818e007e3fe..4ae0286b468db6209311d14d13cd9cc673fb200b 100644 (file)
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
                break;
        case TEGRA30:
        case TEGRA114:
+       case TEGRA124:
                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-                   IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                   IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                   IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                        tegra_tear_down_cpu = tegra30_tear_down_cpu;
                break;
        }
@@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
                break;
        case TEGRA30:
        case TEGRA114:
+       case TEGRA124:
                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-                   IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                   IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                   IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                        tegra30_lp1_iram_hook();
                break;
        default:
@@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void)
                break;
        case TEGRA30:
        case TEGRA114:
+       case TEGRA124:
                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
-                   IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                   IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
+                   IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
                        tegra30_sleep_core_init();
                break;
        default:

diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 93a4dbcde27e5dd3391dc47e0f8876945abbba21..fb7920201ab4de46c654321409c39df1066e5641 100644 (file)
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -20,6 +20,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/tegra-powergate.h>
 
 #include "flowctrl.h"
 #include "fuse.h"
@@ -43,12 +44,6 @@
 #define PMC_CPUPWRGOOD_TIMER   0xc8
 #define PMC_CPUPWROFF_TIMER    0xcc
 
-#define TEGRA_POWERGATE_PCIE   3
-#define TEGRA_POWERGATE_VDEC   4
-#define TEGRA_POWERGATE_CPU1   9
-#define TEGRA_POWERGATE_CPU2   10
-#define TEGRA_POWERGATE_CPU3   11
-
 static u8 tegra_cpu_domains[] = {
        0xFF,                   /* not available for CPU0 */
        TEGRA_POWERGATE_CPU1,
@@ -288,6 +283,7 @@ void tegra_pmc_suspend_init(void)
 #endif
 
 static const struct of_device_id matches[] __initconst = {
+       { .compatible = "nvidia,tegra124-pmc" },
        { .compatible = "nvidia,tegra114-pmc" },
        { .compatible = "nvidia,tegra30-pmc" },
        { .compatible = "nvidia,tegra20-pmc" },

diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index f076f0f80fcd325e836061605f5a628efbd05626..85d28e756bb77e8d3b4b66342608e136716288b3 100644 (file)
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -42,8 +42,16 @@
 
 static int tegra_num_powerdomains;
 static int tegra_num_cpu_domains;
-static u8 *tegra_cpu_domains;
-static u8 tegra30_cpu_domains[] = {
+static const u8 *tegra_cpu_domains;
+
+static const u8 tegra30_cpu_domains[] = {
+       TEGRA_POWERGATE_CPU,
+       TEGRA_POWERGATE_CPU1,
+       TEGRA_POWERGATE_CPU2,
+       TEGRA_POWERGATE_CPU3,
+};
+
+static const u8 tegra114_cpu_domains[] = {
        TEGRA_POWERGATE_CPU0,
        TEGRA_POWERGATE_CPU1,
        TEGRA_POWERGATE_CPU2,
@@ -189,6 +197,11 @@ int __init tegra_powergate_init(void)
                tegra_num_cpu_domains = 4;
                tegra_cpu_domains = tegra30_cpu_domains;
                break;
+       case TEGRA114:
+               tegra_num_powerdomains = 23;
+               tegra_num_cpu_domains = 4;
+               tegra_cpu_domains = tegra114_cpu_domains;
+               break;
        default:
                /* Unknown Tegra variant. Disable powergating */
                tegra_num_powerdomains = 0;
@@ -229,6 +242,27 @@ static const char * const powergate_name_t30[] = {
        [TEGRA_POWERGATE_3D1]   = "3d1",
 };
 
+static const char * const powergate_name_t114[] = {
+       [TEGRA_POWERGATE_CPU]   = "cpu0",
+       [TEGRA_POWERGATE_3D]    = "3d",
+       [TEGRA_POWERGATE_VENC]  = "venc",
+       [TEGRA_POWERGATE_VDEC]  = "vdec",
+       [TEGRA_POWERGATE_MPE]   = "mpe",
+       [TEGRA_POWERGATE_HEG]   = "heg",
+       [TEGRA_POWERGATE_CPU1]  = "cpu1",
+       [TEGRA_POWERGATE_CPU2]  = "cpu2",
+       [TEGRA_POWERGATE_CPU3]  = "cpu3",
+       [TEGRA_POWERGATE_CELP]  = "celp",
+       [TEGRA_POWERGATE_CPU0]  = "cpu0",
+       [TEGRA_POWERGATE_C0NC]  = "c0nc",
+       [TEGRA_POWERGATE_C1NC]  = "c1nc",
+       [TEGRA_POWERGATE_DIS]   = "dis",
+       [TEGRA_POWERGATE_DISB]  = "disb",
+       [TEGRA_POWERGATE_XUSBA] = "xusba",
+       [TEGRA_POWERGATE_XUSBB] = "xusbb",
+       [TEGRA_POWERGATE_XUSBC] = "xusbc",
+};
+
 static int powergate_show(struct seq_file *s, void *data)
 {
        int i;
@@ -236,9 +270,14 @@ static int powergate_show(struct seq_file *s, void *data)
        seq_printf(s, " powergate powered\n");
        seq_printf(s, "------------------\n");
 
-       for (i = 0; i < tegra_num_powerdomains; i++)
+       for (i = 0; i < tegra_num_powerdomains; i++) {
+               if (!powergate_name[i])
+                       continue;
+
                seq_printf(s, " %9s %7s\n", powergate_name[i],
                        tegra_powergate_is_powered(i) ? "yes" : "no");
+       }
+
        return 0;
 }
 
@@ -265,6 +304,9 @@ int __init tegra_powergate_debugfs_init(void)
        case TEGRA30:
                powergate_name = powergate_name_t30;
                break;
+       case TEGRA114:
+               powergate_name = powergate_name_t114;
+               break;
        }
 
        if (powergate_name) {

diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index f527b2c2dea779be4f8f26d654e14ba3282369ee..8c1ba4fea384b732d3c4724b118304a5dafd55a5 100644 (file)
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -45,17 +45,11 @@
 ENTRY(tegra_resume)
        check_cpu_part_num 0xc09, r8, r9
        bleq    v7_invalidate_l1
-       blne    tegra_init_l2_for_a15
 
        cpu_id  r0
-       tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
-       cmp     r6, #TEGRA114
-       beq     no_cpu0_chk
-
        cmp     r0, #0                          @ CPU0?
  THUMB(        it      ne )
        bne     cpu_resume                      @ no
-no_cpu0_chk:
 
        /* Are we on Tegra20? */
        cmp     r6, #TEGRA20
@@ -75,7 +69,7 @@ no_cpu0_chk:
 
        mov32   r9, 0xc09
        cmp     r8, r9
-       bne     not_ca9
+       bne     end_ca9_scu_l2_resume
 #ifdef CONFIG_HAVE_ARM_SCU
        /* enable SCU */
        mov32   r0, TEGRA_ARM_PERIF_BASE
@@ -86,7 +80,10 @@ no_cpu0_chk:
 
        /* L2 cache resume & re-enable */
        l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
-not_ca9:
+end_ca9_scu_l2_resume:
+       mov32   r9, 0xc0f
+       cmp     r8, r9
+       bleq    tegra_init_l2_for_a15
 
        b       cpu_resume
 ENDPROC(tegra_resume)

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index c6fc15cb25df7cccc6ac859576b9449d5ca2e5cb..b16d4a57fa59dd529e2ae97bd8890521bf543fe6 100644 (file)
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -383,7 +383,7 @@ _pll_m_c_x_done:
        add     r1, r1, #LOCK_DELAY
        wait_until r1, r7, r3
 
-       adr     r5, tegra30_sdram_pad_save
+       adr     r5, tegra_sdram_pad_save
 
        ldr     r4, [r5, #0x18]         @ restore CLK_SOURCE_MSELECT
        str     r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
@@ -408,8 +408,12 @@ _pll_m_c_x_done:
        cmp     r10, #TEGRA30
        movweq  r0, #:lower16:TEGRA_EMC_BASE    @ r0 reserved for emc base
        movteq  r0, #:upper16:TEGRA_EMC_BASE
-       movwne  r0, #:lower16:TEGRA_EMC0_BASE
-       movtne  r0, #:upper16:TEGRA_EMC0_BASE
+       cmp     r10, #TEGRA114
+       movweq  r0, #:lower16:TEGRA_EMC0_BASE
+       movteq  r0, #:upper16:TEGRA_EMC0_BASE
+       cmp     r10, #TEGRA124
+       movweq  r0, #:lower16:TEGRA124_EMC_BASE
+       movteq  r0, #:upper16:TEGRA124_EMC_BASE
 
 exit_self_refresh:
        ldr     r1, [r5, #0xC]          @ restore EMC_XM2VTTGENPADCTRL
@@ -538,6 +542,7 @@ tegra30_sdram_pad_address:
        .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+tegra30_sdram_pad_address_end:
 
 tegra114_sdram_pad_address:
        .word   TEGRA_EMC0_BASE + EMC_CFG                               @0x0
@@ -553,16 +558,28 @@ tegra114_sdram_pad_address:
        .word   TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL                 @0x28
        .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL                  @0x2c
        .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2                 @0x30
+tegra114_sdram_pad_adress_end:
+
+tegra124_sdram_pad_address:
+       .word   TEGRA124_EMC_BASE + EMC_CFG                             @0x0
+       .word   TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL                   @0x4
+       .word   TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL               @0x8
+       .word   TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL                @0xc
+       .word   TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2               @0x10
+       .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
+       .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
+       .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+tegra124_sdram_pad_address_end:
 
 tegra30_sdram_pad_size:
-       .word   tegra114_sdram_pad_address - tegra30_sdram_pad_address
+       .word   tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
 
 tegra114_sdram_pad_size:
-       .word   tegra30_sdram_pad_size - tegra114_sdram_pad_address
+       .word   tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
 
-       .type   tegra30_sdram_pad_save, %object
-tegra30_sdram_pad_save:
-       .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
+       .type   tegra_sdram_pad_save, %object
+tegra_sdram_pad_save:
+       .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
        .long   0
        .endr
 
@@ -693,13 +710,18 @@ halted:
  */
 tegra30_sdram_self_refresh:
 
-       adr     r8, tegra30_sdram_pad_save
+       adr     r8, tegra_sdram_pad_save
        tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
        cmp     r10, #TEGRA30
        adreq   r2, tegra30_sdram_pad_address
        ldreq   r3, tegra30_sdram_pad_size
-       adrne   r2, tegra114_sdram_pad_address
-       ldrne   r3, tegra114_sdram_pad_size
+       cmp     r10, #TEGRA114
+       adreq   r2, tegra114_sdram_pad_address
+       ldreq   r3, tegra114_sdram_pad_size
+       cmp     r10, #TEGRA124
+       adreq   r2, tegra124_sdram_pad_address
+       ldreq   r3, tegra30_sdram_pad_size
+
        mov     r9, #0
 
 padsave:
@@ -717,7 +739,10 @@ padsave_done:
 
        cmp     r10, #TEGRA30
        ldreq   r0, =TEGRA_EMC_BASE     @ r0 reserved for emc base addr
-       ldrne   r0, =TEGRA_EMC0_BASE
+       cmp     r10, #TEGRA114
+       ldreq   r0, =TEGRA_EMC0_BASE
+       cmp     r10, #TEGRA124
+       ldreq   r0, =TEGRA124_EMC_BASE
 
 enter_self_refresh:
        cmp     r10, #TEGRA30

diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 386115ae5c0322e487e51b289cb831f18aa4fa37..ce553d557c31caf1670e50ceadad19c067d2864c 100644 (file)
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -173,6 +173,7 @@ static void __init tegra_dt_init_late(void)
 }
 
 static const char * const tegra_dt_board_compat[] = {
+       "nvidia,tegra124",
        "nvidia,tegra114",
        "nvidia,tegra30",
        "nvidia,tegra20",

diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
index 55c29a8d5015f60927d9da28d7992f8e536bfa73..c98cfa40695248d16ab3ee91891c33334239c252 100644 (file)
--- a/include/linux/tegra-powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -34,8 +34,15 @@ struct clk;
 #define TEGRA_POWERGATE_CPU3   11
 #define TEGRA_POWERGATE_CELP   12
 #define TEGRA_POWERGATE_3D1    13
+#define TEGRA_POWERGATE_CPU0   14
+#define TEGRA_POWERGATE_C0NC   15
+#define TEGRA_POWERGATE_C1NC   16
+#define TEGRA_POWERGATE_DIS    18
+#define TEGRA_POWERGATE_DISB   19
+#define TEGRA_POWERGATE_XUSBA  20
+#define TEGRA_POWERGATE_XUSBB  21
+#define TEGRA_POWERGATE_XUSBC  22
 
-#define TEGRA_POWERGATE_CPU0   TEGRA_POWERGATE_CPU
 #define TEGRA_POWERGATE_3D0    TEGRA_POWERGATE_3D
 
 int tegra_powergate_is_powered(int id);