CI_HDRC_IMX_EHCI_QUIRK |
CI_HDRC_DISABLE_STREAMING |
CI_HDRC_OVERRIDE_AHB_BURST |
- CI_HDRC_OVERRIDE_BURST_LENGTH,
+ CI_HDRC_OVERRIDE_BURST_LENGTH |
+ CI_HDRC_IMX_VBUS_EARLY_ON,
.ahbburst_config = 0, /*bit0 - bit2 at $BASE + 0x90 */
.burst_length = 0x1010, /*bit0 - bit15 at $BASE + 0x160 */
};
CI_HDRC_IMX_EHCI_QUIRK |
CI_HDRC_DISABLE_HOST_STREAMING |
CI_HDRC_OVERRIDE_AHB_BURST |
- CI_HDRC_OVERRIDE_BURST_LENGTH,
+ CI_HDRC_OVERRIDE_BURST_LENGTH |
+ CI_HDRC_IMX_VBUS_EARLY_ON,
.ahbburst_config = 0,
.burst_length = 0x1010,
};
CI_HDRC_IMX_EHCI_QUIRK |
CI_HDRC_DISABLE_HOST_STREAMING |
CI_HDRC_OVERRIDE_AHB_BURST |
- CI_HDRC_OVERRIDE_BURST_LENGTH,
+ CI_HDRC_OVERRIDE_BURST_LENGTH |
+ CI_HDRC_IMX_VBUS_EARLY_ON,
.ahbburst_config = 0,
.burst_length = 0x1010,
};
CI_HDRC_DISABLE_HOST_STREAMING)
#define CI_HDRC_OVERRIDE_AHB_BURST BIT(11)
#define CI_HDRC_OVERRIDE_BURST_LENGTH BIT(12)
+#define CI_HDRC_IMX_VBUS_EARLY_ON BIT(13)
enum usb_dr_mode dr_mode;
#define CI_HDRC_CONTROLLER_RESET_EVENT 0
#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1