genirq: Generic chip: Cache per irq bit mask

Cache the per irq bit mask instead of recalculating it over and over.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Rob Landley <rob@landley.net>
Acked-by: Grant Likely <grant.likely@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: http://lkml.kernel.org/r/20130506142539.227119865@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 7f1f0157fd00c8af008b745942742d0136c94ae4..d5fc7f5a49b8ce302e081b183bb1e8f3c8a5b5c2 100644 (file)
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -119,6 +119,7 @@ struct irq_domain;
 
 /**
  * struct irq_data - per irq and irq chip data passed down to chip functions
+ * @mask:              precomputed bitmask for accessing the chip registers
  * @irq:               interrupt number
  * @hwirq:             hardware interrupt number, local to the interrupt domain
  * @node:              node index useful for balancing
@@ -138,6 +139,7 @@ struct irq_domain;
  * irq_data.
  */
 struct irq_data {
+       u32                     mask;
        unsigned int            irq;
        unsigned long           hwirq;
        unsigned int            node;
@@ -705,11 +707,13 @@ struct irq_chip_generic {
  *                             irq chips which need to call irq_set_wake() on
  *                             the parent irq. Usually GPIO implementations
  * @IRQ_GC_MASK_CACHE_PER_TYPE:        Mask cache is chip type private
+ * @IRQ_GC_NO_MASK:            Do not calculate irq_data->mask
  */
 enum irq_gc_flags {
        IRQ_GC_INIT_MASK_CACHE          = 1 << 0,
        IRQ_GC_INIT_NESTED_LOCK         = 1 << 1,
        IRQ_GC_MASK_CACHE_PER_TYPE      = 1 << 2,
+       IRQ_GC_NO_MASK                  = 1 << 3,
 };
 
 /* Generic chip callback functions */

diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index da2a94191fc527a9d36ca09db11fdfaf6a8eb3d1..957155cebbac5b9d5e6f118927b8ab0b347ff5a7 100644 (file)
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -35,7 +35,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        irq_gc_lock(gc);
        irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
@@ -54,7 +54,7 @@ void irq_gc_mask_set_bit(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        irq_gc_lock(gc);
        *ct->mask_cache |= mask;
@@ -73,7 +73,7 @@ void irq_gc_mask_clr_bit(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        irq_gc_lock(gc);
        *ct->mask_cache &= ~mask;
@@ -92,7 +92,7 @@ void irq_gc_unmask_enable_reg(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        irq_gc_lock(gc);
        irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
@@ -108,7 +108,7 @@ void irq_gc_ack_set_bit(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        irq_gc_lock(gc);
        irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
@@ -123,7 +123,7 @@ void irq_gc_ack_clr_bit(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = ~(1 << (d->irq - gc->irq_base));
+       u32 mask = ~d->mask;
 
        irq_gc_lock(gc);
        irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
@@ -138,7 +138,7 @@ void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        irq_gc_lock(gc);
        irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
@@ -154,7 +154,7 @@ void irq_gc_eoi(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        irq_gc_lock(gc);
        irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
@@ -172,7 +172,7 @@ void irq_gc_eoi(struct irq_data *d)
 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-       u32 mask = 1 << (d->irq - gc->irq_base);
+       u32 mask = d->mask;
 
        if (!(mask & gc->wake_enabled))
                return -EINVAL;
@@ -264,6 +264,11 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
                if (flags & IRQ_GC_INIT_NESTED_LOCK)
                        irq_set_lockdep_class(i, &irq_nested_lock_class);
 
+               if (!(flags & IRQ_GC_NO_MASK)) {
+                       struct irq_data *d = irq_get_irq_data(i);
+
+                       d->mask = 1 << (i - gc->irq_base);
+               }
                irq_set_chip_and_handler(i, &ct->chip, ct->handler);
                irq_set_chip_data(i, gc);
                irq_modify_status(i, clr, set);