/* Audio-related clocks configuration */
clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
+ clk_set_parent(clk[asrc_sel], clk[pll3_usb_otg]);
+ clk_set_rate(clk[asrc_sel], 7500000);
/* All existing boards with PCIe use LVDS1 */
if (IS_ENABLED(CONFIG_PCI_IMX6))
static int mxc_init_asrc(void)
{
+ clk_enable(asrc->asrc_clk);
+
/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
asrc_regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
/* Set the processing clock for 56KHz, 133M */
asrc_regmap_write(asrc->regmap, REG_ASR56K, 0x0947);
+ clk_disable(asrc->asrc_clk);
+
return 0;
}
goto err_iomap;
}
#ifndef ASRC_USE_REGMAP
- clk_prepare_enable(asrc->asrc_clk);
+ clk_prepare(asrc->asrc_clk);
#endif
ret = of_property_read_u32_array(pdev->dev.of_node,
static int mxc_asrc_remove(struct platform_device *pdev)
{
+#ifndef ASRC_USE_REGMAP
+ clk_unprepare(asrc->asrc_clk);
+#endif
asrc_proc_remove();
misc_deregister(&asrc_miscdev);
/* Ideal Ratio mode doesn't care the outclk frequency, so be fixed */
-#define ASRC_PRESCALER_IDEAL_RATIO 7
+#define ASRC_PRESCALER_IDEAL_RATIO 5
/* SPDIF rxclk pulse rate is 128 * samplerate, so 2 ^ 7 */
#define ASRC_PRESCALER_SPDIF_RX 7
/* SPDIF txclk pulse rate is 64 * samplerate, so 2 ^ 6 */