]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
ARM: S3C64XX: Migrate clock handling to Common Clock Framework
authorTomasz Figa <tomasz.figa@gmail.com>
Sun, 25 Aug 2013 17:00:38 +0000 (02:00 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Mon, 16 Sep 2013 21:47:36 +0000 (06:47 +0900)
This patch migrates the s3c64xx platform to use the new clock driver
using Common Clock Framework.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
15 files changed:
arch/arm/Kconfig
arch/arm/mach-s3c64xx/Makefile
arch/arm/mach-s3c64xx/common.c
arch/arm/mach-s3c64xx/common.h
arch/arm/mach-s3c64xx/mach-anw6410.c
arch/arm/mach-s3c64xx/mach-crag6410.c
arch/arm/mach-s3c64xx/mach-hmt.c
arch/arm/mach-s3c64xx/mach-mini6410.c
arch/arm/mach-s3c64xx/mach-ncp.c
arch/arm/mach-s3c64xx/mach-smartq.c
arch/arm/mach-s3c64xx/mach-smdk6400.c
arch/arm/mach-s3c64xx/mach-smdk6410.c
arch/arm/mach-s3c64xx/s3c6400.c
arch/arm/mach-s3c64xx/s3c6410.c
drivers/clk/samsung/Makefile

index 3f7714d8d2d216bf3bbd7b4a5b227ea982997554..76b025e3a74afa6d4312cb3b0a90d7a02442ddff 100644 (file)
@@ -727,6 +727,7 @@ config ARCH_S3C64XX
        select ARM_VIC
        select CLKDEV_LOOKUP
        select CLKSRC_SAMSUNG_PWM
+       select COMMON_CLK
        select CPU_V6
        select GENERIC_CLOCKEVENTS
        select GPIO_SAMSUNG
@@ -740,7 +741,6 @@ config ARCH_S3C64XX
        select S3C_DEV_NAND
        select S3C_GPIO_TRACK
        select SAMSUNG_ATAGS
-       select SAMSUNG_CLKSRC
        select SAMSUNG_GPIOLIB_4BIT
        select SAMSUNG_WDT_RESET
        select USB_ARCH_HAS_OHCI
index 31d0c9101272196e81f7da943bc25bfdd1420722..645a8fe55f8d4ed166efffc1f7368e01615cc0da 100644 (file)
@@ -12,7 +12,7 @@ obj-                          :=
 
 # Core
 
-obj-y                          += common.o clock.o
+obj-y                          += common.o
 
 # Core support
 
index 73d79cf5e14118b1e99861c5bd79d6ffc9517164..7d3cb58f1856912c1119b95bdcd1ea4ea41e3718 100644 (file)
@@ -17,6 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/clk-provider.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
@@ -38,7 +39,6 @@
 #include <mach/regs-gpio.h>
 
 #include <plat/cpu.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/gpio-cfg.h>
 
 #include "common.h"
 
+/* External clock frequency */
+static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
+
+void __init s3c64xx_set_xtal_freq(unsigned long freq)
+{
+       xtal_f = freq;
+}
+
+void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
+{
+       xusbxti_f = freq;
+}
+
 /* uart registration process */
 
 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -67,7 +80,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = S3C6400_CPU_ID,
                .idmask         = S3C64XX_CPU_MASK,
                .map_io         = s3c6400_map_io,
-               .init_clocks    = s3c6400_init_clocks,
                .init_uarts     = s3c64xx_init_uarts,
                .init           = s3c6400_init,
                .name           = name_s3c6400,
@@ -75,7 +87,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = S3C6410_CPU_ID,
                .idmask         = S3C64XX_CPU_MASK,
                .map_io         = s3c6410_map_io,
-               .init_clocks    = s3c6410_init_clocks,
                .init_uarts     = s3c64xx_init_uarts,
                .init           = s3c6410_init,
                .name           = name_s3c6410,
@@ -213,8 +224,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 {
        /*
         * FIXME: there is no better place to put this at the moment
-        * (samsung_wdt_reset_init needs clocks)
+        * (s3c64xx_clk_init needs ioremap and must happen before init_time
+        * samsung_wdt_reset_init needs clocks)
         */
+       s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 
        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
index e8f990b37665b900d667c7332b6e26bf389beb93..a2af0e1fdb005573109b37ac506d0f97b8b87326 100644 (file)
 void s3c64xx_init_irq(u32 vic0, u32 vic1);
 void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 
-void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
-void s3c64xx_setup_clocks(void);
-
 void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
 void s3c64xx_init_late(void);
 
+void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
+       unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
+void s3c64xx_set_xtal_freq(unsigned long freq);
+void s3c64xx_set_xusbxti_freq(unsigned long freq);
+
 #ifdef CONFIG_CPU_S3C6400
 
 extern  int s3c6400_init(void);
 extern void s3c6400_init_irq(void);
 extern void s3c6400_map_io(void);
-extern void s3c6400_init_clocks(int xtal);
 
 #else
 #define s3c6400_init_clocks NULL
@@ -46,7 +47,6 @@ extern void s3c6400_init_clocks(int xtal);
 extern  int s3c6410_init(void);
 extern void s3c6410_init_irq(void);
 extern void s3c6410_map_io(void);
-extern void s3c6410_init_clocks(int xtal);
 
 #else
 #define s3c6410_init_clocks NULL
index 35e3f54574eff6773f5c2eca10b69d0d1e02cccc..d266dd5f7060ec37d0266205bf129bdf86177a3e 100644 (file)
@@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = {
 static void __init anw6410_map_io(void)
 {
        s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
        s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
index eb8e5a1aca420005fa5e0988a099e51eb8ec6f94..1a911df9e4519e4c2f6ca494b5a2b182a14e765b 100644 (file)
@@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = {
 static void __init crag6410_map_io(void)
 {
        s3c64xx_init_io(NULL, 0);
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
        s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
index f39569e0f2e6c4045f95e333a255c72d87be4c98..e8064044ef796d35a12bfcc0e06c86dea065dca1 100644 (file)
@@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = {
 static void __init hmt_map_io(void)
 {
        s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
        s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
index fc043e3ecdf8a869ea77e27af42dad5c24222356..58d46a3d7b78936f88318824d1a378fea2532fc1 100644 (file)
@@ -231,7 +231,7 @@ static void __init mini6410_map_io(void)
        u32 tmp;
 
        s3c64xx_init_io(NULL, 0);
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
        s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
index 7e2c3908f1f87a2db546867d9ff8417e2051049e..2067b0bf55b43127eef766b52beb283a11db6431 100644 (file)
@@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {};
 static void __init ncp_map_io(void)
 {
        s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
        s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
index 86d980b448fd0bc272e1e0cf1ab616f0e32ab24e..0f47237be3b2dd2286fe0582791548d16df3a786 100644 (file)
@@ -337,13 +337,6 @@ err:
        return ret;
 }
 
-static int __init smartq_usb_otg_init(void)
-{
-       clk_xusbxti.rate = 12000000;
-
-       return 0;
-}
-
 static int __init smartq_wifi_init(void)
 {
        int ret;
@@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {};
 void __init smartq_map_io(void)
 {
        s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
+       s3c64xx_set_xusbxti_freq(12000000);
        s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
@@ -399,7 +393,6 @@ void __init smartq_machine_init(void)
        WARN_ON(smartq_lcd_setup_gpio());
        WARN_ON(smartq_power_off_init());
        WARN_ON(smartq_usb_host_init());
-       WARN_ON(smartq_usb_otg_init());
        WARN_ON(smartq_wifi_init());
 
        platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
index d70c0843aea2d8bca384cc814d0270e778def128..27381cfcabbedbe2a669272d3786f56db08f11ba 100644 (file)
@@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {};
 static void __init smdk6400_map_io(void)
 {
        s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
        s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
index d90b450c5645bb9f9c10944a65e3086623e25b3b..2a7b32ca5c96a3037c007eeb032092cf2127bfec 100644 (file)
@@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void)
        u32 tmp;
 
        s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
-       s3c24xx_init_clocks(12000000);
+       s3c64xx_set_xtal_freq(12000000);
        s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
index 4869714c6f1bb015e4b6af08705837169bad2466..331fe8e581457ae0ce37dbfc769cd741d0b7c21e 100644 (file)
@@ -58,12 +58,6 @@ void __init s3c6400_map_io(void)
        s3c64xx_onenand1_setname("s3c6400-onenand");
 }
 
-void __init s3c6400_init_clocks(int xtal)
-{
-       s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
-       s3c64xx_setup_clocks();
-}
-
 void __init s3c6400_init_irq(void)
 {
        /* VIC0 does not have IRQS 5..7,
index 31c29fdf1800404948a9e9e207454dcf337b7f7e..7e6fa125584ac721aecb2c0c38f3011662ea1560 100644 (file)
@@ -62,13 +62,6 @@ void __init s3c6410_map_io(void)
        s3c_cfcon_setname("s3c64xx-pata");
 }
 
-void __init s3c6410_init_clocks(int xtal)
-{
-       printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
-       s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
-       s3c64xx_setup_clocks();
-}
-
 void __init s3c6410_init_irq(void)
 {
        /* VIC0 is missing IRQ7, VIC1 is fully populated. */
index 3413380086d5b22f7e9a618231e33af9a1e37b1e..8eb4799237f03d5106cfe52537c587fb7fc648dd 100644 (file)
@@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5420)   += clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
-ifdef CONFIG_COMMON_CLK
 obj-$(CONFIG_ARCH_S3C64XX)     += clk-s3c64xx.o
-endif