PCI: mvebu: Avoid changing the SCC bit in the Link Status register

It seems on later Armada 38x, the slot clock configuration bit is not
read-only, but can be written.  This means that our RW1C protection ends up
clearing this bit when the link control register is written.

Adjust the mask so that we only avoid writing '1' bits to the RW1C bits of
this register (bits 15 and 14 of the link status) rather than masking out
all the status register bits.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index cd7d51988738e288e8269f0c016ec0d31aa99c13..266447ee886782c503d1f4de51f5982af21d842d 100644 (file)
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -752,10 +752,11 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
                 * If the mask is 0xffff0000, then we only want to write
                 * the link control register, rather than clearing the
                 * RW1C bits in the link status register.  Mask out the
-                * status register bits.
+                * RW1C status register bits.
                 */
                if (mask == 0xffff0000)
-                       value &= 0xffff;
+                       value &= ~((PCI_EXP_LNKSTA_LABS |
+                                   PCI_EXP_LNKSTA_LBMS) << 16);
 
                mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
                break;