bnx2x: PCI configuration bug on big-endian

commit 7d96567ac0527703cf1b80043fc0ebd7f21a10ad upstream.

The current code read nothing but zeros on big-endian (wrong part of the
32bits). This caused poor performance on big-endian machines. Though this
issue did not cause the system to crash, the performance is significantly
better with the fix so I view it as critical bug fix.

Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Cc: Alex Chiang <achiang@hp.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 130927cfc75b63c79f986280029ddc4596f81c46..a6c0b3abba290a9cd75c7b7c4a764874c4e55801 100644 (file)
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -564,14 +564,15 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
 
 static void bnx2x_init_pxp(struct bnx2x *bp)
 {
+       u16 devctl;
        int r_order, w_order;
        u32 val, i;
 
        pci_read_config_word(bp->pdev,
-                            bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val);
-       DP(NETIF_MSG_HW, "read 0x%x from devctl\n", (u16)val);
-       w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
-       r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12);
+                            bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
+       DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
+       w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
+       r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
 
        if (r_order > MAX_RD_ORD) {
                DP(NETIF_MSG_HW, "read order of %d  order adjusted to %d\n",