imx_clk_set_parent(pll1_sw_clk, step_clk);
/*
* Ensure that the clock will be
- * at original speed. the arm_podf can only be
- * changed when the pll1 output is enabled. So
- * enable pll1 output before change cpu_clk.
+ * at original speed.
*/
- imx6sl_enable_pll_arm(true);
imx_clk_set_rate(cpu_clk, org_arm_rate);
- imx6sl_enable_pll_arm(false);
}
low_bus_freq_mode = 0;
ultra_low_bus_freq_mode = 0;
/* Move ARM from PLL1_SW_CLK to PLL2_400. */
imx_clk_set_parent(step_clk, pll2_400);
imx_clk_set_parent(pll1_sw_clk, step_clk);
- /*
- * arm_podf can only be changed when pll1 output
- * is enabled. Enable pll1 output before changing
- * cpu_clk rate.
- */
- imx6sl_enable_pll_arm(true);
imx_clk_set_rate(cpu_clk, org_arm_rate);
- imx6sl_enable_pll_arm(false);
ultra_low_bus_freq_mode = 0;
}
}
#define BM_PLL_ARM_DIV_SELECT (0x7f << 0)
#define BM_PLL_ARM_POWERDOWN (1 << 12)
#define BM_PLL_ARM_ENABLE (1 << 13)
-#define BM_PLL_ARM_BYPASS (1 << 16)
#define BM_PLL_ARM_LOCK (1 << 31)
#define PLL_ARM_DIV_792M 66
}
}
-void imx6sl_enable_pll_arm(bool enable)
+static void imx6sl_enable_pll_arm(bool enable)
{
static u32 saved_pll_arm;
u32 val;
if (enable) {
saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
val |= BM_PLL_ARM_ENABLE;
- val |= BM_PLL_ARM_BYPASS;
+ val &= ~BM_PLL_ARM_POWERDOWN;
writel_relaxed(val, anatop_base + PLL_ARM);
+ while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
+ ;
} else {
writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
}
void imx_anatop_post_resume(void);
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_int_mem_clk_lpm(bool enable);
-void imx6sl_enable_pll_arm(bool enable);
void imx6sl_set_wait_clk(bool enter);
void imx6_enet_mac_init(const char *compatible);
int imx_mmdc_get_ddr_type(void);