config SND_SOC_MAX9850
tristate
+config SND_SOC_MSM8x16_WCD
+ tristate "Qualcomm MSM8x16 WCD"
+ depends on SPMI && MFD_SYSCON
+
config SND_SOC_PCM1681
tristate "Texas Instruments PCM1681 CODEC"
depends on I2C
snd-soc-ml26124-objs := ml26124.o
snd-soc-nau8825-objs := nau8825.o
snd-soc-hdmi-codec-objs := hdmi-codec.o
+snd-soc-msm8x16-objs := msm8x16-wcd.o msm8x16-wcd-tables.o
snd-soc-pcm1681-objs := pcm1681.o
snd-soc-pcm1792a-codec-objs := pcm1792a.o
snd-soc-pcm3008-objs := pcm3008.o
snd-soc-wm9712-objs := wm9712.o
snd-soc-wm9713-objs := wm9713.o
snd-soc-wm-hubs-objs := wm_hubs.o
-
# Amp
snd-soc-max9877-objs := max9877.o
snd-soc-tpa6130a2-objs := tpa6130a2.o
obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o
obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o
+obj-$(CONFIG_SND_SOC_MSM8x16_WCD) +=snd-soc-msm8x16.o
obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o
obj-$(CONFIG_SND_SOC_PCM1792A) += snd-soc-pcm1792a-codec.o
obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
--- /dev/null
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm8x16_wcd_registers.h"
+#include "msm8x16-wcd.h"
+
+const u8 msm8x16_wcd_reg_readable[MSM8X16_WCD_CACHE_SIZE] = {
+ [MSM8X16_WCD_A_DIGITAL_REVISION1] = 1,
+ [MSM8X16_WCD_A_DIGITAL_REVISION2] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PERPH_TYPE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_RT_STS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_SET_TYPE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_POLARITY_HIGH] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_POLARITY_LOW] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_EN_SET] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_EN_CLR] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_LATCHED_STS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_PENDING_STS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_MID_SEL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_PRIORITY] = 1,
+ [MSM8X16_WCD_A_DIGITAL_GPIO_MODE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PIN_CTL_OE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PIN_CTL_DATA] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PIN_STATUS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_HDRIVE_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX1_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX2_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX3_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX_LB_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL1] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL2] = 1,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL3] = 1,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA0] = 1,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA1] = 1,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA2] = 1,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA3] = 1,
+ [MSM8X16_WCD_A_DIGITAL_DIG_DEBUG_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_SPARE_0] = 1,
+ [MSM8X16_WCD_A_DIGITAL_SPARE_1] = 1,
+ [MSM8X16_WCD_A_DIGITAL_SPARE_2] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION1] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION2] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION3] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION4] = 1,
+ [MSM8X16_WCD_A_ANALOG_PERPH_TYPE] = 1,
+ [MSM8X16_WCD_A_ANALOG_PERPH_SUBTYPE] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_RT_STS] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_SET_TYPE] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_POLARITY_HIGH] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_POLARITY_LOW] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_EN_SET] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_EN_CLR] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_LATCHED_STS] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_PENDING_STS] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_MID_SEL] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_PRIORITY] = 1,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_EN] = 1,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_VAL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_INT_RBIAS] = 1,
+ [MSM8X16_WCD_A_ANALOG_MICB_2_EN] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_1] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_2] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_FSM_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_DBNC_TIMER] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN0_ZDETL_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN1_ZDETM_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN2_ZDETH_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN3_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN4_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN_RESULT] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_ZDET_ELECT_RESULT] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_1_EN] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_2_EN] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_1] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_2] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_ATEST_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_TXFE_CLKDIV] = 1,
+ [MSM8X16_WCD_A_ANALOG_TX_3_EN] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_EN] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_CLK] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_DEGLITCH] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_FBCTRL] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_BIAS] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_VCTRL] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_TEST] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_CLOCK_DIVIDER] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_PA] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_LDO_OCP] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_CNP] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_TIME] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_EAR_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_ATEST] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_EAR_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_CLIP_DET] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_ANA_BIAS_SET] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_MISC] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG] = 1,
+ [MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT] = 1,
+ [MSM8X16_WCD_A_ANALOG_OUTPUT_VOLTAGE] = 1,
+ [MSM8X16_WCD_A_ANALOG_BYPASS_MODE] = 1,
+ [MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO] = 1,
+ [MSM8X16_WCD_A_ANALOG_RDSON_MAX_DUTY_CYCLE] = 1,
+ [MSM8X16_WCD_A_ANALOG_BOOST_TEST1_1] = 1,
+ [MSM8X16_WCD_A_ANALOG_BOOST_TEST_2] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_SAR_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_PBUS_ADD_CSR] = 1,
+ [MSM8X16_WCD_A_ANALOG_PBUS_ADD_SEL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_TX_RESET_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_DMIC_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_OTHR_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_MCLK_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_PDM_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_SD_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B4_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B4_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B4_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B5_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B5_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B5_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TOP_GAIN_UPDATE] = 1,
+ [MSM8X16_WCD_A_CDC_TOP_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_DEBUG_DESER1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_DEBUG_DESER2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_DEBUG_B1_CTL_CFG] = 1,
+ [MSM8X16_WCD_A_CDC_DEBUG_B2_CTL_CFG] = 1,
+ [MSM8X16_WCD_A_CDC_DEBUG_B3_CTL_CFG] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B4_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B4_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B5_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B5_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B7_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B7_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B8_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B8_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_TIMER_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_TIMER_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_COEF_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_COEF_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_COEF_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_COEF_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX2_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_RX3_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B4_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B2_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B3_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B4_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CONN_TX_I2S_SD1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TX1_VOL_CTL_TIMER] = 1,
+ [MSM8X16_WCD_A_CDC_TX2_VOL_CTL_TIMER] = 1,
+ [MSM8X16_WCD_A_CDC_TX1_VOL_CTL_GAIN] = 1,
+ [MSM8X16_WCD_A_CDC_TX2_VOL_CTL_GAIN] = 1,
+ [MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG] = 1,
+ [MSM8X16_WCD_A_CDC_TX2_VOL_CTL_CFG] = 1,
+ [MSM8X16_WCD_A_CDC_TX1_MUX_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TX2_MUX_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TX1_CLK_FS_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TX2_CLK_FS_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TX1_DMIC_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TX2_DMIC_CTL] = 1,
+ [MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_LATCHED_CLR] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_LATCHED_CLR] = 1,
+ [MSM8X16_WCD_A_ANALOG_NCP_CLIM_ADDR] = 1,
+ [MSM8X16_WCD_A_DIGITAL_SEC_ACCESS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL3] = 1,
+ [MSM8X16_WCD_A_ANALOG_SEC_ACCESS] = 1,
+};
+
+const u8 msm8x16_wcd_reg_readonly[MSM8X16_WCD_CACHE_SIZE] = {
+ [MSM8X16_WCD_A_DIGITAL_REVISION1] = 1,
+ [MSM8X16_WCD_A_DIGITAL_REVISION2] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PERPH_TYPE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_RT_STS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_SET_TYPE] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_POLARITY_HIGH] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_POLARITY_LOW] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_LATCHED_STS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_INT_PENDING_STS] = 1,
+ [MSM8X16_WCD_A_DIGITAL_PIN_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION1] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION2] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION3] = 1,
+ [MSM8X16_WCD_A_ANALOG_REVISION4] = 1,
+ [MSM8X16_WCD_A_ANALOG_PERPH_TYPE] = 1,
+ [MSM8X16_WCD_A_ANALOG_PERPH_SUBTYPE] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_RT_STS] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_SET_TYPE] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_POLARITY_HIGH] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_POLARITY_LOW] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_LATCHED_STS] = 1,
+ [MSM8X16_WCD_A_ANALOG_INT_PENDING_STS] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN_RESULT] = 1,
+ [MSM8X16_WCD_A_ANALOG_MBHC_ZDET_ELECT_RESULT] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_RX_EAR_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_SAR_STATUS] = 1,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_STATUS] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX1_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX2_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_RX3_B6_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG] = 1,
+ [MSM8X16_WCD_A_CDC_TX2_VOL_CTL_CFG] = 1,
+ [MSM8X16_WCD_A_CDC_IIR1_COEF_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_IIR2_COEF_B1_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_MCLK_CTL] = 1,
+ [MSM8X16_WCD_A_CDC_CLK_PDM_CTL] = 1,
+};
+
+u8 msm8x16_wcd_reset_reg_defaults[MSM8X16_WCD_CACHE_SIZE] = {
+ [MSM8X16_WCD_A_DIGITAL_REVISION1] =
+ MSM8X16_WCD_A_DIGITAL_REVISION1__POR,
+ [MSM8X16_WCD_A_DIGITAL_REVISION2] =
+ MSM8X16_WCD_A_DIGITAL_REVISION2__POR,
+ [MSM8X16_WCD_A_DIGITAL_PERPH_TYPE] =
+ MSM8X16_WCD_A_DIGITAL_PERPH_TYPE__POR,
+ [MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE] =
+ MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_RT_STS] =
+ MSM8X16_WCD_A_DIGITAL_INT_RT_STS__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_SET_TYPE] =
+ MSM8X16_WCD_A_DIGITAL_INT_SET_TYPE__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_POLARITY_HIGH] =
+ MSM8X16_WCD_A_DIGITAL_INT_POLARITY_HIGH__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_POLARITY_LOW] =
+ MSM8X16_WCD_A_DIGITAL_INT_POLARITY_LOW__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_LATCHED_CLR] =
+ MSM8X16_WCD_A_DIGITAL_INT_LATCHED_CLR__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_EN_SET] =
+ MSM8X16_WCD_A_DIGITAL_INT_EN_SET__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_EN_CLR] =
+ MSM8X16_WCD_A_DIGITAL_INT_EN_CLR__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_LATCHED_STS] =
+ MSM8X16_WCD_A_DIGITAL_INT_LATCHED_STS__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_PENDING_STS] =
+ MSM8X16_WCD_A_DIGITAL_INT_PENDING_STS__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_MID_SEL] =
+ MSM8X16_WCD_A_DIGITAL_INT_MID_SEL__POR,
+ [MSM8X16_WCD_A_DIGITAL_INT_PRIORITY] =
+ MSM8X16_WCD_A_DIGITAL_INT_PRIORITY__POR,
+ [MSM8X16_WCD_A_DIGITAL_GPIO_MODE] =
+ MSM8X16_WCD_A_DIGITAL_GPIO_MODE__POR,
+ [MSM8X16_WCD_A_DIGITAL_PIN_CTL_OE] =
+ MSM8X16_WCD_A_DIGITAL_PIN_CTL_OE__POR,
+ [MSM8X16_WCD_A_DIGITAL_PIN_CTL_DATA] =
+ MSM8X16_WCD_A_DIGITAL_PIN_CTL_DATA__POR,
+ [MSM8X16_WCD_A_DIGITAL_PIN_STATUS] =
+ MSM8X16_WCD_A_DIGITAL_PIN_STATUS__POR,
+ [MSM8X16_WCD_A_DIGITAL_HDRIVE_CTL] =
+ MSM8X16_WCD_A_DIGITAL_HDRIVE_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX1_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX1_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX2_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX2_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX3_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX3_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX_LB_CTL] =
+ MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX_LB_CTL__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL1] =
+ MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL1__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL2] =
+ MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL2__POR,
+ [MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL3] =
+ MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL3__POR,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA0] =
+ MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA0__POR,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA1] =
+ MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA1__POR,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA2] =
+ MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA2__POR,
+ [MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA3] =
+ MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA3__POR,
+ [MSM8X16_WCD_A_DIGITAL_SPARE_0] =
+ MSM8X16_WCD_A_DIGITAL_SPARE_0__POR,
+ [MSM8X16_WCD_A_DIGITAL_SPARE_1] =
+ MSM8X16_WCD_A_DIGITAL_SPARE_1__POR,
+ [MSM8X16_WCD_A_DIGITAL_SPARE_2] =
+ MSM8X16_WCD_A_DIGITAL_SPARE_2__POR,
+ [MSM8X16_WCD_A_ANALOG_REVISION1] =
+ MSM8X16_WCD_A_ANALOG_REVISION1__POR,
+ [MSM8X16_WCD_A_ANALOG_REVISION2] =
+ MSM8X16_WCD_A_ANALOG_REVISION2__POR,
+ [MSM8X16_WCD_A_ANALOG_REVISION3] =
+ MSM8X16_WCD_A_ANALOG_REVISION3__POR,
+ [MSM8X16_WCD_A_ANALOG_REVISION4] =
+ MSM8X16_WCD_A_ANALOG_REVISION4__POR,
+ [MSM8X16_WCD_A_ANALOG_PERPH_TYPE] =
+ MSM8X16_WCD_A_ANALOG_PERPH_TYPE__POR,
+ [MSM8X16_WCD_A_ANALOG_PERPH_SUBTYPE] =
+ MSM8X16_WCD_A_ANALOG_PERPH_SUBTYPE__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_RT_STS] =
+ MSM8X16_WCD_A_ANALOG_INT_RT_STS__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_SET_TYPE] =
+ MSM8X16_WCD_A_ANALOG_INT_SET_TYPE__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_POLARITY_HIGH] =
+ MSM8X16_WCD_A_ANALOG_INT_POLARITY_HIGH__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_POLARITY_LOW] =
+ MSM8X16_WCD_A_ANALOG_INT_POLARITY_LOW__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_LATCHED_CLR] =
+ MSM8X16_WCD_A_ANALOG_INT_LATCHED_CLR__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_EN_SET] =
+ MSM8X16_WCD_A_ANALOG_INT_EN_SET__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_EN_CLR] =
+ MSM8X16_WCD_A_ANALOG_INT_EN_CLR__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_LATCHED_STS] =
+ MSM8X16_WCD_A_ANALOG_INT_LATCHED_STS__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_PENDING_STS] =
+ MSM8X16_WCD_A_ANALOG_INT_PENDING_STS__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_MID_SEL] =
+ MSM8X16_WCD_A_ANALOG_INT_MID_SEL__POR,
+ [MSM8X16_WCD_A_ANALOG_INT_PRIORITY] =
+ MSM8X16_WCD_A_ANALOG_INT_PRIORITY__POR,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_EN] =
+ MSM8X16_WCD_A_ANALOG_MICB_1_EN__POR,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_VAL] =
+ MSM8X16_WCD_A_ANALOG_MICB_1_VAL__POR,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_CTL] =
+ MSM8X16_WCD_A_ANALOG_MICB_1_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_MICB_1_INT_RBIAS] =
+ MSM8X16_WCD_A_ANALOG_MICB_1_INT_RBIAS__POR,
+ [MSM8X16_WCD_A_ANALOG_MICB_2_EN] =
+ MSM8X16_WCD_A_ANALOG_MICB_2_EN__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_1] =
+ MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_1__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_2] =
+ MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_2__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_FSM_CTL] =
+ MSM8X16_WCD_A_ANALOG_MBHC_FSM_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_DBNC_TIMER] =
+ MSM8X16_WCD_A_ANALOG_MBHC_DBNC_TIMER__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN0_ZDETL_CTL] =
+ MSM8X16_WCD_A_ANALOG_MBHC_BTN0_ZDETL_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN1_ZDETM_CTL] =
+ MSM8X16_WCD_A_ANALOG_MBHC_BTN1_ZDETM_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN2_ZDETH_CTL] =
+ MSM8X16_WCD_A_ANALOG_MBHC_BTN2_ZDETH_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN3_CTL] =
+ MSM8X16_WCD_A_ANALOG_MBHC_BTN3_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN4_CTL] =
+ MSM8X16_WCD_A_ANALOG_MBHC_BTN4_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_BTN_RESULT] =
+ MSM8X16_WCD_A_ANALOG_MBHC_BTN_RESULT__POR,
+ [MSM8X16_WCD_A_ANALOG_MBHC_ZDET_ELECT_RESULT] =
+ MSM8X16_WCD_A_ANALOG_MBHC_ZDET_ELECT_RESULT__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_1_EN] =
+ MSM8X16_WCD_A_ANALOG_TX_1_EN__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_2_EN] =
+ MSM8X16_WCD_A_ANALOG_TX_2_EN__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_1] =
+ MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_1__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_2] =
+ MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_2__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_ATEST_CTL] =
+ MSM8X16_WCD_A_ANALOG_TX_1_2_ATEST_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS] =
+ MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_1_2_TXFE_CLKDIV] =
+ MSM8X16_WCD_A_ANALOG_TX_1_2_TXFE_CLKDIV__POR,
+ [MSM8X16_WCD_A_ANALOG_TX_3_EN] =
+ MSM8X16_WCD_A_ANALOG_TX_3_EN__POR,
+ [MSM8X16_WCD_A_ANALOG_NCP_EN] =
+ MSM8X16_WCD_A_ANALOG_NCP_EN__POR,
+ [MSM8X16_WCD_A_ANALOG_NCP_CLK] =
+ MSM8X16_WCD_A_ANALOG_NCP_CLK__POR,
+ [MSM8X16_WCD_A_ANALOG_NCP_DEGLITCH] =
+ MSM8X16_WCD_A_ANALOG_NCP_DEGLITCH__POR,
+ [MSM8X16_WCD_A_ANALOG_NCP_FBCTRL] =
+ MSM8X16_WCD_A_ANALOG_NCP_FBCTRL__POR,
+ [MSM8X16_WCD_A_ANALOG_NCP_BIAS] =
+ MSM8X16_WCD_A_ANALOG_NCP_BIAS__POR,
+ [MSM8X16_WCD_A_ANALOG_NCP_VCTRL] =
+ MSM8X16_WCD_A_ANALOG_NCP_VCTRL__POR,
+ [MSM8X16_WCD_A_ANALOG_NCP_TEST] =
+ MSM8X16_WCD_A_ANALOG_NCP_TEST__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_CLOCK_DIVIDER] =
+ MSM8X16_WCD_A_ANALOG_RX_CLOCK_DIVIDER__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL] =
+ MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT] =
+ MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC] =
+ MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_PA] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_PA__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_LDO_OCP] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_LDO_OCP__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_CNP] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_CNP__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_CTL] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_TIME] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_TIME__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_EAR_CTL] =
+ MSM8X16_WCD_A_ANALOG_RX_EAR_CTL___POR,
+ [MSM8X16_WCD_A_ANALOG_RX_ATEST] =
+ MSM8X16_WCD_A_ANALOG_RX_ATEST__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_HPH_STATUS] =
+ MSM8X16_WCD_A_ANALOG_RX_HPH_STATUS__POR,
+ [MSM8X16_WCD_A_ANALOG_RX_EAR_STATUS] =
+ MSM8X16_WCD_A_ANALOG_RX_EAR_STATUS__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL] =
+ MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_CLIP_DET] =
+ MSM8X16_WCD_A_ANALOG_SPKR_DRV_CLIP_DET__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL] =
+ MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_ANA_BIAS_SET] =
+ MSM8X16_WCD_A_ANALOG_SPKR_ANA_BIAS_SET__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL] =
+ MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL] =
+ MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_MISC] =
+ MSM8X16_WCD_A_ANALOG_SPKR_DRV_MISC__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG] =
+ MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG__POR,
+ [MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT] =
+ MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT__POR,
+ [MSM8X16_WCD_A_ANALOG_OUTPUT_VOLTAGE] =
+ MSM8X16_WCD_A_ANALOG_OUTPUT_VOLTAGE__POR,
+ [MSM8X16_WCD_A_ANALOG_BYPASS_MODE] =
+ MSM8X16_WCD_A_ANALOG_BYPASS_MODE__POR,
+ [MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL] =
+ MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL__POR,
+ [MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO] =
+ MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO__POR,
+ [MSM8X16_WCD_A_ANALOG_RDSON_MAX_DUTY_CYCLE] =
+ MSM8X16_WCD_A_ANALOG_RDSON_MAX_DUTY_CYCLE__POR,
+ [MSM8X16_WCD_A_ANALOG_BOOST_TEST1_1] =
+ MSM8X16_WCD_A_ANALOG_BOOST_TEST1_1__POR,
+ [MSM8X16_WCD_A_ANALOG_BOOST_TEST_2] =
+ MSM8X16_WCD_A_ANALOG_BOOST_TEST_2__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_SAR_STATUS] =
+ MSM8X16_WCD_A_ANALOG_SPKR_SAR_STATUS__POR,
+ [MSM8X16_WCD_A_ANALOG_SPKR_DRV_STATUS] =
+ MSM8X16_WCD_A_ANALOG_SPKR_DRV_STATUS__POR,
+ [MSM8X16_WCD_A_ANALOG_PBUS_ADD_CSR] =
+ MSM8X16_WCD_A_ANALOG_PBUS_ADD_CSR__POR,
+ [MSM8X16_WCD_A_ANALOG_PBUS_ADD_SEL] =
+ MSM8X16_WCD_A_ANALOG_PBUS_ADD_SEL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_TX_RESET_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_TX_RESET_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_DMIC_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_DMIC_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_OTHR_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_OTHR_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_MCLK_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_MCLK_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_PDM_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_PDM_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CLK_SD_CTL] =
+ MSM8X16_WCD_A_CDC_CLK_SD_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_B1_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_B1_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_B1_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_B2_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_B2_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_B2_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_B3_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_B3_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_B3_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_B4_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_B4_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_B4_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_B4_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_B4_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_B4_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_B5_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_B5_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_B5_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_B5_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_B5_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_B5_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_B6_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_B6_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_B6_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_B6_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_B6_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_B6_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B1_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B1_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B1_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL] =
+ MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL] =
+ MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL] =
+ MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_TOP_GAIN_UPDATE] =
+ MSM8X16_WCD_A_CDC_TOP_GAIN_UPDATE__POR,
+ [MSM8X16_WCD_A_CDC_TOP_CTL] =
+ MSM8X16_WCD_A_CDC_TOP_CTL__POR,
+ [MSM8X16_WCD_A_CDC_DEBUG_DESER1_CTL] =
+ MSM8X16_WCD_A_CDC_DEBUG_DESER1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_DEBUG_DESER2_CTL] =
+ MSM8X16_WCD_A_CDC_DEBUG_DESER2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_DEBUG_B1_CTL_CFG] =
+ MSM8X16_WCD_A_CDC_DEBUG_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_DEBUG_B2_CTL_CFG] =
+ MSM8X16_WCD_A_CDC_DEBUG_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_DEBUG_B3_CTL_CFG] =
+ MSM8X16_WCD_A_CDC_DEBUG_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B1_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B1_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B2_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B2_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B3_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B3_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B4_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B4_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B4_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B4_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B5_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B5_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B5_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B5_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B6_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B6_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B6_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B6_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B7_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B7_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B7_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B7_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_B8_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_B8_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_B8_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_B8_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_GAIN_TIMER_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_GAIN_TIMER_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_GAIN_TIMER_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_GAIN_TIMER_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_COEF_B1_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_COEF_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_COEF_B1_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_COEF_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR1_COEF_B2_CTL] =
+ MSM8X16_WCD_A_CDC_IIR1_COEF_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_IIR2_COEF_B2_CTL] =
+ MSM8X16_WCD_A_CDC_IIR2_COEF_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX2_B2_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX2_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_RX3_B2_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_RX3_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ1_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B2_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ1_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B3_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ1_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ1_B4_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ1_B4_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B1_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ2_B1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B2_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ2_B2_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B3_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ2_B3_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_EQ2_B4_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_EQ2_B4_CTL__POR,
+ [MSM8X16_WCD_A_CDC_CONN_TX_I2S_SD1_CTL] =
+ MSM8X16_WCD_A_CDC_CONN_TX_I2S_SD1_CTL__POR,
+ [MSM8X16_WCD_A_CDC_TX1_VOL_CTL_TIMER] =
+ MSM8X16_WCD_A_CDC_TX1_VOL_CTL_TIMER__POR,
+ [MSM8X16_WCD_A_CDC_TX2_VOL_CTL_TIMER] =
+ MSM8X16_WCD_A_CDC_TX2_VOL_CTL_TIMER__POR,
+ [MSM8X16_WCD_A_CDC_TX1_VOL_CTL_GAIN] =
+ MSM8X16_WCD_A_CDC_TX1_VOL_CTL_GAIN__POR,
+ [MSM8X16_WCD_A_CDC_TX2_VOL_CTL_GAIN] =
+ MSM8X16_WCD_A_CDC_TX2_VOL_CTL_GAIN__POR,
+ [MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG] =
+ MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG__POR,
+ [MSM8X16_WCD_A_CDC_TX2_VOL_CTL_CFG] =
+ MSM8X16_WCD_A_CDC_TX2_VOL_CTL_CFG__POR,
+ [MSM8X16_WCD_A_CDC_TX1_MUX_CTL] =
+ MSM8X16_WCD_A_CDC_TX1_MUX_CTL__POR,
+ [MSM8X16_WCD_A_CDC_TX2_MUX_CTL] =
+ MSM8X16_WCD_A_CDC_TX2_MUX_CTL__POR,
+ [MSM8X16_WCD_A_CDC_TX1_CLK_FS_CTL] =
+ MSM8X16_WCD_A_CDC_TX1_CLK_FS_CTL__POR,
+ [MSM8X16_WCD_A_CDC_TX2_CLK_FS_CTL] =
+ MSM8X16_WCD_A_CDC_TX2_CLK_FS_CTL__POR,
+ [MSM8X16_WCD_A_CDC_TX1_DMIC_CTL] =
+ MSM8X16_WCD_A_CDC_TX1_DMIC_CTL__POR,
+ [MSM8X16_WCD_A_CDC_TX2_DMIC_CTL] =
+ MSM8X16_WCD_A_CDC_TX2_DMIC_CTL__POR,
+};
--- /dev/null
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/regulator/consumer.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/tlv.h>
+
+#include "msm8x16-wcd.h"
+#include "msm8x16_wcd_registers.h"
+
+#define MSM8X16_WCD_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
+#define MSM8X16_WCD_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+
+#define TOMBAK_VERSION_1_0 0
+#define TOMBAK_IS_1_0(ver) \
+ ((ver == TOMBAK_VERSION_1_0) ? 1 : 0)
+
+#define HPHL_PA_DISABLE (0x01 << 1)
+#define HPHR_PA_DISABLE (0x01 << 2)
+#define EAR_PA_DISABLE (0x01 << 3)
+#define SPKR_PA_DISABLE (0x01 << 4)
+
+enum {
+ AIF1_PB = 0,
+ AIF1_CAP,
+ NUM_CODEC_DAIS,
+};
+
+static unsigned long rx_digital_gain_reg[] = {
+ MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
+ MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
+ MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
+};
+
+struct wcd_chip {
+ struct regmap *analog_map;
+ struct regmap *digital_map;
+ unsigned int analog_base;
+ u16 pmic_rev;
+ u16 codec_version;
+ bool spk_boost_set;
+ u32 mute_mask;
+ u32 rx_bias_count;
+ bool ear_pa_boost_set;
+ bool lb_mode;
+ struct clk *mclk;
+
+ struct regulator *vddio;
+ struct regulator *vdd_pa;
+ struct regulator *vdd_px;
+ struct regulator *vdd_cp;
+};
+
+
+static int msm8x16_wcd_volatile(struct snd_soc_codec *codec, unsigned int reg)
+{
+ return msm8x16_wcd_reg_readonly[reg];
+}
+
+static int msm8x16_wcd_readable(struct snd_soc_codec *ssc, unsigned int reg)
+{
+ return msm8x16_wcd_reg_readable[reg];
+}
+
+static int __msm8x16_wcd_reg_write(struct snd_soc_codec *codec,
+ unsigned short reg, u8 val)
+{
+ int ret = -EINVAL;
+ struct wcd_chip *chip = dev_get_drvdata(codec->dev);
+
+ if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
+ ret = regmap_write(chip->analog_map,
+ chip->analog_base + reg, val);
+ } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
+ u32 temp = val & 0x000000FF;
+ u16 offset = (reg ^ 0x0200) & 0x0FFF;
+
+ ret = regmap_write(chip->digital_map, offset, temp);
+ }
+
+ return ret;
+}
+
+static int msm8x16_wcd_write(struct snd_soc_codec *codec, unsigned int reg,
+ unsigned int value)
+{
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
+ if (!msm8x16_wcd_volatile(codec, reg))
+ msm8x16_wcd_reset_reg_defaults[reg] = value;
+
+ return __msm8x16_wcd_reg_write(codec, reg, (u8)value);
+}
+
+static int __msm8x16_wcd_reg_read(struct snd_soc_codec *codec,
+ unsigned short reg)
+{
+ int ret = -EINVAL;
+ u32 temp = 0;
+ struct wcd_chip *chip = dev_get_drvdata(codec->dev);
+
+ if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
+ ret = regmap_read(chip->analog_map,
+ chip->analog_base + reg, &temp);
+ } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
+ u32 val;
+ u16 offset = (reg ^ 0x0200) & 0x0FFF;
+
+ ret = regmap_read(chip->digital_map, offset, &val);
+ temp = (u8)val;
+ }
+
+ if (ret < 0) {
+ dev_err(codec->dev,
+ "%s: codec read failed for reg 0x%x\n",
+ __func__, reg);
+ return ret;
+ }
+
+ dev_dbg(codec->dev, "Read 0x%02x from 0x%x\n", temp, reg);
+
+ return temp;
+}
+
+
+static unsigned int msm8x16_wcd_read(struct snd_soc_codec *codec,
+ unsigned int reg)
+{
+ unsigned int val;
+
+ if (reg == SND_SOC_NOPM)
+ return 0;
+
+ BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
+
+ if (!msm8x16_wcd_volatile(codec, reg) &&
+ msm8x16_wcd_readable(codec, reg) &&
+ reg < codec->driver->reg_cache_size) {
+ return msm8x16_wcd_reset_reg_defaults[reg];
+ }
+
+ val = __msm8x16_wcd_reg_read(codec, reg);
+
+ return val;
+}
+
+static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults[] = {
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
+};
+
+static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults_2_0[] = {
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL3, 0x0F),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS, 0x4B),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x28),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0x69),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG, 0x01),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL, 0x5F),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO, 0x88),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3, 0x0F),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
+ MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
+};
+
+static int msm8x16_wcd_bringup(struct snd_soc_codec *codec)
+{
+ snd_soc_write(codec, MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL4, 0x01);
+ snd_soc_write(codec, MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL4, 0x01);
+ return 0;
+}
+
+static const struct msm8x16_wcd_reg_mask_val
+ msm8x16_wcd_codec_reg_init_val[] = {
+
+ /* Initialize current threshold to 350MA
+ * number of wait and run cycles to 4096
+ */
+ {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL, 0xFF, 0xD1},
+ {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT, 0xFF, 0xFF},
+};
+
+static void msm8x16_wcd_codec_init_reg(struct snd_soc_codec *codec)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_codec_reg_init_val); i++)
+ snd_soc_update_bits(codec,
+ msm8x16_wcd_codec_reg_init_val[i].reg,
+ msm8x16_wcd_codec_reg_init_val[i].mask,
+ msm8x16_wcd_codec_reg_init_val[i].val);
+}
+
+static void msm8x16_wcd_update_reg_defaults(struct snd_soc_codec *codec)
+{
+ u32 i;
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+ if (TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev)) {
+ for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults); i++)
+ snd_soc_write(codec, msm8x16_wcd_reg_defaults[i].reg,
+ msm8x16_wcd_reg_defaults[i].val);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults_2_0); i++)
+ snd_soc_write(codec,
+ msm8x16_wcd_reg_defaults_2_0[i].reg,
+ msm8x16_wcd_reg_defaults_2_0[i].val);
+ }
+}
+
+static int msm8x16_wcd_device_up(struct snd_soc_codec *codec)
+{
+ u32 reg;
+
+ dev_dbg(codec->dev, "%s: device up!\n", __func__);
+ msm8x16_wcd_bringup(codec);
+
+ for (reg = 0; reg < ARRAY_SIZE(msm8x16_wcd_reset_reg_defaults); reg++)
+ if (msm8x16_wcd_reg_readable[reg])
+ msm8x16_wcd_write(codec,
+ reg, msm8x16_wcd_reset_reg_defaults[reg]);
+
+ /* delay is required to make sure sound card state updated */
+ usleep_range(5000, 5100);
+
+ msm8x16_wcd_codec_init_reg(codec);
+ msm8x16_wcd_update_reg_defaults(codec);
+
+
+ return 0;
+}
+
+static int msm8x16_wcd_codec_enable_clock_block(struct snd_soc_codec *codec,
+ int enable)
+{
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+ unsigned long mclk_rate;
+
+ if (enable) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x03);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
+
+ mclk_rate = clk_get_rate(msm8x16_wcd->mclk);
+
+ if (mclk_rate == 12288000)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x00);
+ else if (mclk_rate == 9600000)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x01);
+ } else {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
+
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_codec_probe(struct snd_soc_codec *codec)
+{
+ struct wcd_chip *chip = dev_get_drvdata(codec->dev);
+ int err;
+
+ snd_soc_codec_set_drvdata(codec, chip);
+ chip->pmic_rev = snd_soc_read(codec, MSM8X16_WCD_A_DIGITAL_REVISION1);
+ dev_info(codec->dev, "%s :PMIC REV: %d", __func__,
+ chip->pmic_rev);
+
+ chip->codec_version = snd_soc_read(codec,
+ MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE);
+ dev_info(codec->dev, "%s :CODEC Version: %d", __func__,
+ chip->codec_version);
+
+ msm8x16_wcd_device_up(codec);
+
+ err = regulator_enable(chip->vddio);
+ if (err < 0) {
+ dev_err(codec->dev, "failed to enable VDD regulator\n");
+ return err;
+ }
+
+ err = regulator_enable(chip->vdd_pa);
+ if (err < 0) {
+ dev_err(codec->dev, "failed to enable VDD regulator\n");
+ return err;
+ }
+
+ msm8x16_wcd_codec_enable_clock_block(codec, 1);
+
+ return 0;
+}
+
+static int msm8x16_wcd_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
+ __func__,
+ substream->name, substream->stream);
+ return 0;
+}
+
+static void msm8x16_wcd_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ dev_dbg(dai->codec->dev,
+ "%s(): substream = %s stream = %d\n", __func__,
+ substream->name, substream->stream);
+}
+
+static int msm8x16_wcd_set_interpolator_rate(struct snd_soc_dai *dai,
+ u8 rx_fs_rate_reg_val, u32 sample_rate)
+{
+ return 0;
+}
+
+static int msm8x16_wcd_set_decimator_rate(struct snd_soc_dai *dai,
+ u8 tx_fs_rate_reg_val, u32 sample_rate)
+{
+ return 0;
+}
+
+static int msm8x16_wcd_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ u8 tx_fs_rate, rx_fs_rate;
+ int ret;
+
+ dev_dbg(dai->codec->dev,
+ "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n",
+ __func__, dai->name, dai->id, params_rate(params),
+ params_channels(params), params_format(params));
+
+ switch (params_rate(params)) {
+ case 8000:
+ tx_fs_rate = 0x00;
+ rx_fs_rate = 0x00;
+ break;
+ case 16000:
+ tx_fs_rate = 0x01;
+ rx_fs_rate = 0x20;
+ break;
+ case 32000:
+ tx_fs_rate = 0x02;
+ rx_fs_rate = 0x40;
+ break;
+ case 48000:
+ tx_fs_rate = 0x03;
+ rx_fs_rate = 0x60;
+ break;
+ case 96000:
+ tx_fs_rate = 0x04;
+ rx_fs_rate = 0x80;
+ break;
+ case 192000:
+ tx_fs_rate = 0x05;
+ rx_fs_rate = 0xA0;
+ break;
+ default:
+ dev_err(dai->codec->dev,
+ "%s: Invalid sampling rate %d\n", __func__,
+ params_rate(params));
+ return -EINVAL;
+ }
+
+ switch (substream->stream) {
+ case SNDRV_PCM_STREAM_CAPTURE:
+ ret = msm8x16_wcd_set_decimator_rate(dai, tx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ dev_err(dai->codec->dev,
+ "%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+ break;
+ case SNDRV_PCM_STREAM_PLAYBACK:
+ ret = msm8x16_wcd_set_interpolator_rate(dai, rx_fs_rate,
+ params_rate(params));
+ if (ret < 0) {
+ dev_err(dai->codec->dev,
+ "%s: set decimator rate failed %d\n", __func__,
+ ret);
+ return ret;
+ }
+ break;
+ default:
+ dev_err(dai->codec->dev,
+ "%s: Invalid stream type %d\n", __func__,
+ substream->stream);
+ return -EINVAL;
+ }
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ snd_soc_update_bits(dai->codec,
+ MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x20);
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ snd_soc_update_bits(dai->codec,
+ MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x00);
+ break;
+ default:
+ dev_err(dai->dev, "%s: wrong format selected\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int msm8x16_wcd_set_dai_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ dev_dbg(dai->codec->dev, "%s\n", __func__);
+ return 0;
+}
+
+static int msm8x16_wcd_set_channel_map(struct snd_soc_dai *dai,
+ unsigned int tx_num, unsigned int *tx_slot,
+ unsigned int rx_num, unsigned int *rx_slot)
+
+{
+ dev_dbg(dai->codec->dev, "%s\n", __func__);
+ return 0;
+}
+
+static int msm8x16_wcd_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ dev_dbg(dai->codec->dev, "%s\n", __func__);
+
+ return 0;
+}
+
+static struct snd_soc_dai_ops msm8x16_wcd_dai_ops = {
+ .startup = msm8x16_wcd_startup,
+ .shutdown = msm8x16_wcd_shutdown,
+ .hw_params = msm8x16_wcd_hw_params,
+ .set_sysclk = msm8x16_wcd_set_dai_sysclk,
+ .set_fmt = msm8x16_wcd_set_dai_fmt,
+ .set_channel_map = msm8x16_wcd_set_channel_map,
+};
+
+static struct snd_soc_dai_driver msm8x16_wcd_codec_dai[] = {
+ {
+ .name = "msm8x16_wcd_i2s_rx1",
+ .id = AIF1_PB,
+ .playback = {
+ .stream_name = "AIF1 Playback",
+ .rates = MSM8X16_WCD_RATES,
+ .formats = MSM8X16_WCD_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 3,
+ },
+ .ops = &msm8x16_wcd_dai_ops,
+ },
+ {
+ .name = "msm8x16_wcd_i2s_tx1",
+ .id = AIF1_CAP,
+ .capture = {
+ .stream_name = "AIF1 Capture",
+ .rates = MSM8X16_WCD_RATES,
+ .formats = MSM8X16_WCD_FORMATS,
+ .rate_max = 192000,
+ .rate_min = 8000,
+ .channels_min = 1,
+ .channels_max = 4,
+ },
+ .ops = &msm8x16_wcd_dai_ops,
+ },
+};
+
+static int msm8x16_wcd_codec_remove(struct snd_soc_codec *codec)
+{
+ /* TODO */
+ return 0;
+};
+
+
+static int msm8x16_wcd_spk_boost_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ struct wcd_chip *msm8x16_wcd = dev_get_drvdata(codec->dev);
+
+ if (msm8x16_wcd->spk_boost_set == false) {
+ ucontrol->value.integer.value[0] = 0;
+ } else if (msm8x16_wcd->spk_boost_set == true) {
+ ucontrol->value.integer.value[0] = 1;
+ } else {
+ dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n",
+ __func__, msm8x16_wcd->spk_boost_set);
+ return -EINVAL;
+ }
+
+ dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n", __func__,
+ msm8x16_wcd->spk_boost_set);
+ return 0;
+}
+
+static int msm8x16_wcd_spk_boost_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+
+ switch (ucontrol->value.integer.value[0]) {
+ case 0:
+ msm8x16_wcd->spk_boost_set = false;
+ break;
+ case 1:
+ msm8x16_wcd->spk_boost_set = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+ dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n",
+ __func__, msm8x16_wcd->spk_boost_set);
+ return 0;
+}
+
+static const char * const hph_text[] = {
+ "ZERO", "Switch",
+};
+
+static const struct soc_enum hph_enum =
+ SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(hph_text), hph_text);
+
+
+static const struct snd_kcontrol_new hphl_mux[] = {
+ SOC_DAPM_ENUM("HPHL", hph_enum)
+};
+
+static const struct snd_kcontrol_new hphr_mux[] = {
+ SOC_DAPM_ENUM("HPHR", hph_enum)
+};
+
+static const struct snd_kcontrol_new spkr_switch[] = {
+ SOC_DAPM_SINGLE("Switch",
+ MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 7, 1, 0)
+};
+
+static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
+static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
+
+static const struct snd_soc_dapm_route audio_map[] = {
+ {"RX_I2S_CLK", NULL, "CDC_CONN"},
+ {"I2S RX1", NULL, "RX_I2S_CLK"},
+ {"I2S RX2", NULL, "RX_I2S_CLK"},
+ {"I2S RX3", NULL, "RX_I2S_CLK"},
+
+ {"I2S TX1", NULL, "TX_I2S_CLK"},
+ {"I2S TX2", NULL, "TX_I2S_CLK"},
+
+ {"I2S TX1", NULL, "DEC1 MUX"},
+ {"I2S TX2", NULL, "DEC2 MUX"},
+
+ /* RDAC Connections */
+ {"HPHR DAC", NULL, "RDAC2 MUX"},
+ {"RDAC2 MUX", "RX1", "RX1 CHAIN"},
+ {"RDAC2 MUX", "RX2", "RX2 CHAIN"},
+
+ /* Earpiece (RX MIX1) */
+ {"EAR", NULL, "EAR_S"},
+ {"EAR_S", "Switch", "EAR PA"},
+ {"EAR PA", NULL, "RX_BIAS"},
+ {"EAR PA", NULL, "HPHL DAC"},
+ {"EAR PA", NULL, "HPHR DAC"},
+ {"EAR PA", NULL, "EAR CP"},
+
+ /* Headset (RX MIX1 and RX MIX2) */
+ {"HEADPHONE", NULL, "HPHL PA"},
+ {"HEADPHONE", NULL, "HPHR PA"},
+
+
+ {"HPHL PA", NULL, "HPHL"},
+ {"HPHR PA", NULL, "HPHR"},
+ {"HPHL", "Switch", "HPHL DAC"},
+ {"HPHR", "Switch", "HPHR DAC"},
+ {"HPHL PA", NULL, "CP"},
+ {"HPHL PA", NULL, "RX_BIAS"},
+ {"HPHR PA", NULL, "CP"},
+ {"HPHR PA", NULL, "RX_BIAS"},
+ {"HPHL DAC", NULL, "RX1 CHAIN"},
+
+ {"SPK_OUT", NULL, "SPK PA"},
+ {"SPK PA", NULL, "SPK_RX_BIAS"},
+ {"SPK PA", NULL, "SPK DAC"},
+ {"SPK DAC", "Switch", "RX3 CHAIN"},
+
+ {"RX1 CHAIN", NULL, "RX1 CLK"},
+ {"RX2 CHAIN", NULL, "RX2 CLK"},
+ {"RX3 CHAIN", NULL, "RX3 CLK"},
+ {"RX1 CHAIN", NULL, "RX1 MIX2"},
+ {"RX2 CHAIN", NULL, "RX2 MIX2"},
+ {"RX1 CHAIN", NULL, "RX1 MIX1"},
+ {"RX2 CHAIN", NULL, "RX2 MIX1"},
+ {"RX3 CHAIN", NULL, "RX3 MIX1"},
+
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
+ {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
+
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
+ {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
+
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
+ {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
+
+ {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
+ {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
+
+ {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
+ {"RX1 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
+ {"RX1 MIX1 INP2", "IIR1", "IIR1"},
+ {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
+ {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
+ {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
+
+ {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
+ {"RX2 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
+ {"RX2 MIX1 INP2", "IIR1", "IIR1"},
+
+ {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
+ {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
+ {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
+ {"RX3 MIX1 INP1", "IIR1", "IIR1"},
+ {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
+ {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
+ {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
+ {"RX3 MIX1 INP2", "IIR1", "IIR1"},
+
+ {"RX1 MIX2 INP1", "IIR1", "IIR1"},
+ {"RX2 MIX2 INP1", "IIR1", "IIR1"},
+
+ /* Decimator Inputs */
+ {"DEC1 MUX", "DMIC1", "DMIC1"},
+ {"DEC1 MUX", "DMIC2", "DMIC2"},
+ {"DEC1 MUX", "ADC1", "ADC1"},
+ {"DEC1 MUX", "ADC2", "ADC2"},
+ {"DEC1 MUX", "ADC3", "ADC3"},
+ {"DEC1 MUX", NULL, "CDC_CONN"},
+
+ {"DEC2 MUX", "DMIC1", "DMIC1"},
+ {"DEC2 MUX", "DMIC2", "DMIC2"},
+ {"DEC2 MUX", "ADC1", "ADC1"},
+ {"DEC2 MUX", "ADC2", "ADC2"},
+ {"DEC2 MUX", "ADC3", "ADC3"},
+ {"DEC2 MUX", NULL, "CDC_CONN"},
+
+ /* ADC Connections */
+ {"ADC2", NULL, "ADC2 MUX"},
+ {"ADC3", NULL, "ADC2 MUX"},
+ {"ADC2 MUX", "INP2", "ADC2_INP2"},
+ {"ADC2 MUX", "INP3", "ADC2_INP3"},
+
+ {"ADC1", NULL, "AMIC1"},
+ {"ADC2_INP2", NULL, "AMIC2"},
+ {"ADC2_INP3", NULL, "AMIC3"},
+
+ /* TODO: Fix this */
+ {"IIR1", NULL, "IIR1 INP1 MUX"},
+ {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
+ {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
+ {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
+ {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
+ {"MIC BIAS External", NULL, "INT_LDO_H"},
+ {"MIC BIAS External2", NULL, "INT_LDO_H"},
+ {"MIC BIAS Internal1", NULL, "MICBIAS_REGULATOR"},
+ {"MIC BIAS Internal2", NULL, "MICBIAS_REGULATOR"},
+ {"MIC BIAS External", NULL, "MICBIAS_REGULATOR"},
+ {"MIC BIAS External2", NULL, "MICBIAS_REGULATOR"},
+};
+
+static const char * const rx_mix1_text[] = {
+ "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
+};
+
+static const char * const rx_mix2_text[] = {
+ "ZERO", "IIR1", "IIR2"
+};
+
+static const char * const dec_mux_text[] = {
+ "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
+};
+
+static const char * const adc2_mux_text[] = {
+ "ZERO", "INP2", "INP3"
+};
+
+static const char * const rdac2_mux_text[] = {
+ "ZERO", "RX2", "RX1"
+};
+
+static const char * const iir1_inp1_text[] = {
+ "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
+};
+
+/* RX1 MIX1 */
+static const struct soc_enum rx_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
+ 0, 6, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
+ 3, 6, rx_mix1_text);
+
+static const struct soc_enum rx_mix1_inp3_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL,
+ 0, 6, rx_mix1_text);
+/* RX1 MIX2 */
+static const struct soc_enum rx_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL,
+ 0, 3, rx_mix2_text);
+
+/* RX2 MIX1 */
+static const struct soc_enum rx2_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
+ 0, 6, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
+ 3, 6, rx_mix1_text);
+
+static const struct soc_enum rx2_mix1_inp3_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
+ 0, 6, rx_mix1_text);
+
+/* RX2 MIX2 */
+static const struct soc_enum rx2_mix2_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL,
+ 0, 3, rx_mix2_text);
+
+/* RX3 MIX1 */
+static const struct soc_enum rx3_mix1_inp1_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
+ 0, 6, rx_mix1_text);
+
+static const struct soc_enum rx3_mix1_inp2_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
+ 3, 6, rx_mix1_text);
+
+static const struct soc_enum rdac2_mux_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL,
+ 0, 3, rdac2_mux_text);
+
+static const struct soc_enum rx3_mix1_inp3_chain_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
+ 0, 6, rx_mix1_text);
+static const struct snd_kcontrol_new rx_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rdac2_mux =
+ SOC_DAPM_ENUM("RDAC2 MUX Mux", rdac2_mux_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx_mix1_inp3_mux =
+ SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix1_inp3_mux =
+ SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
+
+static const struct snd_kcontrol_new rx3_mix1_inp3_mux =
+ SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum);
+
+static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
+
+static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
+ SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
+
+static const char * const msm8x16_wcd_loopback_mode_ctrl_text[] = {
+ "DISABLE", "ENABLE"};
+
+static const struct soc_enum msm8x16_wcd_loopback_mode_ctl_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_loopback_mode_ctrl_text),
+};
+
+static const char * const msm8x16_wcd_ear_pa_boost_ctrl_text[] = {
+ "DISABLE", "ENABLE"};
+static const struct soc_enum msm8x16_wcd_ear_pa_boost_ctl_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_boost_ctrl_text),
+};
+
+static const char * const msm8x16_wcd_ear_pa_gain_text[] = {
+ "POS_6_DB", "POS_1P5_DB"};
+static const struct soc_enum msm8x16_wcd_ear_pa_gain_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_gain_text),
+};
+
+static const char * const msm8x16_wcd_spk_boost_ctrl_text[] = {
+ "DISABLE", "ENABLE"};
+static const struct soc_enum msm8x16_wcd_spk_boost_ctl_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_spk_boost_ctrl_text),
+};
+
+/*cut of frequency for high pass filter*/
+static const char * const cf_text[] = {
+ "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
+};
+
+static const struct soc_enum cf_dec1_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_dec2_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
+
+static const struct soc_enum cf_rxmix1_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX1_B4_CTL, 0, 3, cf_text);
+
+static const struct soc_enum cf_rxmix2_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX2_B4_CTL, 0, 3, cf_text);
+
+static const struct soc_enum cf_rxmix3_enum =
+ SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX3_B4_CTL, 0, 3, cf_text);
+
+static const struct snd_kcontrol_new msm8x16_wcd_snd_controls[] = {
+
+ SOC_ENUM_EXT("Speaker Boost", msm8x16_wcd_spk_boost_ctl_enum[0],
+ msm8x16_wcd_spk_boost_get, msm8x16_wcd_spk_boost_set),
+
+ SOC_SINGLE_TLV("ADC1 Volume", MSM8X16_WCD_A_ANALOG_TX_1_EN, 3,
+ 8, 0, analog_gain),
+ SOC_SINGLE_TLV("ADC2 Volume", MSM8X16_WCD_A_ANALOG_TX_2_EN, 3,
+ 8, 0, analog_gain),
+ SOC_SINGLE_TLV("ADC3 Volume", MSM8X16_WCD_A_ANALOG_TX_3_EN, 3,
+ 8, 0, analog_gain),
+
+ SOC_SINGLE_SX_TLV("RX1 Digital Volume",
+ MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
+ 0, -84, 40, digital_gain),
+ SOC_SINGLE_SX_TLV("RX2 Digital Volume",
+ MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
+ 0, -84, 40, digital_gain),
+ SOC_SINGLE_SX_TLV("RX3 Digital Volume",
+ MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
+ 0, -84, 40, digital_gain),
+
+ SOC_SINGLE("RX1 HPF Switch",
+ MSM8X16_WCD_A_CDC_RX1_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX2 HPF Switch",
+ MSM8X16_WCD_A_CDC_RX2_B5_CTL, 2, 1, 0),
+ SOC_SINGLE("RX3 HPF Switch",
+ MSM8X16_WCD_A_CDC_RX3_B5_CTL, 2, 1, 0),
+
+ SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
+ SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
+ SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
+};
+
+
+static const struct snd_kcontrol_new ear_pa_switch[] = {
+ SOC_DAPM_SINGLE("Switch",
+ MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 5, 1, 0)
+};
+
+static int msm8x16_wcd_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ dev_dbg(codec->dev,
+ "%s: Sleeping 20ms after select EAR PA\n",
+ __func__);
+ snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
+ 0x80, 0x80);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ dev_dbg(codec->dev,
+ "%s: Sleeping 20ms after enabling EAR PA\n",
+ __func__);
+ snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
+ 0x40, 0x40);
+ usleep_range(7000, 7100);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
+ msleep(20);
+ msm8x16_wcd->mute_mask |= EAR_PA_DISABLE;
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ dev_dbg(codec->dev,
+ "%s: Sleeping 7ms after disabling EAR PA\n",
+ __func__);
+ snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
+ 0x40, 0x00);
+ usleep_range(7000, 7100);
+ /*
+ * Reset pa select bit from ear to hph after ear pa
+ * is disabled to reduce ear turn off pop
+ */
+ snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
+ 0x80, 0x00);
+ break;
+ }
+ return 0;
+}
+
+
+static int msm8x16_wcd_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01);
+ if (!msm8x16_wcd->spk_boost_set)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x10);
+ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0);
+ if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x01);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
+ if (msm8x16_wcd->spk_boost_set)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0xEF);
+ else
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
+ snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
+ break;
+ case SND_SOC_DAPM_PRE_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x01);
+ msleep(20);
+ msm8x16_wcd->mute_mask |= SPKR_PA_DISABLE;
+ snd_soc_update_bits(codec, w->reg, 0x80, 0x00);
+ if (msm8x16_wcd->spk_boost_set)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0x00);
+ else
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0x00);
+ if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x00);
+ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol,
+ int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ /* apply the digital gain after the interpolator is enabled*/
+ if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
+ snd_soc_write(codec,
+ rx_digital_gain_reg[w->shift],
+ snd_soc_read(codec,
+ rx_digital_gain_reg[w->shift])
+ );
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 1 << w->shift);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
+ 1 << w->shift, 0x0);
+ /*
+ * disable the mute enabled during the PMD of this device
+ */
+ if (msm8x16_wcd->mute_mask & HPHL_PA_DISABLE) {
+ pr_debug("disabling HPHL mute\n");
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
+ msm8x16_wcd->mute_mask &= ~(HPHL_PA_DISABLE);
+ }
+ if (msm8x16_wcd->mute_mask & HPHR_PA_DISABLE) {
+ pr_debug("disabling HPHR mute\n");
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
+ msm8x16_wcd->mute_mask &= ~(HPHR_PA_DISABLE);
+ }
+ if (msm8x16_wcd->mute_mask & SPKR_PA_DISABLE) {
+ pr_debug("disabling SPKR mute\n");
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
+ msm8x16_wcd->mute_mask &= ~(SPKR_PA_DISABLE);
+ }
+ if (msm8x16_wcd->mute_mask & EAR_PA_DISABLE) {
+ pr_debug("disabling EAR mute\n");
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
+ msm8x16_wcd->mute_mask &= ~(EAR_PA_DISABLE);
+ }
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (w->shift == 2)
+ snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
+ if (msm8x16_wcd->spk_boost_set) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
+ 0xA5, 0xA5);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
+ 0x0F, 0x0F);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
+ 0x82, 0x82);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x20, 0x20);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
+ 0xDF, 0xDF);
+ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
+ 0x83, 0x83);
+ } else if (msm8x16_wcd->ear_pa_boost_set) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
+ 0xA5, 0xA5);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
+ 0x07, 0x07);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
+ 0x40, 0x40);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
+ 0x80, 0x80);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
+ 0x02, 0x02);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
+ 0xDF, 0xDF);
+ } else {
+ snd_soc_update_bits(codec, w->reg, 1<<w->shift,
+ 1<<w->shift);
+ }
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ if (msm8x16_wcd->spk_boost_set) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
+ 0xDF, 0x5F);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x20, 0x00);
+ } else if (msm8x16_wcd->ear_pa_boost_set) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
+ 0x80, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
+ 0x80, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
+ 0x02, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
+ 0x40, 0x00);
+ } else {
+ snd_soc_update_bits(codec, w->reg, 1<<w->shift, 0x00);
+ }
+ break;
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_codec_enable_rx_chain(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x80, 0x80);
+ dev_dbg(codec->dev,
+ "%s: PMU:Sleeping 20ms after disabling mute\n",
+ __func__);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x80, 0x00);
+ dev_dbg(codec->dev,
+ "%s: PMD:Sleeping 20ms after disabling mute\n",
+ __func__);
+ snd_soc_update_bits(codec, w->reg,
+ 1 << w->shift, 0x00);
+ msleep(20);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ msm8x16_wcd->rx_bias_count++;
+ if (msm8x16_wcd->rx_bias_count == 1)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
+ 0x81, 0x81);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ msm8x16_wcd->rx_bias_count--;
+ if (msm8x16_wcd->rx_bias_count == 0)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
+ 0x81, 0x00);
+ break;
+ }
+ dev_dbg(codec->dev, "%s rx_bias_count = %d\n",
+ __func__, msm8x16_wcd->rx_bias_count);
+ return 0;
+}
+
+static int msm8x16_wcd_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (!(strcmp(w->name, "EAR CP")))
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x80, 0x80);
+ else
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0xC0, 0xC0);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
+ if (!(strcmp(w->name, "EAR CP")))
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x80, 0x00);
+ else {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x40, 0x00);
+ if (msm8x16_wcd->rx_bias_count == 0)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0x80, 0x00);
+ dev_dbg(codec->dev, "%s: rx_bias_count = %d\n",
+ __func__, msm8x16_wcd->rx_bias_count);
+ }
+ break;
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_hphl_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_hph_pa_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ if (w->shift == 5) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x04);
+ } else if (w->shift == 4) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x04);
+ }
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x20, 0x20);
+ break;
+
+ case SND_SOC_DAPM_POST_PMU:
+ usleep_range(4000, 4100);
+ if (w->shift == 5)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
+ else if (w->shift == 4)
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
+ usleep_range(10000, 10100);
+ break;
+
+ case SND_SOC_DAPM_PRE_PMD:
+ if (w->shift == 5) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
+ msleep(20);
+ msm8x16_wcd->mute_mask |= HPHL_PA_DISABLE;
+ } else if (w->shift == 4) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x01);
+ msleep(20);
+ msm8x16_wcd->mute_mask |= HPHR_PA_DISABLE;
+ }
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ if (w->shift == 5) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x00);
+
+ } else if (w->shift == 4) {
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x00);
+ }
+ usleep_range(4000, 4100);
+
+ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
+ dev_dbg(codec->dev,
+ "%s: sleep 10 ms after %s PA disable.\n", __func__,
+ w->name);
+ usleep_range(10000, 10100);
+ break;
+ }
+ return 0;
+}
+
+static int msm8x16_wcd_hphr_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
+ snd_soc_update_bits(codec,
+ MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00);
+ break;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget msm8x16_wcd_dapm_widgets[] = {
+ /*RX stuff */
+ SND_SOC_DAPM_OUTPUT("EAR"),
+
+ SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
+ 0, 0, NULL, 0, msm8x16_wcd_codec_enable_ear_pa,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER("EAR_S", SND_SOC_NOPM, 0, 0,
+ ear_pa_switch, ARRAY_SIZE(ear_pa_switch)),
+
+ SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+
+ SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
+
+ SND_SOC_DAPM_OUTPUT("HEADPHONE"),
+ SND_SOC_DAPM_PGA_E("HPHL PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
+ 5, 0, NULL, 0,
+ msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, hphl_mux),
+
+ SND_SOC_DAPM_MIXER_E("HPHL DAC",
+ MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
+ 0, msm8x16_wcd_hphl_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_PGA_E("HPHR PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
+ 4, 0, NULL, 0,
+ msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
+ SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, hphr_mux),
+
+ SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
+ spkr_switch, ARRAY_SIZE(spkr_switch)),
+
+ SND_SOC_DAPM_MIXER_E("HPHR DAC",
+ MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
+ 0, msm8x16_wcd_hphr_dac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+ /* Speaker */
+ SND_SOC_DAPM_OUTPUT("SPK_OUT"),
+
+ SND_SOC_DAPM_PGA_E("SPK PA", MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL,
+ 6, 0, NULL, 0, msm8x16_wcd_codec_enable_spk_pa,
+ SND_SOC_DAPM_PRE_REG|
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER_E("RX1 MIX1",
+ MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL, 0,
+ msm8x16_wcd_codec_enable_interpolator,
+ SND_SOC_DAPM_PRE_REG|
+ SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD|
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER_E("RX2 MIX1",
+ MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL, 0,
+ msm8x16_wcd_codec_enable_interpolator,
+ SND_SOC_DAPM_PRE_REG|
+ SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MIXER_E("RX1 MIX2",
+ MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
+ 0, msm8x16_wcd_codec_enable_interpolator,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER_E("RX2 MIX2",
+ MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
+ 0, msm8x16_wcd_codec_enable_interpolator,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER_E("RX3 MIX1",
+ MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
+ 0, msm8x16_wcd_codec_enable_interpolator,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY("RX1 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 0, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RX2 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 1, 0, NULL, 0),
+ SND_SOC_DAPM_SUPPLY("RX3 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
+ 2, 0, msm8x16_wcd_codec_enable_dig_clk, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER_E("RX1 CHAIN", MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0, 0,
+ NULL, 0,
+ msm8x16_wcd_codec_enable_rx_chain,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER_E("RX2 CHAIN", MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0, 0,
+ NULL, 0,
+ msm8x16_wcd_codec_enable_rx_chain,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MIXER_E("RX3 CHAIN", MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0, 0,
+ NULL, 0,
+ msm8x16_wcd_codec_enable_rx_chain,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx_mix1_inp3_mux),
+
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx2_mix1_inp3_mux),
+
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp1_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp2_mux),
+ SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
+ &rx3_mix1_inp3_mux),
+
+ SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx1_mix2_inp1_mux),
+ SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
+ &rx2_mix2_inp1_mux),
+ SND_SOC_DAPM_SUPPLY("CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 0, 0,
+ msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY("EAR CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 4, 0,
+ msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM,
+ 0, 0, msm8x16_wcd_codec_enable_rx_bias,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ SND_SOC_DAPM_SUPPLY("SPK_RX_BIAS",
+ SND_SOC_NOPM, 0, 0,
+ msm8x16_wcd_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
+ SND_SOC_DAPM_SUPPLY("RX_I2S_CLK",
+ MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 4, 0, NULL, 0),
+};
+
+
+static struct snd_soc_codec_driver msm8x16_wcd_codec = {
+ .probe = msm8x16_wcd_codec_probe,
+ .remove = msm8x16_wcd_codec_remove,
+ .read = msm8x16_wcd_read,
+ .write = msm8x16_wcd_write,
+ .reg_cache_size = MSM8X16_WCD_CACHE_SIZE,
+ .reg_cache_default = msm8x16_wcd_reset_reg_defaults,
+ .reg_word_size = 1,
+ .controls = msm8x16_wcd_snd_controls,
+ .num_controls = ARRAY_SIZE(msm8x16_wcd_snd_controls),
+ .dapm_widgets = msm8x16_wcd_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(msm8x16_wcd_dapm_widgets),
+ .dapm_routes = audio_map,
+ .num_dapm_routes = ARRAY_SIZE(audio_map),
+};
+
+static int msm8x16_wcd_codec_parse_dt(struct platform_device *pdev,
+ struct wcd_chip *chip)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+ u32 res[2];
+
+ ret = of_property_read_u32_array(np, "reg", res, 2);
+ if (ret < 0)
+ return ret;
+
+ chip->analog_base = res[0];
+
+ chip->digital_map = syscon_regmap_lookup_by_phandle(np, "digital");
+ if (IS_ERR(chip->digital_map))
+ return PTR_ERR(chip->digital_map);
+
+ chip->vddio = devm_regulator_get(dev, "vddio");
+ if (IS_ERR(chip->vddio)) {
+ dev_err(dev, "Failed to get vdd supply\n");
+ return PTR_ERR(chip->vddio);
+ }
+
+ chip->vdd_pa = devm_regulator_get(dev, "vdd-pa");
+ if (IS_ERR(chip->vdd_pa)) {
+ dev_err(dev, "Failed to get vdd supply\n");
+ return PTR_ERR(chip->vdd_pa);
+ }
+
+ chip->mclk = devm_clk_get(dev, "mclk");
+
+ return 0;
+}
+
+static int wcd_probe(struct platform_device *pdev)
+{
+ struct wcd_chip *chip;
+ struct device *dev = &pdev->dev;
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->analog_map = dev_get_regmap(dev->parent, NULL);
+ if (!chip->analog_map)
+ return -ENXIO;
+
+ msm8x16_wcd_codec_parse_dt(pdev, chip);
+ clk_set_rate(chip->mclk, 9600000);
+ clk_prepare_enable(chip->mclk);
+
+ dev_set_drvdata(dev, chip);
+
+ return snd_soc_register_codec(dev, &msm8x16_wcd_codec,
+ msm8x16_wcd_codec_dai,
+ ARRAY_SIZE(msm8x16_wcd_codec_dai));
+}
+
+static int wcd_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id wcd_match_table[] = {
+ { .compatible = "qcom,apq8016-wcd-codec" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, wcd_match_table);
+
+static struct platform_driver wcd_driver = {
+ .driver = {
+ .name = "spmi-wcd-codec",
+ .of_match_table = wcd_match_table,
+ },
+ .probe = wcd_probe,
+ .remove = wcd_remove,
+};
+module_platform_driver(wcd_driver);
+
+MODULE_ALIAS("platform:spmi-wcd-codec");
+MODULE_DESCRIPTION("SPMI PMIC WCD codec driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef MSM8X16_WCD_H
+#define MSM8X16_WCD_H
+
+#include <linux/types.h>
+
+#define MSM8X16_WCD_NUM_REGISTERS 0x6FF
+#define MSM8X16_WCD_MAX_REGISTER (MSM8X16_WCD_NUM_REGISTERS-1)
+#define MSM8X16_WCD_CACHE_SIZE MSM8X16_WCD_NUM_REGISTERS
+#define MSM8X16_WCD_NUM_IRQ_REGS 2
+#define MAX_REGULATOR 7
+#define MSM8X16_WCD_REG_VAL(reg, val) {reg, 0, val}
+#define MSM8X16_TOMBAK_LPASS_AUDIO_CORE_DIG_CODEC_CLK_SEL 0xFE03B004
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CMD_RCGR 0x0181C09C
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CFG_RCGR 0x0181C0A0
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_M 0x0181C0A4
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_N 0x0181C0A8
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_D 0x0181C0AC
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CBCR 0x0181C0B0
+#define MSM8X16_TOMBAK_LPASS_DIGCODEC_AHB_CBCR 0x0181C0B4
+
+#define MSM8X16_CODEC_NAME "msm8x16_wcd_codec"
+
+#define MSM8X16_WCD_IS_DIGITAL_REG(reg) \
+ (((reg >= 0x200) && (reg <= 0x4FF)) ? 1 : 0)
+#define MSM8X16_WCD_IS_TOMBAK_REG(reg) \
+ (((reg >= 0x000) && (reg <= 0x1FF)) ? 1 : 0)
+/*
+ * MCLK activity indicators during suspend and resume call
+ */
+#define MCLK_SUS_DIS 1
+#define MCLK_SUS_RSC 2
+#define MCLK_SUS_NO_ACT 3
+
+#define NUM_DECIMATORS 2
+
+extern const u8 msm8x16_wcd_reg_readable[MSM8X16_WCD_CACHE_SIZE];
+extern const u8 msm8x16_wcd_reg_readonly[MSM8X16_WCD_CACHE_SIZE];
+extern u8 msm8x16_wcd_reset_reg_defaults[MSM8X16_WCD_CACHE_SIZE];
+
+enum msm8x16_wcd_pid_current {
+ MSM8X16_WCD_PID_MIC_2P5_UA,
+ MSM8X16_WCD_PID_MIC_5_UA,
+ MSM8X16_WCD_PID_MIC_10_UA,
+ MSM8X16_WCD_PID_MIC_20_UA,
+};
+
+struct msm8x16_wcd_reg_mask_val {
+ u16 reg;
+ u8 mask;
+ u8 val;
+};
+
+enum msm8x16_wcd_mbhc_analog_pwr_cfg {
+ MSM8X16_WCD_ANALOG_PWR_COLLAPSED = 0,
+ MSM8X16_WCD_ANALOG_PWR_ON,
+ MSM8X16_WCD_NUM_ANALOG_PWR_CONFIGS,
+};
+
+/* Number of input and output I2S port */
+enum {
+ MSM8X16_WCD_RX1 = 0,
+ MSM8X16_WCD_RX2,
+ MSM8X16_WCD_RX3,
+ MSM8X16_WCD_RX_MAX,
+};
+
+enum {
+ MSM8X16_WCD_TX1 = 0,
+ MSM8X16_WCD_TX2,
+ MSM8X16_WCD_TX3,
+ MSM8X16_WCD_TX4,
+ MSM8X16_WCD_TX_MAX,
+};
+
+enum {
+ /* INTR_REG 0 - Digital Periph */
+ MSM8X16_WCD_IRQ_SPKR_CNP = 0,
+ MSM8X16_WCD_IRQ_SPKR_CLIP,
+ MSM8X16_WCD_IRQ_SPKR_OCP,
+ MSM8X16_WCD_IRQ_MBHC_INSREM_DET1,
+ MSM8X16_WCD_IRQ_MBHC_RELEASE,
+ MSM8X16_WCD_IRQ_MBHC_PRESS,
+ MSM8X16_WCD_IRQ_MBHC_INSREM_DET,
+ MSM8X16_WCD_IRQ_MBHC_HS_DET,
+ /* INTR_REG 1 - Analog Periph */
+ MSM8X16_WCD_IRQ_EAR_OCP,
+ MSM8X16_WCD_IRQ_HPHR_OCP,
+ MSM8X16_WCD_IRQ_HPHL_OCP,
+ MSM8X16_WCD_IRQ_EAR_CNP,
+ MSM8X16_WCD_IRQ_HPHR_CNP,
+ MSM8X16_WCD_IRQ_HPHL_CNP,
+ MSM8X16_WCD_NUM_IRQS,
+};
+
+enum wcd_notify_event {
+ WCD_EVENT_INVALID,
+ /* events for micbias ON and OFF */
+ WCD_EVENT_PRE_MICBIAS_2_OFF,
+ WCD_EVENT_POST_MICBIAS_2_OFF,
+ WCD_EVENT_PRE_MICBIAS_2_ON,
+ WCD_EVENT_POST_MICBIAS_2_ON,
+ /* events for PA ON and OFF */
+ WCD_EVENT_PRE_HPHL_PA_ON,
+ WCD_EVENT_POST_HPHL_PA_OFF,
+ WCD_EVENT_PRE_HPHR_PA_ON,
+ WCD_EVENT_POST_HPHR_PA_OFF,
+ WCD_EVENT_LAST,
+};
+
+enum {
+ ON_DEMAND_MICBIAS = 0,
+ ON_DEMAND_SUPPLIES_MAX,
+};
+
+/*
+ * The delay list is per codec HW specification.
+ * Please add delay in the list in the future instead
+ * of magic number
+ */
+enum {
+ CODEC_DELAY_1_MS = 1000,
+ CODEC_DELAY_1_1_MS = 1100,
+};
+#if 0
+struct msm8x16_wcd_regulator {
+ const char *name;
+ int min_uv;
+ int max_uv;
+ int optimum_ua;
+ bool ondemand;
+ struct regulator *regulator;
+};
+
+struct msm8916_asoc_mach_data {
+ int codec_type;
+ int ext_pa;
+ int us_euro_gpio;
+ int mclk_freq;
+ int lb_mode;
+ atomic_t mclk_rsc_ref;
+ atomic_t mclk_enabled;
+ struct mutex cdc_mclk_mutex;
+ struct delayed_work disable_mclk_work;
+ struct afe_digital_clk_cfg digital_cdc_clk;
+};
+
+struct msm8x16_wcd_pdata {
+ int irq;
+ int irq_base;
+ int num_irqs;
+ int reset_gpio;
+ void *msm8x16_wcd_ahb_base_vaddr;
+ struct wcd9xxx_micbias_setting micbias;
+ struct msm8x16_wcd_regulator regulator[MAX_REGULATOR];
+ u32 mclk_rate;
+};
+
+enum msm8x16_wcd_micbias_num {
+ MSM8X16_WCD_MICBIAS1 = 0,
+};
+
+struct msm8x16_wcd {
+ struct device *dev;
+ struct mutex io_lock;
+ u8 version;
+
+ int reset_gpio;
+ int (*read_dev)(struct snd_soc_codec *codec,
+ unsigned short reg);
+ int (*write_dev)(struct snd_soc_codec *codec,
+ unsigned short reg, u8 val);
+
+ u32 num_of_supplies;
+ struct regulator_bulk_data *supplies;
+
+ u8 idbyte[4];
+
+ int num_irqs;
+ u32 mclk_rate;
+ char __iomem *dig_base;
+};
+
+struct on_demand_supply {
+ struct regulator *supply;
+ atomic_t ref;
+};
+
+struct msm8x16_wcd_priv {
+ struct snd_soc_codec *codec;
+ u16 pmic_rev;
+ u32 adc_count;
+ u32 rx_bias_count;
+ s32 dmic_1_2_clk_cnt;
+ u32 mute_mask;
+ bool mclk_enabled;
+ bool clock_active;
+ bool config_mode_active;
+ bool spk_boost_set;
+ bool ear_pa_boost_set;
+ bool dec_active[NUM_DECIMATORS];
+ struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX];
+ /* mbhc module */
+ struct wcd_mbhc mbhc;
+ struct blocking_notifier_head notifier;
+
+};
+
+extern int msm8x16_wcd_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
+ bool dapm);
+
+extern int msm8x16_wcd_hs_detect(struct snd_soc_codec *codec,
+ struct wcd_mbhc_config *mbhc_cfg);
+
+extern void msm8x16_wcd_hs_detect_exit(struct snd_soc_codec *codec);
+
+extern int msm8x16_register_notifier(struct snd_soc_codec *codec,
+ struct notifier_block *nblock);
+
+extern int msm8x16_unregister_notifier(struct snd_soc_codec *codec,
+ struct notifier_block *nblock);
+#endif
+#endif
+
--- /dev/null
+ /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef MSM8X16_WCD_REGISTERS_H
+#define MSM8X16_WCD_REGISTERS_H
+
+#define MSM8X16_WCD_A_DIGITAL_REVISION1 (0x000)
+#define MSM8X16_WCD_A_DIGITAL_REVISION1__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_REVISION2 (0x001)
+#define MSM8X16_WCD_A_DIGITAL_REVISION2__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_TYPE (0x004)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_TYPE__POR (0x23)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE (0x005)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE__POR (0x01)
+#define MSM8X16_WCD_A_DIGITAL_INT_RT_STS (0x010)
+#define MSM8X16_WCD_A_DIGITAL_INT_RT_STS__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_SET_TYPE (0x011)
+#define MSM8X16_WCD_A_DIGITAL_INT_SET_TYPE__POR (0xFF)
+#define MSM8X16_WCD_A_DIGITAL_INT_POLARITY_HIGH (0x012)
+#define MSM8X16_WCD_A_DIGITAL_INT_POLARITY_HIGH__POR (0xFF)
+#define MSM8X16_WCD_A_DIGITAL_INT_POLARITY_LOW (0x013)
+#define MSM8X16_WCD_A_DIGITAL_INT_POLARITY_LOW__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_LATCHED_CLR (0x014)
+#define MSM8X16_WCD_A_DIGITAL_INT_LATCHED_CLR__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_EN_SET (0x015)
+#define MSM8X16_WCD_A_DIGITAL_INT_EN_SET__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_EN_CLR (0x016)
+#define MSM8X16_WCD_A_DIGITAL_INT_EN_CLR__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_LATCHED_STS (0x018)
+#define MSM8X16_WCD_A_DIGITAL_INT_LATCHED_STS__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_PENDING_STS (0x019)
+#define MSM8X16_WCD_A_DIGITAL_INT_PENDING_STS__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_MID_SEL (0x01A)
+#define MSM8X16_WCD_A_DIGITAL_INT_MID_SEL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_PRIORITY (0x01B)
+#define MSM8X16_WCD_A_DIGITAL_INT_PRIORITY__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_GPIO_MODE (0x040)
+#define MSM8X16_WCD_A_DIGITAL_GPIO_MODE__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_PIN_CTL_OE (0x041)
+#define MSM8X16_WCD_A_DIGITAL_PIN_CTL_OE__POR (0x01)
+#define MSM8X16_WCD_A_DIGITAL_PIN_CTL_DATA (0x042)
+#define MSM8X16_WCD_A_DIGITAL_PIN_CTL_DATA__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_PIN_STATUS (0x043)
+#define MSM8X16_WCD_A_DIGITAL_PIN_STATUS__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_HDRIVE_CTL (0x044)
+#define MSM8X16_WCD_A_DIGITAL_HDRIVE_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL (0x046)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL (0x048)
+#define MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL (0x049)
+#define MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL (0x04A)
+#define MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL (0x050)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL__POR (0x02)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL (0x051)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL__POR (0x02)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL (0x052)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX1_CTL (0x053)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX2_CTL (0x054)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX3_CTL (0x055)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX_LB_CTL (0x056)
+#define MSM8X16_WCD_A_DIGITAL_CDC_CONN_RX_LB_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL1 (0x058)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL1__POR (0x7C)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL2 (0x059)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL2__POR (0x7C)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL3 (0x05A)
+#define MSM8X16_WCD_A_DIGITAL_CDC_RX_CTL3__POR (0x7C)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA0 (0x05B)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA0__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA1 (0x05C)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA1__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA2 (0x05D)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA2__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA3 (0x05E)
+#define MSM8X16_WCD_A_DIGITAL_DEM_BYPASS_DATA3__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_DIG_DEBUG_CTL (0x068)
+#define MSM8X16_WCD_A_DIGITAL_DIG_DEBUG_CTL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_DIG_DEBUG_EN (0x069)
+#define MSM8X16_WCD_A_DIGITAL_DIG_DEBUG_EN__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_SPARE_0 (0x070)
+#define MSM8X16_WCD_A_DIGITAL_SPARE_0__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_SPARE_1 (0x071)
+#define MSM8X16_WCD_A_DIGITAL_SPARE_1__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_SPARE_2 (0x072)
+#define MSM8X16_WCD_A_DIGITAL_SPARE_2__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_SEC_ACCESS (0x0D0)
+#define MSM8X16_WCD_A_DIGITAL_SEC_ACCESS__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL1 (0x0D8)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL1__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL2 (0x0D9)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL2__POR (0x01)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL3 (0x0DA)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL3__POR (0x05)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL4 (0x0DB)
+#define MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL4__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_TEST1 (0x0E0)
+#define MSM8X16_WCD_A_DIGITAL_INT_TEST1__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_INT_TEST_VAL (0x0E1)
+#define MSM8X16_WCD_A_DIGITAL_INT_TEST_VAL__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_TRIM_NUM (0x0F0)
+#define MSM8X16_WCD_A_DIGITAL_TRIM_NUM__POR (0x00)
+#define MSM8X16_WCD_A_DIGITAL_TRIM_CTRL (0x0F1)
+#define MSM8X16_WCD_A_DIGITAL_TRIM_CTRL__POR (0x00)
+
+#define MSM8X16_WCD_A_ANALOG_REVISION1 (0x100)
+#define MSM8X16_WCD_A_ANALOG_REVISION1__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_REVISION2 (0x101)
+#define MSM8X16_WCD_A_ANALOG_REVISION2__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_REVISION3 (0x102)
+#define MSM8X16_WCD_A_ANALOG_REVISION3__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_REVISION4 (0x103)
+#define MSM8X16_WCD_A_ANALOG_REVISION4__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_PERPH_TYPE (0x104)
+#define MSM8X16_WCD_A_ANALOG_PERPH_TYPE__POR (0x23)
+#define MSM8X16_WCD_A_ANALOG_PERPH_SUBTYPE (0x105)
+#define MSM8X16_WCD_A_ANALOG_PERPH_SUBTYPE__POR (0x09)
+#define MSM8X16_WCD_A_ANALOG_INT_RT_STS (0x110)
+#define MSM8X16_WCD_A_ANALOG_INT_RT_STS__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_SET_TYPE (0x111)
+#define MSM8X16_WCD_A_ANALOG_INT_SET_TYPE__POR (0x3F)
+#define MSM8X16_WCD_A_ANALOG_INT_POLARITY_HIGH (0x112)
+#define MSM8X16_WCD_A_ANALOG_INT_POLARITY_HIGH__POR (0x3F)
+#define MSM8X16_WCD_A_ANALOG_INT_POLARITY_LOW (0x113)
+#define MSM8X16_WCD_A_ANALOG_INT_POLARITY_LOW__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_LATCHED_CLR (0x114)
+#define MSM8X16_WCD_A_ANALOG_INT_LATCHED_CLR__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_EN_SET (0x115)
+#define MSM8X16_WCD_A_ANALOG_INT_EN_SET__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_EN_CLR (0x116)
+#define MSM8X16_WCD_A_ANALOG_INT_EN_CLR__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_LATCHED_STS (0x118)
+#define MSM8X16_WCD_A_ANALOG_INT_LATCHED_STS__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_PENDING_STS (0x119)
+#define MSM8X16_WCD_A_ANALOG_INT_PENDING_STS__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_MID_SEL (0x11A)
+#define MSM8X16_WCD_A_ANALOG_INT_MID_SEL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_PRIORITY (0x11B)
+#define MSM8X16_WCD_A_ANALOG_INT_PRIORITY__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_EN (0x140)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_EN__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_VAL (0x141)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_VAL__POR (0x20)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_CTL (0x142)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_INT_RBIAS (0x143)
+#define MSM8X16_WCD_A_ANALOG_MICB_1_INT_RBIAS__POR (0x49)
+#define MSM8X16_WCD_A_ANALOG_MICB_2_EN (0x144)
+#define MSM8X16_WCD_A_ANALOG_MICB_2_EN__POR (0x20)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_ATEST_CTL_2 (0x145)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_ATEST_CTL_2__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL (0x146)
+#define MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_1 (0x147)
+#define MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_1__POR (0x35)
+#define MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_2 (0x150)
+#define MSM8X16_WCD_A_ANALOG_MBHC_DET_CTL_2__POR (0x08)
+#define MSM8X16_WCD_A_ANALOG_MBHC_FSM_CTL (0x151)
+#define MSM8X16_WCD_A_ANALOG_MBHC_FSM_CTL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MBHC_DBNC_TIMER (0x152)
+#define MSM8X16_WCD_A_ANALOG_MBHC_DBNC_TIMER__POR (0x98)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN0_ZDETL_CTL (0x153)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN0_ZDETL_CTL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN1_ZDETM_CTL (0x154)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN1_ZDETM_CTL__POR (0x20)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN2_ZDETH_CTL (0x155)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN2_ZDETH_CTL__POR (0x40)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN3_CTL (0x156)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN3_CTL__POR (0x61)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN4_CTL (0x157)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN4_CTL__POR (0x80)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN_RESULT (0x158)
+#define MSM8X16_WCD_A_ANALOG_MBHC_BTN_RESULT__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_MBHC_ZDET_ELECT_RESULT (0x159)
+#define MSM8X16_WCD_A_ANALOG_MBHC_ZDET_ELECT_RESULT__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_TX_1_EN (0x160)
+#define MSM8X16_WCD_A_ANALOG_TX_1_EN__POR (0x03)
+#define MSM8X16_WCD_A_ANALOG_TX_2_EN (0x161)
+#define MSM8X16_WCD_A_ANALOG_TX_2_EN__POR (0x03)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_1 (0x162)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_1__POR (0xBF)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_2 (0x163)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_2__POR (0x8C)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_ATEST_CTL (0x164)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_ATEST_CTL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS (0x165)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS__POR (0x6B)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_TXFE_CLKDIV (0x166)
+#define MSM8X16_WCD_A_ANALOG_TX_1_2_TXFE_CLKDIV__POR (0x51)
+#define MSM8X16_WCD_A_ANALOG_TX_3_EN (0x167)
+#define MSM8X16_WCD_A_ANALOG_TX_3_EN__POR (0x02)
+#define MSM8X16_WCD_A_ANALOG_NCP_EN (0x180)
+#define MSM8X16_WCD_A_ANALOG_NCP_EN__POR (0x26)
+#define MSM8X16_WCD_A_ANALOG_NCP_CLK (0x181)
+#define MSM8X16_WCD_A_ANALOG_NCP_CLK__POR (0x23)
+#define MSM8X16_WCD_A_ANALOG_NCP_DEGLITCH (0x182)
+#define MSM8X16_WCD_A_ANALOG_NCP_DEGLITCH__POR (0x5B)
+#define MSM8X16_WCD_A_ANALOG_NCP_FBCTRL (0x183)
+#define MSM8X16_WCD_A_ANALOG_NCP_FBCTRL__POR (0x08)
+#define MSM8X16_WCD_A_ANALOG_NCP_BIAS (0x184)
+#define MSM8X16_WCD_A_ANALOG_NCP_BIAS__POR (0x29)
+#define MSM8X16_WCD_A_ANALOG_NCP_VCTRL (0x185)
+#define MSM8X16_WCD_A_ANALOG_NCP_VCTRL__POR (0x24)
+#define MSM8X16_WCD_A_ANALOG_NCP_TEST (0x186)
+#define MSM8X16_WCD_A_ANALOG_NCP_TEST__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_NCP_CLIM_ADDR (0x187)
+#define MSM8X16_WCD_A_ANALOG_NCP_CLIM_ADDR__POR (0xD5)
+#define MSM8X16_WCD_A_ANALOG_RX_CLOCK_DIVIDER (0x190)
+#define MSM8X16_WCD_A_ANALOG_RX_CLOCK_DIVIDER__POR (0xE8)
+#define MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL (0x191)
+#define MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL__POR (0xCF)
+#define MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT (0x192)
+#define MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT__POR (0x6E)
+#define MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC (0x193)
+#define MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC__POR (0x10)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_PA (0x194)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_PA__POR (0x5A)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_LDO_OCP (0x195)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_LDO_OCP__POR (0x69)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_CNP (0x196)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_BIAS_CNP__POR (0x29)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN (0x197)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN__POR (0x80)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_CTL (0x198)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_CTL__POR (0xDA)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_TIME (0x199)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_WG_TIME__POR (0x16)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST (0x19A)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL (0x19B)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL__POR (0x20)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST (0x19C)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL (0x19D)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL__POR (0x20)
+#define MSM8X16_WCD_A_ANALOG_RX_EAR_CTL (0x19E)
+#define MSM8X16_WCD_A_ANALOG_RX_EAR_CTL___POR (0x12)
+#define MSM8X16_WCD_A_ANALOG_RX_ATEST (0x19F)
+#define MSM8X16_WCD_A_ANALOG_RX_ATEST__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_STATUS (0x1A0)
+#define MSM8X16_WCD_A_ANALOG_RX_HPH_STATUS__POR (0x0C)
+#define MSM8X16_WCD_A_ANALOG_RX_EAR_STATUS (0x1A1)
+#define MSM8X16_WCD_A_ANALOG_RX_EAR_STATUS__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL (0x1B0)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL__POR (0x83)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_CLIP_DET (0x1B1)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_CLIP_DET__POR (0x91)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL (0x1B2)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL__POR (0x29)
+#define MSM8X16_WCD_A_ANALOG_SPKR_ANA_BIAS_SET (0x1B3)
+#define MSM8X16_WCD_A_ANALOG_SPKR_ANA_BIAS_SET__POR (0x4D)
+#define MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL (0x1B4)
+#define MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL__POR (0xE1)
+#define MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL (0x1B5)
+#define MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL__POR (0x1E)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_MISC (0x1B6)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_MISC__POR (0xCB)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG (0x1B7)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT (0x1C0)
+#define MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT__POR (0x02)
+#define MSM8X16_WCD_A_ANALOG_OUTPUT_VOLTAGE (0x1C1)
+#define MSM8X16_WCD_A_ANALOG_OUTPUT_VOLTAGE__POR (0x14)
+#define MSM8X16_WCD_A_ANALOG_BYPASS_MODE (0x1C2)
+#define MSM8X16_WCD_A_ANALOG_BYPASS_MODE__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL (0x1C3)
+#define MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL__POR (0x1F)
+#define MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO (0x1C4)
+#define MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO__POR (0x8C)
+#define MSM8X16_WCD_A_ANALOG_RDSON_MAX_DUTY_CYCLE (0x1C5)
+#define MSM8X16_WCD_A_ANALOG_RDSON_MAX_DUTY_CYCLE__POR (0xC0)
+#define MSM8X16_WCD_A_ANALOG_BOOST_TEST1_1 (0x1C6)
+#define MSM8X16_WCD_A_ANALOG_BOOST_TEST1_1__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_BOOST_TEST_2 (0x1C7)
+#define MSM8X16_WCD_A_ANALOG_BOOST_TEST_2__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_SPKR_SAR_STATUS (0x1C8)
+#define MSM8X16_WCD_A_ANALOG_SPKR_SAR_STATUS__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_STATUS (0x1C9)
+#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_STATUS__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_PBUS_ADD_CSR (0x1CE)
+#define MSM8X16_WCD_A_ANALOG_PBUS_ADD_CSR__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_PBUS_ADD_SEL (0x1CF)
+#define MSM8X16_WCD_A_ANALOG_PBUS_ADD_SEL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_SEC_ACCESS (0x1D0)
+#define MSM8X16_WCD_A_ANALOG_SEC_ACCESS__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL1 (0x1D8)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL1__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL2 (0x1D9)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL2__POR (0x01)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3 (0x1DA)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3__POR (0x05)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL4 (0x1DB)
+#define MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL4__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_TEST1 (0x1E0)
+#define MSM8X16_WCD_A_ANALOG_INT_TEST1__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_INT_TEST_VAL (0x1E1)
+#define MSM8X16_WCD_A_ANALOG_INT_TEST_VAL__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_TRIM_NUM (0x1F0)
+#define MSM8X16_WCD_A_ANALOG_TRIM_NUM__POR (0x04)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL1 (0x1F1)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL1__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL2 (0x1F2)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL2__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL3 (0x1F3)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL3__POR (0x00)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL4 (0x1F4)
+#define MSM8X16_WCD_A_ANALOG_TRIM_CTRL4__POR (0x00)
+
+/* Digital part */
+#define MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL (0x200)
+#define MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_TX_RESET_B1_CTL (0x204)
+#define MSM8X16_WCD_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_DMIC_B1_CTL (0x208)
+#define MSM8X16_WCD_A_CDC_CLK_DMIC_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL (0x20C)
+#define MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL__POR (0x13)
+#define MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL (0x210)
+#define MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL__POR (0x13)
+#define MSM8X16_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL (0x214)
+#define MSM8X16_WCD_A_CDC_CLK_OTHR_RESET_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x218)
+#define MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_OTHR_CTL (0x21C)
+#define MSM8X16_WCD_A_CDC_CLK_OTHR_CTL__POR (0x04)
+#define MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL (0x220)
+#define MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_MCLK_CTL (0x224)
+#define MSM8X16_WCD_A_CDC_CLK_MCLK_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_PDM_CTL (0x228)
+#define MSM8X16_WCD_A_CDC_CLK_PDM_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CLK_SD_CTL (0x22C)
+#define MSM8X16_WCD_A_CDC_CLK_SD_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX1_B1_CTL (0x240)
+#define MSM8X16_WCD_A_CDC_RX1_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX2_B1_CTL (0x260)
+#define MSM8X16_WCD_A_CDC_RX2_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX3_B1_CTL (0x280)
+#define MSM8X16_WCD_A_CDC_RX3_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX1_B2_CTL (0x244)
+#define MSM8X16_WCD_A_CDC_RX1_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX2_B2_CTL (0x264)
+#define MSM8X16_WCD_A_CDC_RX2_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX3_B2_CTL (0x284)
+#define MSM8X16_WCD_A_CDC_RX3_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX1_B3_CTL (0x248)
+#define MSM8X16_WCD_A_CDC_RX1_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX2_B3_CTL (0x268)
+#define MSM8X16_WCD_A_CDC_RX2_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX3_B3_CTL (0x288)
+#define MSM8X16_WCD_A_CDC_RX3_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX1_B4_CTL (0x24C)
+#define MSM8X16_WCD_A_CDC_RX1_B4_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX2_B4_CTL (0x26C)
+#define MSM8X16_WCD_A_CDC_RX2_B4_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX3_B4_CTL (0x28C)
+#define MSM8X16_WCD_A_CDC_RX3_B4_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX1_B5_CTL (0x250)
+#define MSM8X16_WCD_A_CDC_RX1_B5_CTL__POR (0x68)
+#define MSM8X16_WCD_A_CDC_RX2_B5_CTL (0x270)
+#define MSM8X16_WCD_A_CDC_RX2_B5_CTL__POR (0x68)
+#define MSM8X16_WCD_A_CDC_RX3_B5_CTL (0x290)
+#define MSM8X16_WCD_A_CDC_RX3_B5_CTL__POR (0x68)
+#define MSM8X16_WCD_A_CDC_RX1_B6_CTL (0x254)
+#define MSM8X16_WCD_A_CDC_RX1_B6_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX2_B6_CTL (0x274)
+#define MSM8X16_WCD_A_CDC_RX2_B6_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX3_B6_CTL (0x294)
+#define MSM8X16_WCD_A_CDC_RX3_B6_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B1_CTL (0x258)
+#define MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B1_CTL (0x278)
+#define MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B1_CTL (0x298)
+#define MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL (0x25C)
+#define MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL (0x27C)
+#define MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL (0x29C)
+#define MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TOP_GAIN_UPDATE (0x2A0)
+#define MSM8X16_WCD_A_CDC_TOP_GAIN_UPDATE__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TOP_CTL (0x2A4)
+#define MSM8X16_WCD_A_CDC_TOP_CTL__POR (0x01)
+#define MSM8X16_WCD_A_CDC_DEBUG_DESER1_CTL (0x2E0)
+#define MSM8X16_WCD_A_CDC_DEBUG_DESER1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_DEBUG_DESER2_CTL (0x2E4)
+#define MSM8X16_WCD_A_CDC_DEBUG_DESER2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_DEBUG_B1_CTL_CFG (0x2E8)
+#define MSM8X16_WCD_A_CDC_DEBUG_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_DEBUG_B2_CTL_CFG (0x2EC)
+#define MSM8X16_WCD_A_CDC_DEBUG_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_DEBUG_B3_CTL_CFG (0x2F0)
+#define MSM8X16_WCD_A_CDC_DEBUG_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B1_CTL (0x300)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B1_CTL (0x340)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B2_CTL (0x304)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B2_CTL (0x344)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B3_CTL (0x308)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B3_CTL (0x348)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B4_CTL (0x30C)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B4_CTL (0x34C)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B4_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B5_CTL (0x310)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B5_CTL (0x350)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B5_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B6_CTL (0x314)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B6_CTL (0x354)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B6_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B7_CTL (0x318)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B7_CTL (0x358)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B7_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B8_CTL (0x31C)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B8_CTL (0x35C)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_B8_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_CTL (0x320)
+#define MSM8X16_WCD_A_CDC_IIR1_CTL__POR (0x40)
+#define MSM8X16_WCD_A_CDC_IIR2_CTL (0x360)
+#define MSM8X16_WCD_A_CDC_IIR2_CTL__POR (0x40)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_TIMER_CTL (0x324)
+#define MSM8X16_WCD_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_TIMER_CTL (0x364)
+#define MSM8X16_WCD_A_CDC_IIR2_GAIN_TIMER_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_COEF_B1_CTL (0x328)
+#define MSM8X16_WCD_A_CDC_IIR1_COEF_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_COEF_B1_CTL (0x368)
+#define MSM8X16_WCD_A_CDC_IIR2_COEF_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR1_COEF_B2_CTL (0x32C)
+#define MSM8X16_WCD_A_CDC_IIR1_COEF_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_IIR2_COEF_B2_CTL (0x36C)
+#define MSM8X16_WCD_A_CDC_IIR2_COEF_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL (0x380)
+#define MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL (0x384)
+#define MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL (0x388)
+#define MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL (0x38C)
+#define MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX2_B2_CTL (0x390)
+#define MSM8X16_WCD_A_CDC_CONN_RX2_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL (0x394)
+#define MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL (0x398)
+#define MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_RX3_B2_CTL (0x39C)
+#define MSM8X16_WCD_A_CDC_CONN_RX3_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL (0x3A0)
+#define MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B1_CTL (0x3A8)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B2_CTL (0x3AC)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B3_CTL (0x3B0)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B4_CTL (0x3B4)
+#define MSM8X16_WCD_A_CDC_CONN_EQ1_B4_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B1_CTL (0x3B8)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B2_CTL (0x3BC)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B2_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B3_CTL (0x3C0)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B3_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B4_CTL (0x3C4)
+#define MSM8X16_WCD_A_CDC_CONN_EQ2_B4_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_CONN_TX_I2S_SD1_CTL (0x3C8)
+#define MSM8X16_WCD_A_CDC_CONN_TX_I2S_SD1_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX1_VOL_CTL_TIMER (0x480)
+#define MSM8X16_WCD_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX2_VOL_CTL_TIMER (0x4A0)
+#define MSM8X16_WCD_A_CDC_TX2_VOL_CTL_TIMER__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX1_VOL_CTL_GAIN (0x484)
+#define MSM8X16_WCD_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX2_VOL_CTL_GAIN (0x4A4)
+#define MSM8X16_WCD_A_CDC_TX2_VOL_CTL_GAIN__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG (0x488)
+#define MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX2_VOL_CTL_CFG (0x4A8)
+#define MSM8X16_WCD_A_CDC_TX2_VOL_CTL_CFG__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX1_MUX_CTL (0x48C)
+#define MSM8X16_WCD_A_CDC_TX1_MUX_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX2_MUX_CTL (0x4AC)
+#define MSM8X16_WCD_A_CDC_TX2_MUX_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX1_CLK_FS_CTL (0x490)
+#define MSM8X16_WCD_A_CDC_TX1_CLK_FS_CTL__POR (0x03)
+#define MSM8X16_WCD_A_CDC_TX2_CLK_FS_CTL (0x4B0)
+#define MSM8X16_WCD_A_CDC_TX2_CLK_FS_CTL__POR (0x03)
+#define MSM8X16_WCD_A_CDC_TX1_DMIC_CTL (0x494)
+#define MSM8X16_WCD_A_CDC_TX1_DMIC_CTL__POR (0x00)
+#define MSM8X16_WCD_A_CDC_TX2_DMIC_CTL (0x4B4)
+#define MSM8X16_WCD_A_CDC_TX2_DMIC_CTL__POR (0x00)
+#endif
projects / karo-tx-linux.git / commitdiff