ALSA: dice: avoid superflous write at bus reset

When a bus reset happens, the enable register is automatically cleared,
so we do not need to clear it manually when stopping the stream.

Signed-off-by: Clemens Ladisch <clemens@ladisch.de>

diff --git a/sound/firewire/dice.c b/sound/firewire/dice.c
index 59d5ca4438b26fbcca68fb0b917454ada4f65c14..cfa98a83acb2aa6ef717d4a047983fb8c2c4268d 100644 (file)
--- a/sound/firewire/dice.c
+++ b/sound/firewire/dice.c
@@ -246,6 +246,9 @@ static void dice_enable_clear(struct dice *dice)
 {
        __be32 value;
 
+       if (!dice->global_enabled)
+               return;
+
        value = 0;
        snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
                           global_address(dice, GLOBAL_ENABLE),
@@ -1009,6 +1012,8 @@ static void dice_bus_reset(struct fw_unit *unit)
         * manner.
         */
        amdtp_out_stream_pcm_abort(&dice->stream);
+
+       dice->global_enabled = false;
        dice_stream_stop_packets(dice);
 
        dice_owner_update(dice);