static struct clk *axi_sel_clk;
static struct clk *pll3_pfd1_540m;
static struct clk *m4_clk;
+static struct clk *pll1;
+static struct clk *pll1_bypass;
+static struct clk *pll1_bypass_src;
static u32 pll2_org_rate;
static struct delayed_work low_bus_freq_handler;
else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
update_lpddr2_freq(ddr_normal_rate);
/* correct parent info after ddr freq change in asm code */
- imx_clk_set_parent(periph2_clk2_sel, pll3);
imx_clk_set_parent(periph2_pre_clk, pll2_400);
imx_clk_set_parent(periph2_clk, periph2_pre_clk);
+ imx_clk_set_parent(periph2_clk2_sel, pll3);
+
/*
* As periph2_clk's parent is not changed from
* audio mode to high mode, so clk framework
imx_clk_set_rate(mmdc_clk, ddr_normal_rate);
clk_disable_unprepare(pll2_400);
+
if (audio_bus_freq_mode)
clk_disable_unprepare(pll2_400);
}
*/
imx_clk_set_parent(step_clk, pll2_400);
imx_clk_set_parent(pll1_sw_clk, step_clk);
+ /*
+ * Need to ensure that PLL1 is bypassed and enabled
+ * before ARM-PODF is set.
+ */
+ clk_set_parent(pll1_bypass, pll1_bypass_src);
+
/*
* Ensure that the clock will be
* at original speed.
* the CPU freq does not change, so attempt to
* get a freq as close to 396MHz as possible.
*/
- imx_clk_set_rate(pll1_sys,
- clk_round_rate(pll1_sys, (org_arm_rate * 2)));
- pll1_rate = clk_get_rate(pll1_sys);
+ imx_clk_set_rate(pll1,
+ clk_round_rate(pll1, (org_arm_rate * 2)));
+ pll1_rate = clk_get_rate(pll1);
arm_div = pll1_rate / org_arm_rate;
if (pll1_rate / arm_div > org_arm_rate)
arm_div++;
+ /*
+ * Need to ensure that PLL1 is bypassed and enabled
+ * before ARM-PODF is set.
+ */
+ clk_set_parent(pll1_bypass, pll1);
/*
* Ensure ARM CLK is lower before
* changing the parent.
/* Move ARM from PLL1_SW_CLK to PLL2_400. */
imx_clk_set_parent(step_clk, pll2_400);
imx_clk_set_parent(pll1_sw_clk, step_clk);
+ /*
+ * Need to ensure that PLL1 is bypassed and enabled
+ * before ARM-PODF is set.
+ */
+ clk_set_parent(pll1_bypass, pll1_bypass_src);
imx_clk_set_rate(cpu_clk, org_arm_rate);
ultra_low_bus_freq_mode = 0;
}
}
if (cpu_is_imx6sl() || cpu_is_imx6sx()) {
- pll1_sys = devm_clk_get(&pdev->dev, "pll1_sys");
- if (IS_ERR(pll1_sys)) {
- dev_err(busfreq_dev, "%s: failed to get pll1_sys\n",
- __func__);
- return PTR_ERR(pll1_sys);
- }
-
ahb_clk = devm_clk_get(&pdev->dev, "ahb");
if (IS_ERR(ahb_clk)) {
dev_err(busfreq_dev, "%s: failed to get ahb_clk\n",
return PTR_ERR(ocram_clk);
}
- pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw");
- if (IS_ERR(pll1_sw_clk)) {
- dev_err(busfreq_dev, "%s: failed to get pll1_sw_clk\n",
- __func__);
- return PTR_ERR(pll1_sw_clk);
- }
-
periph2_clk = devm_clk_get(&pdev->dev, "periph2");
if (IS_ERR(periph2_clk)) {
dev_err(busfreq_dev, "%s: failed to get periph2\n",
}
}
if (cpu_is_imx6sl()) {
+ pll1 = devm_clk_get(&pdev->dev, "pll1");
+ if (IS_ERR(pll1)) {
+ dev_err(busfreq_dev, "%s: failed to get pll1\n",
+ __func__);
+ return PTR_ERR(pll1);
+ }
+
+ pll1_bypass = devm_clk_get(&pdev->dev, "pll1_bypass");
+ if (IS_ERR(pll1_bypass)) {
+ dev_err(busfreq_dev, "%s: failed to get pll1_bypass\n",
+ __func__);
+ return PTR_ERR(pll1_bypass);
+ }
+
+ pll1_bypass_src = devm_clk_get(&pdev->dev, "pll1_bypass_src");
+ if (IS_ERR(pll1_bypass_src)) {
+ dev_err(busfreq_dev, "%s: failed to get pll1_bypass_src\n",
+ __func__);
+ return PTR_ERR(pll1_bypass_src);
+ }
+
+ pll1_sys = devm_clk_get(&pdev->dev, "pll1_sys");
+ if (IS_ERR(pll1_sys)) {
+ dev_err(busfreq_dev, "%s: failed to get pll1_sys\n",
+ __func__);
+ return PTR_ERR(pll1_sys);
+ }
+
+ pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw");
+ if (IS_ERR(pll1_sw_clk)) {
+ dev_err(busfreq_dev, "%s: failed to get pll1_sw_clk\n",
+ __func__);
+ return PTR_ERR(pll1_sw_clk);
+ }
+
pll2_bypass_src = devm_clk_get(&pdev->dev, "pll2_bypass_src");
if (IS_ERR(pll2_bypass_src)) {
dev_err(busfreq_dev, "%s: failed to get pll2_bypass_src\n",
}
}
-static void imx6sl_enable_pll_arm(bool enable)
-{
- static u32 saved_pll_arm;
- u32 val;
-
- if (enable) {
- saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
- val |= BM_PLL_ARM_ENABLE;
- val &= ~BM_PLL_ARM_POWERDOWN;
- writel_relaxed(val, anatop_base + PLL_ARM);
- while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
- ;
- } else {
- writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
- }
-}
-
void imx6sl_set_wait_clk(bool enter)
{
static unsigned long saved_arm_div;
u32 val;
int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
- /*
- * According to hardware design, arm podf change need
- * PLL1 clock enabled.
- */
- if (arm_div_for_wait == ARM_WAIT_DIV_396M)
- imx6sl_enable_pll_arm(true);
-
if (enter) {
/*
* If in this mode, the IPG clock is at 12MHz, we can
}
while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
;
-
- if (arm_div_for_wait == ARM_WAIT_DIV_396M)
- imx6sl_enable_pll_arm(false);
}
static int __init setup_uart_clk(char *uart_rate)
imx_clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
imx_clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
- clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
+ clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
projects / karo-tx-linux.git / commitdiff