static const char *lvds_sels[] = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
"dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", };
static const char *pll_av_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
+static void __iomem *anatop_base;
+static void __iomem *ccm_base;
+
enum mx6q_clks {
dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
{ }
};
+static void init_ldb_clks(enum mx6q_clks new_parent)
+{
+ u32 reg;
+
+ /*
+ * Need to follow a strict procedure when changing the LDB
+ * clock, else we can introduce a glitch. Things to keep in
+ * mind:
+ * 1. The current and new parent clocks must be disabled.
+ * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
+ * no CG bit.
+ * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
+ * the top four options are in one mux and the PLL3 option along
+ * with another option is in the second mux. There is third mux
+ * used to decide between the first and second mux.
+ * The code below switches the parent to the bottom mux first
+ * and then manipulates the top mux. This ensures that no glitch
+ * will enter the divider.
+ *
+ * Need to disable MMDC_CH1 clock manually as there is no CG bit
+ * for this clock. The only way to disable this clock is to move
+ * it topll3_sw_clk and then to disable pll3_sw_clk
+ * Make sure periph2_clk2_sel is set to pll3_sw_clk
+ */
+ reg = readl_relaxed(ccm_base + 0x18);
+ reg &= ~(1 << 20);
+ writel_relaxed(reg, ccm_base + 0x18);
+
+ /*
+ * Set MMDC_CH1 mask bit.
+ */
+ reg = readl_relaxed(ccm_base + 0x4);
+ reg |= 1 << 16;
+ writel_relaxed(reg, ccm_base + 0x4);
+
+ /*
+ * Set the periph2_clk_sel to the top mux so that
+ * mmdc_ch1 is from pll3_sw_clk.
+ */
+ reg = readl_relaxed(ccm_base + 0x14);
+ reg |= 1 << 26;
+ writel_relaxed(reg, ccm_base + 0x14);
+
+ /*
+ * Wait for the clock switch.
+ */
+ while (readl_relaxed(ccm_base + 0x48))
+ ;
+
+ /*
+ * Disable pll3_sw_clk by selecting the bypass clock source.
+ */
+ reg = readl_relaxed(ccm_base + 0xc);
+ reg |= 1 << 0;
+ writel_relaxed(reg, ccm_base + 0xc);
+
+ /*
+ * Set the ldb_di0_clk and ldb_di1_clk to 111b.
+ */
+ reg = readl_relaxed(ccm_base + 0x2c);
+ reg |= ((7 << 9) | (7 << 12));
+ writel_relaxed(reg, ccm_base + 0x2c);
+
+ /*
+ * Set the ldb_di0_clk and ldb_di1_clk to 100b.
+ */
+ reg = readl_relaxed(ccm_base + 0x2c);
+ reg &= ~((7 << 9) | (7 << 12));
+ reg |= ((4 << 9) | (4 << 12));
+ writel_relaxed(reg, ccm_base + 0x2c);
+
+ /*
+ * Perform the LDB parent clock switch.
+ */
+ clk_set_parent(clk[ldb_di0_sel], clk[new_parent]);
+ clk_set_parent(clk[ldb_di1_sel], clk[new_parent]);
+
+ /*
+ * Unbypass pll3_sw_clk.
+ */
+ reg = readl_relaxed(ccm_base + 0xc);
+ reg &= ~(1 << 0);
+ writel_relaxed(reg, ccm_base + 0xc);
+
+ /*
+ * Set the periph2_clk_sel back to the bottom mux so that
+ * mmdc_ch1 is from its original parent.
+ */
+ reg = readl_relaxed(ccm_base + 0x14);
+ reg &= ~(1 << 26);
+ writel_relaxed(reg, ccm_base + 0x14);
+
+ /*
+ * Wait for the clock switch.
+ */
+ while (readl_relaxed(ccm_base + 0x48))
+ ;
+
+ /*
+ * Clear MMDC_CH1 mask bit.
+ */
+ reg = readl_relaxed(ccm_base + 0x4);
+ reg &= ~(1 << 16);
+ writel_relaxed(reg, ccm_base + 0x4);
+
+}
+
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *base;
int i, irq;
int ret;
+ u32 reg;
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
clk[anaclk2] = imx_obtain_fixed_clock("anaclk2", 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
- base = of_iomap(np, 0);
+ anatop_base = base = of_iomap(np, 0);
WARN_ON(!base);
/* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
np = ccm_node;
- base = of_iomap(np, 0);
+ ccm_base = base = of_iomap(np, 0);
WARN_ON(!base);
imx6_pm_set_ccm_base(base);
writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c);
writel_relaxed(0, base + 0x80);
+ /* Make sure PFDs are disabled at boot. */
+ reg = readl_relaxed(anatop_base + 0x100);
+ /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
+ if (cpu_is_imx6dl())
+ reg |= 0x80008080;
+ else
+ reg |= 0x80808080;
+ writel_relaxed(reg, anatop_base + 0x100);
+
+ /* Disable PLL3 PFDs. */
+ reg = readl_relaxed(anatop_base + 0xF0);
+ reg |= 0x80808080;
+ writel_relaxed(reg, anatop_base + 0xF0);
+
+ /* Make sure PLLs is disabled */
+ reg = readl_relaxed(anatop_base + 0xA0);
+ reg &= ~(1 << 13);
+ writel_relaxed(reg, anatop_base + 0xA0);
+
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clk[lvds2_in], "lvds2_in", NULL);
clk_register_clkdev(clk[esai], "esai", NULL);
- if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
- clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
- clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
- }
-
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
* We can not get the 100MHz from the pll2_pfd0_352m.
if (clk_set_parent(clk[pcie_axi_sel], clk[axi]))
pr_err("Failed to set PCIe parent clk.\n");
-
/* gpu clock initilazation */
clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
clk_set_rate(clk[gpu3d_shader], 594000000);
}
/* ipu clock initialization */
- clk_set_parent(clk[ldb_di0_sel], clk[pll2_pfd0_352m]);
- clk_set_parent(clk[ldb_di1_sel], clk[pll2_pfd0_352m]);
+ init_ldb_clks(pll2_pfd0_352m);
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
projects / karo-tx-linux.git / commitdiff