Merge remote-tracking branch 'clk/clk-next'

diff --combined drivers/clk/rockchip/clk-rk3036.c
index 5759d75780cf70b4d30becc7fc442dd8cad1e4d1,bc7fbac83ab74dfca9e534401bc430f629d01357..0703c8f08ef869638f8c2672827a1eea34e406e0
--- 1/drivers/clk/rockchip/clk-rk3036.c
--- 2/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@@ -133,7 -133,7 +133,7 @@@ PNAME(mux_spdif_p) = { "spdif_src", "sp
  PNAME(mux_uart0_p)    = { "uart0_src", "uart0_frac", "xin24m" };
  PNAME(mux_uart1_p)    = { "uart1_src", "uart1_frac", "xin24m" };
  PNAME(mux_uart2_p)    = { "uart2_src", "uart2_frac", "xin24m" };
- PNAME(mux_mac_p)      = { "mac_pll_src", "ext_gmac" };
+ PNAME(mux_mac_p)      = { "mac_pll_src", "rmii_clkin" };
  PNAME(mux_dclk_p)     = { "dclk_lcdc", "dclk_cru" };
  
  static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
@@@ -177,8 -177,6 +177,8 @@@ static struct rockchip_clk_branch rk303
        GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(0), 6, GFLAGS),
  
 +      FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 +
        /*
         * Clock-Architecture Diagram 2
         */
@@@ -189,7 -187,6 +189,7 @@@
                        RK2928_CLKGATE_CON(0), 8, GFLAGS),
        COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 +      FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2),
  
        COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
                        RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
@@@ -227,16 -224,16 +227,16 @@@
                        RK2928_CLKGATE_CON(2), 2, GFLAGS),
  
        COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
-                       RK2928_CLKSEL_CON(2), 4, 1, DFLAGS,
+                       RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
                        RK2928_CLKGATE_CON(1), 0, GFLAGS),
        COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
-                       RK2928_CLKSEL_CON(2), 5, 1, DFLAGS,
+                       RK2928_CLKSEL_CON(2), 5, 1, MFLAGS,
                        RK2928_CLKGATE_CON(1), 1, GFLAGS),
        COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
-                       RK2928_CLKSEL_CON(2), 6, 1, DFLAGS,
+                       RK2928_CLKSEL_CON(2), 6, 1, MFLAGS,
                        RK2928_CLKGATE_CON(2), 4, GFLAGS),
        COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
-                       RK2928_CLKSEL_CON(2), 7, 1, DFLAGS,
+                       RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
                        RK2928_CLKGATE_CON(2), 5, GFLAGS),
  
        MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
@@@ -245,11 -242,11 +245,11 @@@
                        RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
                        RK2928_CLKGATE_CON(1), 8, GFLAGS),
        COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
-                       RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
-                       RK2928_CLKGATE_CON(1), 8, GFLAGS),
+                       RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
+                       RK2928_CLKGATE_CON(1), 10, GFLAGS),
        COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
-                       RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
-                       RK2928_CLKGATE_CON(1), 8, GFLAGS),
+                       RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
+                       RK2928_CLKGATE_CON(1), 12, GFLAGS),
        COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
                        RK2928_CLKSEL_CON(17), 0,
                        RK2928_CLKGATE_CON(1), 9, GFLAGS,
@@@ -266,8 -263,6 +266,8 @@@
        COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
                        RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK2928_CLKGATE_CON(3), 11, GFLAGS),
 +      FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
 +                      RK2928_CLKGATE_CON(3), 12, GFLAGS),
  
        COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
                        RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
@@@ -284,13 -279,13 +284,13 @@@
                        RK2928_CLKGATE_CON(3), 2, GFLAGS),
  
        COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
-                       RK2928_CLKSEL_CON(12), 8, 2, DFLAGS,
+                       RK2928_CLKSEL_CON(12), 8, 2, MFLAGS,
                        RK2928_CLKGATE_CON(2), 11, GFLAGS),
        DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
                        RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
  
        COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
-                       RK2928_CLKSEL_CON(12), 10, 2, DFLAGS,
+                       RK2928_CLKSEL_CON(12), 10, 2, MFLAGS,
                        RK2928_CLKGATE_CON(2), 13, GFLAGS),
        DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
                        RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
@@@ -349,14 -344,13 +349,14 @@@
                        RK2928_CLKGATE_CON(10), 5, GFLAGS),
  
        COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
-                       RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
+                       RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
        MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
                        RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
  
        COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
-                       RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
+                       RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
                        RK2928_CLKGATE_CON(2), 6, GFLAGS),
 +      FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2),
  
        MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
                        RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
@@@ -382,9 -376,11 +382,9 @@@
        GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
        GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
  
 -      GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
 +      GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
        GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
  
 -      /* hclk_video gates */
 -      GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),
  
        /* xin24m gates */
        GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
@@@ -448,11 -444,34 +448,11 @@@ static void __init rk3036_clk_init(stru
  
        rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
  
 -      /* xin12m is created by an cru-internal divider */
 -      clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 -      if (IS_ERR(clk))
 -              pr_warn("%s: could not register clock xin12m: %ld\n",
 -                      __func__, PTR_ERR(clk));
 -
        clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
        if (IS_ERR(clk))
                pr_warn("%s: could not register clock usb480m: %ld\n",
                        __func__, PTR_ERR(clk));
  
 -      clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2);
 -      if (IS_ERR(clk))
 -              pr_warn("%s: could not register clock ddrphy: %ld\n",
 -                      __func__, PTR_ERR(clk));
 -
 -      clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
 -                                      "aclk_vcodec", 0, 1, 4);
 -      if (IS_ERR(clk))
 -              pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 -                      __func__, PTR_ERR(clk));
 -
 -      clk = clk_register_fixed_factor(NULL, "sclk_macref_out",
 -                                      "hclk_peri_src", 0, 1, 2);
 -      if (IS_ERR(clk))
 -              pr_warn("%s: could not register clock sclk_macref_out: %ld\n",
 -                      __func__, PTR_ERR(clk));
 -
        rockchip_clk_register_plls(rk3036_pll_clks,
                                   ARRAY_SIZE(rk3036_pll_clks),
                                   RK3036_GRF_SOC_STATUS0);

diff --combined drivers/clk/rockchip/clk-rk3368.c
index 31facd8426f754640a63b2984cf27aa7cb4d74d6,21f3ea909fabdb7c4f753cd4ed817035c15a31e0..c2b0421f2076135161e49de66cf02c91ac034587
--- 1/drivers/clk/rockchip/clk-rk3368.c
--- 2/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@@ -121,7 -121,7 +121,7 @@@ PNAME(mux_i2s_2ch_p)               = { "i2s_2ch_src"
                                    "dummy", "xin12m" };
  PNAME(mux_spdif_8ch_p)                = { "spdif_8ch_pre", "spdif_8ch_frac",
                                    "ext_i2s", "xin12m" };
 -PNAME(mux_edp_24m_p)          = { "dummy", "xin24m" };
 +PNAME(mux_edp_24m_p)          = { "xin24m", "dummy" };
  PNAME(mux_vip_out_p)          = { "vip_src", "xin24m" };
  PNAME(mux_usbphy480m_p)               = { "usbotg_out", "xin24m" };
  PNAME(mux_hsic_usbphy480m_p)  = { "usbotg_out", "dummy" };
@@@ -165,7 -165,7 +165,7 @@@ static const struct rockchip_cpuclk_reg
        .core_reg = RK3368_CLKSEL_CON(0),
        .div_core_shift = 0,
        .div_core_mask = 0x1f,
 -      .mux_core_shift = 15,
 +      .mux_core_shift = 7,
  };
  
  static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
@@@ -218,29 -218,29 +218,29 @@@
        }
  
  static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
 -      RK3368_CPUCLKB_RATE(1512000000, 2, 6, 6),
 -      RK3368_CPUCLKB_RATE(1488000000, 2, 5, 5),
 -      RK3368_CPUCLKB_RATE(1416000000, 2, 5, 5),
 -      RK3368_CPUCLKB_RATE(1200000000, 2, 4, 4),
 -      RK3368_CPUCLKB_RATE(1008000000, 2, 4, 4),
 -      RK3368_CPUCLKB_RATE( 816000000, 2, 3, 3),
 -      RK3368_CPUCLKB_RATE( 696000000, 2, 3, 3),
 -      RK3368_CPUCLKB_RATE( 600000000, 2, 2, 2),
 -      RK3368_CPUCLKB_RATE( 408000000, 2, 2, 2),
 -      RK3368_CPUCLKB_RATE( 312000000, 2, 2, 2),
 +      RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
 +      RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
 +      RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
 +      RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
 +      RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
 +      RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
 +      RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
 +      RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
 +      RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
 +      RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
  };
  
  static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
 -      RK3368_CPUCLKL_RATE(1512000000, 2, 7, 7),
 -      RK3368_CPUCLKL_RATE(1488000000, 2, 6, 6),
 -      RK3368_CPUCLKL_RATE(1416000000, 2, 6, 6),
 -      RK3368_CPUCLKL_RATE(1200000000, 2, 5, 5),
 -      RK3368_CPUCLKL_RATE(1008000000, 2, 5, 5),
 -      RK3368_CPUCLKL_RATE( 816000000, 2, 4, 4),
 -      RK3368_CPUCLKL_RATE( 696000000, 2, 3, 3),
 -      RK3368_CPUCLKL_RATE( 600000000, 2, 3, 3),
 -      RK3368_CPUCLKL_RATE( 408000000, 2, 2, 2),
 -      RK3368_CPUCLKL_RATE( 312000000, 2, 2, 2),
 +      RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
 +      RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
 +      RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
 +      RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
 +      RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
 +      RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
 +      RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
 +      RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
 +      RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
 +      RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
  };
  
  static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
@@@ -248,8 -248,6 +248,8 @@@
         * Clock-Architecture Diagram 2
         */
  
 +      FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 +
        MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
  
@@@ -301,7 -299,7 +301,7 @@@
        COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
  
 -      GATE(0, "sclk_ddr", "ddrphy_div4", CLK_IGNORE_UNUSED,
 +      FACTOR_GATE(0, "sclk_ddr", "ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
                        RK3368_CLKGATE_CON(6), 14, GFLAGS),
        GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
                        RK3368_CLKGATE_CON(6), 15, GFLAGS),
@@@ -355,7 -353,7 +355,7 @@@
        COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(32), 0,
                        RK3368_CLKGATE_CON(6), 5, GFLAGS),
 -      COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
 +      COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(31), 8, 2, MFLAGS,
                        RK3368_CLKGATE_CON(6), 6, GFLAGS),
        COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
@@@ -364,7 -362,7 +364,7 @@@
        COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(54), 0,
                        RK3368_CLKGATE_CON(5), 14, GFLAGS),
 -      COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, 0,
 +      COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
                        RK3368_CLKSEL_CON(53), 8, 2, MFLAGS,
                        RK3368_CLKGATE_CON(5), 15, GFLAGS),
  
@@@ -386,18 -384,18 +386,18 @@@
         * Clock-Architecture Diagram 3
         */
  
 -      COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb_p, 0,
 +      COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
                        RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3368_CLKGATE_CON(4), 6, GFLAGS),
 -      COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb_p, 0,
 +      COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
                        RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
                        RK3368_CLKGATE_CON(4), 7, GFLAGS),
  
        /*
 -       * We introduce a virtual node of hclk_vodec_pre_v to split one clock
 -       * struct with a gate and a fix divider into two node in software.
 +       * We use aclk_vdpu by default ---GRF_SOC_CON0[7] setting in system,
 +       * so we ignore the mux and make clocks nodes as following,
         */
 -      GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0,
 +      FACTOR_GATE(0, "hclk_video_pre", "aclk_vdpu", 0, 1, 4,
                RK3368_CLKGATE_CON(4), 8, GFLAGS),
  
        COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
@@@ -444,7 -442,7 +444,7 @@@
        GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
                        RK3368_CLKGATE_CON(4), 13, GFLAGS),
        GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
 -                      RK3368_CLKGATE_CON(5), 12, GFLAGS),
 +                      RK3368_CLKGATE_CON(4), 12, GFLAGS),
  
        COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
                        RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
@@@ -782,13 -780,13 +782,13 @@@
        GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
  
        /* pclk_pd_alive gates */
-       GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 8, GFLAGS),
-       GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 7, GFLAGS),
-       GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 12, GFLAGS),
-       GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 11, GFLAGS),
-       GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 3, GFLAGS),
-       GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 2, GFLAGS),
-       GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 1, GFLAGS),
+       GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
+       GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
+       GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
+       GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
+       GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
+       GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
+       GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
  
        /*
         * pclk_vio gates
@@@ -798,12 -796,12 +798,12 @@@
        GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
  
        /* pclk_pd_pmu gates */
-       GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 0, GFLAGS),
-       GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
-       GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 3, GFLAGS),
-       GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS),
-       GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 1, GFLAGS),
-       GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS),
+       GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
+       GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
+       GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
+       GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
+       GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
+       GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
  
        /* timer gates */
        GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
@@@ -844,6 -842,24 +844,6 @@@ static void __init rk3368_clk_init(stru
  
        rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
  
 -      /* xin12m is created by a cru-internal divider */
 -      clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 -      if (IS_ERR(clk))
 -              pr_warn("%s: could not register clock xin12m: %ld\n",
 -                      __func__, PTR_ERR(clk));
 -
 -      /* ddrphy_div4 is created by a cru-internal divider */
 -      clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4);
 -      if (IS_ERR(clk))
 -              pr_warn("%s: could not register clock xin12m: %ld\n",
 -                      __func__, PTR_ERR(clk));
 -
 -      clk = clk_register_fixed_factor(NULL, "hclk_video_pre",
 -                                      "hclk_video_pre_v", 0, 1, 4);
 -      if (IS_ERR(clk))
 -              pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 -                      __func__, PTR_ERR(clk));
 -
        /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
        clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
        if (IS_ERR(clk))

diff --combined drivers/clk/rockchip/clk.c
index ab505247887013d8b5eac570c996e96627165f26,f7e8693ad28bf6fe0586792c7847a9a2727cc9de..ec06350c78c4808c7dc6a849f157428402cccf0f
--- 1/drivers/clk/rockchip/clk.c
--- 2/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@@ -70,7 -70,7 +70,7 @@@ static struct clk *rockchip_clk_registe
        if (gate_offset >= 0) {
                gate = kzalloc(sizeof(*gate), GFP_KERNEL);
                if (!gate)
 -                      return ERR_PTR(-ENOMEM);
 +                      goto err_gate;
  
                gate->flags = gate_flags;
                gate->reg = base + gate_offset;
@@@ -82,7 -82,7 +82,7 @@@
        if (div_width > 0) {
                div = kzalloc(sizeof(*div), GFP_KERNEL);
                if (!div)
 -                      return ERR_PTR(-ENOMEM);
 +                      goto err_div;
  
                div->flags = div_flags;
                div->reg = base + muxdiv_offset;
@@@ -90,7 -90,9 +90,9 @@@
                div->width = div_width;
                div->lock = lock;
                div->table = div_table;
-               div_ops = &clk_divider_ops;
+               div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
+                                               ? &clk_divider_ro_ops
+                                               : &clk_divider_ops;
        }
  
        clk = clk_register_composite(NULL, name, parent_names, num_parents,
@@@ -100,11 -102,6 +102,11 @@@
                                     flags);
  
        return clk;
 +err_div:
 +      kfree(gate);
 +err_gate:
 +      kfree(mux);
 +      return ERR_PTR(-ENOMEM);
  }
  
  struct rockchip_clk_frac {
@@@ -265,53 -262,6 +267,53 @@@ static struct clk *rockchip_clk_registe
        return clk;
  }
  
 +static struct clk *rockchip_clk_register_factor_branch(const char *name,
 +              const char *const *parent_names, u8 num_parents,
 +              void __iomem *base, unsigned int mult, unsigned int div,
 +              int gate_offset, u8 gate_shift, u8 gate_flags,
 +              unsigned long flags, spinlock_t *lock)
 +{
 +      struct clk *clk;
 +      struct clk_gate *gate = NULL;
 +      struct clk_fixed_factor *fix = NULL;
 +
 +      /* without gate, register a simple factor clock */
 +      if (gate_offset == 0) {
 +              return clk_register_fixed_factor(NULL, name,
 +                              parent_names[0], flags, mult,
 +                              div);
 +      }
 +
 +      gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 +      if (!gate)
 +              return ERR_PTR(-ENOMEM);
 +
 +      gate->flags = gate_flags;
 +      gate->reg = base + gate_offset;
 +      gate->bit_idx = gate_shift;
 +      gate->lock = lock;
 +
 +      fix = kzalloc(sizeof(*fix), GFP_KERNEL);
 +      if (!fix) {
 +              kfree(gate);
 +              return ERR_PTR(-ENOMEM);
 +      }
 +
 +      fix->mult = mult;
 +      fix->div = div;
 +
 +      clk = clk_register_composite(NULL, name, parent_names, num_parents,
 +                                   NULL, NULL,
 +                                   &fix->hw, &clk_fixed_factor_ops,
 +                                   &gate->hw, &clk_gate_ops, flags);
 +      if (IS_ERR(clk)) {
 +              kfree(fix);
 +              kfree(gate);
 +      }
 +
 +      return clk;
 +}
 +
  static DEFINE_SPINLOCK(clk_lock);
  static struct clk **clk_table;
  static void __iomem *reg_base;
@@@ -447,14 -397,6 +449,14 @@@ void __init rockchip_clk_register_branc
                                reg_base + list->muxdiv_offset,
                                list->div_shift, list->div_flags, &clk_lock);
                        break;
 +              case branch_factor:
 +                      clk = rockchip_clk_register_factor_branch(
 +                              list->name, list->parent_names,
 +                              list->num_parents, reg_base,
 +                              list->div_shift, list->div_width,
 +                              list->gate_offset, list->gate_shift,
 +                              list->gate_flags, flags, &clk_lock);
 +                      break;
                }
  
                /* none of the cases above matched */

diff --combined include/linux/device.h
index 6c1a8ce77e3b391396939a7e7663c7bc21745608,74674e0983158e35006b59f2eda058478ce4917c..deb861960c6f06502546d35e95420cc773243702
--- 1/include/linux/device.h
--- 2/include/linux/device.h
+++ b/include/linux/device.h
@@@ -682,6 -682,18 +682,18 @@@ void __iomem *devm_ioremap_resource(str
  int devm_add_action(struct device *dev, void (*action)(void *), void *data);
  void devm_remove_action(struct device *dev, void (*action)(void *), void *data);
  
+ static inline int devm_add_action_or_reset(struct device *dev,
+                                          void (*action)(void *), void *data)
+ {
+       int ret;
+ 
+       ret = devm_add_action(dev, action, data);
+       if (ret)
+               action(data);
+ 
+       return ret;
+ }
+ 
  struct device_dma_parameters {
        /*
         * a low level driver may set these to teach IOMMU code about
@@@ -958,11 -970,6 +970,11 @@@ static inline void device_lock(struct d
        mutex_lock(&dev->mutex);
  }
  
 +static inline int device_lock_interruptible(struct device *dev)
 +{
 +      return mutex_lock_interruptible(&dev->mutex);
 +}
 +
  static inline int device_trylock(struct device *dev)
  {
        return mutex_trylock(&dev->mutex);
@@@ -1296,9 -1303,8 +1308,9 @@@ do {                                                                    
   * dev_WARN*() acts like dev_printk(), but with the key difference of
   * using WARN/WARN_ONCE to include file/line information and a backtrace.
   */
 -#define dev_WARN(dev, format, arg...) \
 -      WARN(1, "%s %s: " format, dev_driver_string(dev), dev_name(dev), ## arg);
 +#define dev_WARN(dev, condition, format, arg...)              \
 +      WARN(condition, "%s %s: " format,                       \
 +                      dev_driver_string(dev), dev_name(dev), ## arg)
  
  #define dev_WARN_ONCE(dev, condition, format, arg...) \
        WARN_ONCE(condition, "%s %s: " format, \