1 RedBoot for Starter-Kit V (STK5)
4 ===========================================================
8 - reduce the NFC clock frequency to 16MHz to prevent NAND chip
9 detection errors at cold temperatures with the Toshiba
10 TC58NYG0S3EBAI4 flash chips
15 - updated SDRAM initialization to work with NT5CB128M16 mask
16 revision 'F' (see: TX53-PCN-2013-08.pdf)
21 - workaround for MPLL restart problem in i.MX27 date code 1230
22 and newer (see /Documentation/TX27PCN2012-09.pdf).
23 - wait after enabling wdt clock in HAL_PLATFORM_RESET() to
24 prevent possible hang in 'reset' command.
25 - fix trampoline code change for archs that use the default
26 CYGARC_HAL_MMU_OFF macro.
29 Fixup messed up source code from previous release
34 - fixed the trampoline code in redboot_linux_exec.c
36 - fixed phys <-> virt address calculations
37 - added support for 2 memory banks (1GiB)
38 - fixed ATAG_MEM construction for banked memory
44 - add support for Toshiba NAND flash
45 - implement workaround for ENGcm12051 (DPLL: Meta-stability Issue)
47 - fix CCGR0 settings to enable JTAG interface
51 Fix FEC driver handling of 10BaseT link
55 Added support for TX53
60 Added support for redundant WinCE image load
65 Added support for splash screen, enabled with:
66 fconfig bootsplash_enable true
68 Name Default Value Description
69 lcd_bpp: 16 LCD color depth (only 16bpp for now)
70 lcd_buffer_addr: -2113929216 LCD frame buffer address (hex: 0x82000000)
71 lcd_clk_period: 33333 Pixel clock period (in ps)
72 lcd_clk_polarity: false Pixel clock polarity active low
73 lcd_panel_width: 640 LCD panel width (in pixels)
74 lcd_panel_height: 480 LCD panel height (in pixels)
75 lcd_hsync_polarity: true HSYNC polarity active low
76 lcd_hsync_width: 64 HSYNC pulse width (in pixels): 1 .. 64
77 lcd_margin_left: 96 Left margin (in pixels): 1 .. 256
78 lcd_margin_right: 80 Right margin (in pixels): 1 .. 256
79 lcd_margin_top: 46 Top margin (in scan lines): 0 .. 255
80 lcd_margin_bottom: 39 Bottom margin (in scan lines): 0 .. 255
81 lcd_vsync_polarity: true VSYNC polarity active low
82 lcd_vsync_width: 3 VSYNC pulse width (in scan lines): 0 .. 63
84 Image data is loaded from the flash partition named 'logo' and
85 can be stored either as a binary dump or in Windows .bmp
88 Renamed config/TX25-40x0.ecc to config/TX25-40x1.ecc to be in
89 sync with the module name
94 Added support for TX51-80x2 and TX51-80x1 (SDRAM clock selectable via cdl)
99 Fixed SDRAM timing according to application note from Micron.
101 Fixed display of reset reason.
102 Corrected DEBUG LED settings
104 Disabled FIS CRC check to facilitate update of the Linux
105 partition from within Linux (see RedBoot/README)
109 Added support for TX51-80x0
113 Corrected SDRAM timing setup for TX25 that was accidentally broken
114 in the previous release
118 switched to unified source tree for TX25,TX27,TX37
119 fixing some issues with bad block handling on TX27
123 Corrected the SDRAM initialisation for TX27-4021 (128MiB SDRAM)
128 Fixed a bug that lead to writing the RedBoot config partition on
129 every startup which would lead to excessive wearout of the flash.
130 The patch ecos-tx27-update.patch should be applied before compiling
135 + 'RedBoot config' partition merged with 'FIS Directory' into one
137 + improved bad block handling
138 + Flash partitioning changed due to the above
139 NOTE: The Linux kernel expects the RedBoot partition table at a
140 fixed block in flash determined by a configuration option.
141 Thus the new RedBoot version will only work with the new
143 + MAC address stored in processor internal fuse array
144 + new command: 'nand bad' to manually update the BBT