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12 >TX39 Hardware Setup</TITLE
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25 TITLE="AM33 STB Hardware Setup"
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28 TITLE="TX39 Architectural Simulator Setup"
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40 SUMMARY="Header navigation table"
57 HREF="setup-am33-stb.html"
65 >Appendix A. Target Setup</TD
71 HREF="setup-tx39-sim.html"
85 NAME="SETUP-TX39-JMR3904">TX39 Hardware Setup</H1
87 >The eCos Developer’s Kit package comes with a pair
88 of ROMs that provide GDB support for
89 the Toshiba JMR-TX3904 RISC processor reference board by way of CygMon. </P
91 >Images of these ROMs are also provided at <TT
93 >BASE_DIR/loaders/tx39-jmr3904/cygmon50.bin</TT
96 >BASE_DIR/loaders/tx39-jmr3904/cygmon66.bin</TT
98 50 MHz and 66 MHz boards respectively. The ROMs are installed to
99 sockets IC6 and IC7 on the memory daughterboard according to their
100 labels. Attention should be paid to the correct orientation of these
101 ROMs during installation.</P
103 >The GDB stub allows communication with GDB using the serial
104 port (channel C) at connector PJ1. The communication parameters
105 are fixed at 38400 baud, 8 data bits, no parity bit, and 1 stop
106 bit (8-N-1). No handshaking is employed. Connection to the host
107 computer should be made using an RS232C null modem cable.</P
109 >CygMon and eCos currently provide support for a 16Mbyte 60ns
110 72pin DRAM SIMM fitted to the PJ21 connector. Different size DRAMs
111 may require changes in the value stored in the DCCR0 register. This
112 value may be found near line 211 in <TT
117 ><version></I
121 in eCos, and near line 99 in
124 >libstub/mips/tx39jmr/tx39jmr-power.S</TT
126 CygMon. eCos does not currently use the DRAM for any purpose itself,
127 so it is entirely available for application use.</P
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145 HREF="setup-am33-stb.html"
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173 >AM33 STB Hardware Setup</TD
179 HREF="appendix-target-setup.html"
187 >TX39 Architectural Simulator Setup</TD