1 #ifndef __BSP_ARM_INSN_H__
2 #define __BSP_ARM_INSN_H__
3 //==========================================================================
7 // ARM(R) instruction descriptions.
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
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32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
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36 // this file might be covered by the GNU General Public License.
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors: gthomas
48 // Purpose: ARM(R) instruction descriptions.
49 // Description: ARM is a Registered Trademark of Advanced RISC Machines
51 // Other Brands and Trademarks are the property of their
54 //####DESCRIPTIONEND####
56 //=========================================================================
59 /* Data Processing Immediate Type */
61 unsigned immediate : 8;
67 unsigned rsv1 : 3; /* == 001b */
70 #define DPI_RSV1_VALUE 0x1
72 /* Data Processing Immediate Shift Type */
75 unsigned rsv2 : 1; /* == 0b */
77 unsigned shift_immed : 5;
82 unsigned rsv1 : 3; /* == 000b */
85 #define DPIS_RSV1_VALUE 0x0
86 #define DPIS_RSV2_VALUE 0x0
88 /* Data Processing Register Shift Type */
91 unsigned rsv3 : 1; /* == 1b */
93 unsigned rsv2 : 1; /* == 0b */
99 unsigned rsv1 : 3; /* == 000b */
102 #define DPRS_RSV1_VALUE 0x0
103 #define DPRS_RSV2_VALUE 0x0
104 #define DPRS_RSV3_VALUE 0x1
109 unsigned rsv2 : 4; /* == 1001b */
115 unsigned rsv1 : 6; /* == 000000b */
118 #define M_RSV1_VALUE 0x0
119 #define M_RSV2_VALUE 0x9
121 /* Multiply Long Type */
124 unsigned rsv2 : 4; /* == 1001b */
131 unsigned rsv1 : 5; /* == 00001b */
134 #define ML_RSV1_VALUE 0x1
135 #define ML_RSV2_VALUE 0x9
137 /* Move from status register Type */
142 unsigned rsv2 : 2; /* == 00b */
144 unsigned rsv1 : 5; /* == 00010b */
147 #define MRS_RSV1_VALUE 0x2
148 #define MRS_RSV2_VALUE 0x0
150 /* Move Immediate to status register Type */
152 unsigned immediate : 8;
156 unsigned rsv2 : 2; /* == 10b */
158 unsigned rsv1 : 5; /* == 00110b */
161 #define MISR_RSV1_VALUE 0x6
162 #define MISR_RSV2_VALUE 0x2
164 /* Move register to status register Type */
167 unsigned rsv3 : 1; /* == 0b */
171 unsigned rsv2 : 2; /* == 10b */
173 unsigned rsv1 : 5; /* == 00010b */
176 #define MRSR_RSV1_VALUE 0x2
177 #define MRSR_RSV2_VALUE 0x2
178 #define MRSR_RSV3_VALUE 0x0
180 /* Branch/Exchange Type */
183 unsigned rsv2 : 4; /* == 0001b */
187 unsigned rsv1 : 8; /* == 00010010b */
190 #define BX_RSV1_VALUE 0x12
191 #define BX_RSV2_VALUE 0x1
193 /* Load/Store Immediate Offset Type */
195 unsigned immediate : 12;
203 unsigned rsv1 : 3; /* == 010b */
206 #define LSIO_RSV1_VALUE 0x2
208 /* Load/Store Register Offset Type */
211 unsigned rsv2 : 1; /* == 0b */
213 unsigned shift_immed : 5;
221 unsigned rsv1 : 3; /* == 011b */
224 #define LSRO_RSV1_VALUE 0x3
225 #define LSRO_RSV2_VALUE 0x0
227 /* Load/Store halfword/signed byte Immediate Offset Type */
229 unsigned Lo_Offset : 4;
230 unsigned rsv4 : 1; /* == 1b */
233 unsigned rsv3 : 1; /* == 1b */
234 unsigned Hi_Offset : 4;
239 unsigned rsv2 : 1; /* == 1b */
242 unsigned rsv1 : 3; /* == 000b */
245 #define LSHWI_RSV1_VALUE 0x0
246 #define LSHWI_RSV2_VALUE 0x1
247 #define LSHWI_RSV3_VALUE 0x1
248 #define LSHWI_RSV4_VALUE 0x1
250 /* Load/Store halfword/signed byte Register Offset Type */
253 unsigned rsv4 : 1; /* == 1b */
256 unsigned rsv3 : 1; /* == 1b */
262 unsigned rsv2 : 1; /* == 0b */
265 unsigned rsv1 : 3; /* == 000b */
268 #define LSHWR_RSV1_VALUE 0x3
269 #define LSHWR_RSV2_VALUE 0x1
270 #define LSHWR_RSV3_VALUE 0x1
271 #define LSHWR_RSV4_VALUE 0x1
273 /* Swap/Swap Byte Type */
276 unsigned rsv3 : 4; /* == 1001b */
280 unsigned rsv2 : 2; /* == 00b */
282 unsigned rsv1 : 5; /* == 00010b */
285 #define SWAP_RSV1_VALUE 0x2
286 #define SWAP_RSV2_VALUE 0x0
287 #define SWAP_RSV3_VALUE 0x9
289 /* Load/Store Multiple Type */
291 unsigned Reg_List : 16 ;
298 unsigned rsv1 : 3; /* == 100b */
301 #define LSM_RSV1_VALUE 0x4
303 /* Coprocessor Data Processing Type */
306 unsigned rsv2 : 1; /* == 0b */
312 unsigned rsv1 : 4; /* == 1110b */
315 #define CPDP_RSV1_VALUE 0xE
316 #define CPDP_RSV2_VALUE 0x0
318 /* Coprocessor Register Transfer Type */
321 unsigned rsv2 : 1; /* == 1b */
328 unsigned rsv1 : 4; /* == 1110b */
331 #define CPRT_RSV1_VALUE 0xE
332 #define CPRT_RSV2_VALUE 0x1
334 /* Coprocessor Load/Store Type */
345 unsigned rsv1 : 3; /* == 110b */
348 #define CPLS_RSV1_VALUE 0x6
350 /* Branch/Branch w/ Link Type */
352 unsigned offset : 24;
354 unsigned rsv1 : 3; /* == 101b */
357 #define BBL_RSV1_VALUE 0x5
361 unsigned swi_number : 24;
362 unsigned rsv1 : 4; /* == 1111b */
365 #define SWI_RSV1_VALUE 0xF
367 /* Undefined Instruction Type */
370 unsigned rsv2 : 1; /* == 1b */
372 unsigned rsv1 : 3; /* == 011b */
375 #define UNDEF_RSV1_VALUE 0x3
376 #define UNDEF_RSV2_VALUE 0x1
381 struct dpis_type dpis;
382 struct dprs_type dprs;
386 struct misr_type misr;
387 struct mrsr_type mrsr;
389 struct lsio_type lsio;
390 struct lsro_type lsro;
391 struct lshwi_type lshwi;
392 struct lshwr_type lshwr;
393 struct swap_type swap;
395 struct cpdp_type cpdp;
396 struct cprt_type cprt;
397 struct cpls_type cpls;
400 struct undef_type undef;
404 * Conditional field values
408 #define COND_CS_HI 0x2
409 #define COND_CC_LO 0x3
424 * Data Processiong Opcode field values
426 #define DP_OPCODE_MOV 0xD
427 #define DP_OPCODE_MVN 0xF
428 #define DP_OPCODE_ADD 0x4
429 #define DP_OPCODE_ADC 0x5
430 #define DP_OPCODE_SUB 0x2
431 #define DP_OPCODE_SBC 0x6
432 #define DP_OPCODE_RSB 0x3
433 #define DP_OPCODE_RSC 0x7
434 #define DP_OPCODE_AND 0x0
435 #define DP_OPCODE_EOR 0x1
436 #define DP_OPCODE_ORR 0xC
437 #define DP_OPCODE_BIC 0xE
438 #define DP_OPCODE_CMP 0xA
439 #define DP_OPCODE_CMN 0xB
440 #define DP_OPCODE_TST 0x8
441 #define DP_OPCODE_TEQ 0x9
446 #define SHIFT_LSL 0x0
447 #define SHIFT_LSR 0x1
448 #define SHIFT_ASR 0x2
449 #define SHIFT_ROR 0x3
450 #define SHIFT_RRX 0x3 /* Special case: ROR(0) implies RRX */
453 * Load/Store indexing definitions
455 #define LS_INDEX_POST 0x0
456 #define LS_INDEX_PRE 0x1
459 * Load/Store offset operation definitions
461 #define LS_OFFSET_SUB 0x0
462 #define LS_OFFSET_ADD 0x1
465 * Load/Store size definitions
467 #define LS_SIZE_WORD 0x0
468 #define LS_SIZE_BYTE 0x1
471 * Load/Store Update definitions
473 #define LS_NO_UPDATE 0x0
474 #define LS_UPDATE 0x1
477 * Load/Store Opcode definitions
482 #endif // __BSP_ARM_INSN_H__