1 //==========================================================================
3 // devs/eth/arm/iq80321/include/devs_eth_arm_iq80321.inl
5 // IQ80321 ethernet I/O definitions.
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors:msalter
46 // Purpose: IQ80321 ethernet defintions
47 //####DESCRIPTIONEND####
48 //==========================================================================
50 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHERNET
51 #include <cyg/hal/hal_cache.h> // HAL_DCACHE_LINE_SIZE
52 #include <cyg/hal/plf_io.h> // CYGARC_UNCACHED_ADDRESS
54 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80321_I82544_ETH0
56 // Use auto speed detection
57 #define CYGHWR_DEVS_ETH_INTEL_I82544_USE_ASD
59 #define CYGHWR_INTEL_I82544_PCI_VIRT_TO_BUS( _x_ ) ((cyg_uint32)CYGARC_VIRT_TO_BUS(_x_))
60 #define CYGHWR_INTEL_I82544_PCI_BUS_TO_VIRT( _x_ ) ((cyg_uint32)CYGARC_BUS_TO_VIRT(_x_))
62 #define MAX_PACKET_SIZE 1536
63 #define SIZEOF_DESCRIPTOR 16
65 #define CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE \
66 (((MAX_PACKET_SIZE + SIZEOF_DESCRIPTOR) * \
67 (MAX_TX_DESCRIPTORS + MAX_RX_DESCRIPTORS)) + 64)
69 static char pci_mem_buffer[CYGHWR_INTEL_I82544_PCI_MEM_MAP_SIZE + HAL_DCACHE_LINE_SIZE];
71 #define CYGHWR_INTEL_I82544_PCI_MEM_MAP_BASE \
72 (CYGARC_UNCACHED_ADDRESS(((unsigned)pci_mem_buffer + HAL_DCACHE_LINE_SIZE - 1) & ~(HAL_DCACHE_LINE_SIZE - 1)))
74 static I82544 i82544_eth0_priv_data = {
75 #ifdef CYGSEM_DEVS_ETH_ARM_IQ80321_I82544_ETH0_SET_ESA
77 mac_address: CYGDAT_DEVS_ETH_ARM_IQ80321_I82544_ETH0_ESA
83 ETH_DRV_SC(i82544_sc0,
84 &i82544_eth0_priv_data, // Driver specific data
85 CYGDAT_DEVS_ETH_ARM_IQ80321_I82544_ETH0_NAME, // Name for device
97 NETDEVTAB_ENTRY(i82544_netdev0,
98 "i82544_" CYGDAT_DEVS_ETH_ARM_IQ80321_I82544_ETH0_NAME,
102 #endif // CYGPKG_DEVS_ETH_ARM_IQ80321_I82544_ETH0
105 // These arrays are used for sanity checking of pointers
107 i82544_priv_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
108 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80321_I82544_ETH0
109 &i82544_eth0_priv_data,
113 #ifdef CYGDBG_USE_ASSERTS
114 // These are only used when assertions are enabled
115 cyg_netdevtab_entry_t *
116 i82544_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
117 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80321_I82544_ETH0
123 i82544_sc_array[CYGNUM_DEVS_ETH_INTEL_I82544_DEV_COUNT] = {
124 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80321_I82544_ETH0
128 #endif // CYGDBG_USE_ASSERTS
130 // EOF devs_eth_arm_iq80321.inl