1 #ifndef _CYGONCE_ETH_CL_CS8900_H_
2 #define _CYGONCE_ETH_CL_CS8900_H_
3 //==========================================================================
7 // Cirrus Logic CS8900 Ethernet chip
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //####BSDCOPYRIGHTBEGIN####
44 // -------------------------------------------
46 // Portions of this software may have been derived from OpenBSD or other sources,
47 // and are covered by the appropriate copyright disclaimers included herein.
49 // -------------------------------------------
51 //####BSDCOPYRIGHTEND####
52 //==========================================================================
53 //#####DESCRIPTIONBEGIN####
56 // Contributors: gthomas, jskov
61 //####DESCRIPTIONEND####
63 //==========================================================================
65 #include <cyg/infra/cyg_type.h>
67 #include <cyg/hal/hal_io.h>
68 #include <pkgconf/devs_eth_cl_cs8900a.h>
71 #include CYGDAT_DEVS_ETH_CL_CS8900A_INL
74 // ------------------------------------------------------------------------
78 // 0 disables all debug output
79 // 1 for process debug output
80 // 2 for added data IO output: get_reg, put_reg
81 // 4 for packet allocation/free output
82 // 8 for only startup status, so we can tell we're installed OK
86 #define DEBUG_FUNCTION() do { diag_printf("%s\n", __FUNCTION__); } while (0)
87 #define DEBUG_LINE() do { diag_printf("%d\n", __LINE__); } while (0)
89 #define DEBUG_FUNCTION() do {} while(0)
90 #define DEBUG_LINE() do {} while(0)
93 // ------------------------------------------------------------------------
94 // Macros for keeping track of statistics
95 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
96 #define KEEP_STATISTICS
99 #ifdef KEEP_STATISTICS
100 #define INCR_STAT( _x_ ) (cpd->stats. _x_ ++)
102 #define INCR_STAT( _x_ ) CYG_EMPTY_STATEMENT
105 // ------------------------------------------------------------------------
106 // Private driver structure
107 struct cs8900a_priv_data;
108 typedef cyg_bool (*provide_esa_t)(struct cs8900a_priv_data* cpd);
110 typedef struct cs8900a_priv_data {
111 bool txbusy, hardwired_esa;
114 provide_esa_t provide_esa;
115 cyg_vector_t interrupt; // Interrupt vector used by controller
116 cyg_handle_t interrupt_handle;
117 cyg_interrupt interrupt_object;
119 cyg_uint32 txkey; // Used to ack when packet sent
120 struct cyg_netdevtab_entry *tab;
122 cyg_tick_count_t txstart;
124 } cs8900a_priv_data_t;
126 // ------------------------------------------------------------------------
127 // Macros for accessing CS registers
128 // These can be overridden by the platform header
131 # define CS_IN(_b_, _o_, _d_) HAL_READ_UINT16 ((cyg_addrword_t)(_b_)+(_o_), (_d_))
132 # define CS_OUT(_b_, _o_, _d_) HAL_WRITE_UINT16((cyg_addrword_t)(_b_)+(_o_), (_d_))
135 // ------------------------------------------------------------------------
136 // Macros allowing platform to customize some of the driver details
138 #ifndef CYGHWR_CL_CS8900A_PLF_RESET
139 # define CYGHWR_CL_CS8900A_PLF_RESET(_b_) do { } while (0)
142 #ifndef CYGHWR_CL_CS8900A_PLF_POST_RESET
143 # define CYGHWR_CL_CS8900A_PLF_POST_RESET(_b_) do { } while (0)
146 #ifndef CYGHWR_CL_CS8900A_PLF_INT_CLEAR
147 # define CYGHWR_CL_CS8900A_PLF_INT_CLEAR(_cdp_)
150 #ifndef CYGHWR_CL_CS8900A_PLF_INIT
151 #define CYGHWR_CL_CS8900A_PLF_INIT(_cdp_) do { } while (0)
155 // ------------------------------------------------------------------------
156 // Directly visible registers.
157 // Platform can override stepping or layout if necessary.
159 # define CS8900A_step 2
161 #ifndef CS8900A_RTDATA
162 # define CS8900A_RTDATA (0*CS8900A_step)
163 # define CS8900A_TxCMD (2*CS8900A_step)
164 # define CS8900A_TxLEN (3*CS8900A_step)
165 # define CS8900A_ISQ (4*CS8900A_step)
166 # define CS8900A_PPTR (5*CS8900A_step)
167 # define CS8900A_PDATA (6*CS8900A_step)
170 #ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
171 #define ISQ_RxEvent 0x0004
172 #define ISQ_TxEvent 0x0008
173 #define ISQ_BufEvent 0x000C
174 #define ISQ_RxMissEvent 0x0010
175 #define ISQ_TxColEvent 0x0012
176 #define ISQ_EventMask 0x003F
178 #define ISQ_RxEvent 0x0400
179 #define ISQ_TxEvent 0x0800
180 #define ISQ_BufEvent 0x0C00
181 #define ISQ_RxMissEvent 0x1000
182 #define ISQ_TxColEvent 0x1200
183 #define ISQ_EventMask 0x3F00
186 // ------------------------------------------------------------------------
187 // Registers available via "page pointer" (indirect access)
188 #ifndef CYGIMP_DEVS_ETH_CL_CS8900A_DATABUS_BYTE_SWAPPED
190 #define PP_ChipID 0x0000 // Chip identifier - must be 0x630e
191 #define PP_ChipRev 0x0002 // Chip revision, model codes
192 #define PP_ChipID_CL 0x630e
194 #define PP_IntReg 0x0022 // Interrupt configuration
195 #define PP_IntReg_IRQ0 0x0000 // Use INTR0 pin
196 #define PP_IntReg_IRQ1 0x0001 // Use INTR1 pin
197 #define PP_IntReg_IRQ2 0x0002 // Use INTR2 pin
198 #define PP_IntReg_IRQ3 0x0003 // Use INTR3 pin
200 #define PP_RxCFG 0x0102 // Receiver configuration
201 #define PP_RxCFG_Skip1 0x0040 // Skip (i.e. discard) current frame
202 #define PP_RxCFG_Stream 0x0080 // Enable streaming mode
203 #define PP_RxCFG_RxOK 0x0100 // RxOK interrupt enable
204 #define PP_RxCFG_RxDMAonly 0x0200 // Use RxDMA for all frames
205 #define PP_RxCFG_AutoRxDMA 0x0400 // Select RxDMA automatically
206 #define PP_RxCFG_BufferCRC 0x0800 // Include CRC characters in frame
207 #define PP_RxCFG_CRC 0x1000 // Enable interrupt on CRC error
208 #define PP_RxCFG_RUNT 0x2000 // Enable interrupt on RUNT frames
209 #define PP_RxCFG_EXTRA 0x4000 // Enable interrupt on frames with extra data
211 #define PP_RxCTL 0x0104 // Receiver control
212 #define PP_RxCTL_IAHash 0x0040 // Accept frames that match hash
213 #define PP_RxCTL_Promiscuous 0x0080 // Accept any frame
214 #define PP_RxCTL_RxOK 0x0100 // Accept well formed frames
215 #define PP_RxCTL_Multicast 0x0200 // Accept multicast frames
216 #define PP_RxCTL_IA 0x0400 // Accept frame that matches IA
217 #define PP_RxCTL_Broadcast 0x0800 // Accept broadcast frames
218 #define PP_RxCTL_CRC 0x1000 // Accept frames with bad CRC
219 #define PP_RxCTL_RUNT 0x2000 // Accept runt frames
220 #define PP_RxCTL_EXTRA 0x4000 // Accept frames that are too long
222 #define PP_TxCFG 0x0106 // Transmit configuration
223 #define PP_TxCFG_CRS 0x0040 // Enable interrupt on loss of carrier
224 #define PP_TxCFG_SQE 0x0080 // Enable interrupt on Signal Quality Error
225 #define PP_TxCFG_TxOK 0x0100 // Enable interrupt on successful xmits
226 #define PP_TxCFG_Late 0x0200 // Enable interrupt on "out of window"
227 #define PP_TxCFG_Jabber 0x0400 // Enable interrupt on jabber detect
228 #define PP_TxCFG_Collision 0x0800 // Enable interrupt if collision
229 #define PP_TxCFG_16Collisions 0x8000 // Enable interrupt if > 16 collisions
231 #define PP_TxCmd 0x0108 // Transmit command status
232 #define PP_TxCmd_TxStart_5 0x0000 // Start after 5 bytes in buffer
233 #define PP_TxCmd_TxStart_381 0x0040 // Start after 381 bytes in buffer
234 #define PP_TxCmd_TxStart_1021 0x0080 // Start after 1021 bytes in buffer
235 #define PP_TxCmd_TxStart_Full 0x00C0 // Start after all bytes loaded
236 #define PP_TxCmd_Force 0x0100 // Discard any pending packets
237 #define PP_TxCmd_OneCollision 0x0200 // Abort after a single collision
238 #define PP_TxCmd_NoCRC 0x1000 // Do not add CRC
239 #define PP_TxCmd_NoPad 0x2000 // Do not pad short packets
241 #define PP_BufCFG 0x010A // Buffer configuration
242 #define PP_BufCFG_SWI 0x0040 // Force interrupt via software
243 #define PP_BufCFG_RxDMA 0x0080 // Enable interrupt on Rx DMA
244 #define PP_BufCFG_TxRDY 0x0100 // Enable interrupt when ready for Tx
245 #define PP_BufCFG_TxUE 0x0200 // Enable interrupt in Tx underrun
246 #define PP_BufCFG_RxMiss 0x0400 // Enable interrupt on missed Rx packets
247 #define PP_BufCFG_Rx128 0x0800 // Enable Rx interrupt after 128 bytes
248 #define PP_BufCFG_TxCol 0x1000 // Enable int on Tx collision ctr overflow
249 #define PP_BufCFG_Miss 0x2000 // Enable int on Rx miss ctr overflow
250 #define PP_BufCFG_RxDest 0x8000 // Enable int on Rx dest addr match
252 #define PP_LineCTL 0x0112 // Line control
253 #define PP_LineCTL_Rx 0x0040 // Enable receiver
254 #define PP_LineCTL_Tx 0x0080 // Enable transmitter
256 #define PP_RER 0x0124 // Receive event
257 #define PP_RER_IAHash 0x0040 // Frame hash match
258 #define PP_RER_Dribble 0x0080 // Frame had 1-7 extra bits after last byte
259 #define PP_RER_RxOK 0x0100 // Frame received with no errors
260 #define PP_RER_Hashed 0x0200 // Frame address hashed OK
261 #define PP_RER_IA 0x0400 // Frame address matched IA
262 #define PP_RER_Broadcast 0x0800 // Broadcast frame
263 #define PP_RER_CRC 0x1000 // Frame had CRC error
264 #define PP_RER_RUNT 0x2000 // Runt frame
265 #define PP_RER_EXTRA 0x4000 // Frame was too long
267 #define PP_TER 0x0128 // Transmit event
268 #define PP_TER_CRS 0x0040 // Carrier lost
269 #define PP_TER_SQE 0x0080 // Signal Quality Error
270 #define PP_TER_TxOK 0x0100 // Packet sent without error
271 #define PP_TER_Late 0x0200 // Out of window
272 #define PP_TER_Jabber 0x0400 // Stuck transmit?
273 #define PP_TER_NumCollisions 0x7800 // Number of collisions
274 #define PP_TER_16Collisions 0x8000 // > 16 collisions
276 #define PP_SelfCtl 0x0114 // Chip control
277 #define PP_SelfCtl_Reset 0x0040 // Self-clearing reset
279 #define PP_BusCtl 0x0116 // Bus control
280 #define PP_BusCtl_ResetRxDMA 0x0040 // Reset receiver DMA engine
281 #define PP_BusCtl_DMAextend 0x0100
282 #define PP_BusCtl_UseSA 0x0200
283 #define PP_BusCtl_MemoryE 0x0400 // Enable "memory mode"
284 #define PP_BusCtl_DMAburst 0x0800
285 #define PP_BusCtl_IOCH_RDYE 0x1000
286 #define PP_BusCtl_RxDMAsize 0x2000
287 #define PP_BusCtl_EnableIRQ 0x8000 // Enable interrupts
289 #define PP_LineStat 0x0134 // Line status
290 #define PP_LineStat_LinkOK 0x0080 // Line is connected and working
291 #define PP_LineStat_AUI 0x0100 // Connected via AUI
292 #define PP_LineStat_10BT 0x0200 // Connected via twisted pair
293 #define PP_LineStat_Polarity 0x1000 // Line polarity OK (10BT only)
294 #define PP_LineStat_CRS 0x4000 // Frame being received
296 #define PP_SelfStat 0x0136 // Chip status
297 #define PP_SelfStat_InitD 0x0080 // Chip initialization complete
298 #define PP_SelfStat_SIBSY 0x0100 // EEPROM is busy
299 #define PP_SelfStat_EEPROM 0x0200 // EEPROM present
300 #define PP_SelfStat_EEPROM_OK 0x0400 // EEPROM checks out
301 #define PP_SelfStat_ELPresent 0x0800 // External address latch logic available
302 #define PP_SelfStat_EEsize 0x1000 // Size of EEPROM
304 #define PP_BusStat 0x0138 // Bus status
305 #define PP_BusStat_TxBid 0x0080 // Tx error
306 #define PP_BusStat_TxRDY 0x0100 // Ready for Tx data
308 #define PP_LAF 0x0150 // Logical address filter (6 bytes)
309 #define PP_IA 0x0158 // Individual address (MAC)
313 #define PP_ChipID 0x0000 // Chip identifier - must be 0x0e63
314 #define PP_ChipRev 0x0200 // Chip revision, model codes
315 #define PP_ChipID_CL 0x0e63
317 #define PP_IntReg 0x2200 // Interrupt configuration
318 #define PP_IntReg_IRQ0 0x0000 // Use INTR0 pin
319 #define PP_IntReg_IRQ1 0x0100 // Use INTR1 pin
320 #define PP_IntReg_IRQ2 0x0200 // Use INTR2 pin
321 #define PP_IntReg_IRQ3 0x0300 // Use INTR3 pin
323 #define PP_RxCFG 0x0201 // Receiver configuration
324 #define PP_RxCFG_Skip1 0x4000 // Skip (i.e. discard) current frame
325 #define PP_RxCFG_Stream 0x8000 // Enable streaming mode
326 #define PP_RxCFG_RxOK 0x0001 // RxOK interrupt enable
327 #define PP_RxCFG_RxDMAonly 0x0002 // Use RxDMA for all frames
328 #define PP_RxCFG_AutoRxDMA 0x0004 // Select RxDMA automatically
329 #define PP_RxCFG_BufferCRC 0x0008 // Include CRC characters in frame
330 #define PP_RxCFG_CRC 0x0010 // Enable interrupt on CRC error
331 #define PP_RxCFG_RUNT 0x0020 // Enable interrupt on RUNT frames
332 #define PP_RxCFG_EXTRA 0x0040 // Enable interrupt on frames with extra data
334 #define PP_RxCTL 0x0401 // Receiver control
335 #define PP_RxCTL_IAHash 0x4000 // Accept frames that match hash
336 #define PP_RxCTL_Promiscuous 0x8000 // Accept any frame
337 #define PP_RxCTL_RxOK 0x0001 // Accept well formed frames
338 #define PP_RxCTL_Multicast 0x0002 // Accept multicast frames
339 #define PP_RxCTL_IA 0x0004 // Accept frame that matches IA
340 #define PP_RxCTL_Broadcast 0x0008 // Accept broadcast frames
341 #define PP_RxCTL_CRC 0x0010 // Accept frames with bad CRC
342 #define PP_RxCTL_RUNT 0x0020 // Accept runt frames
343 #define PP_RxCTL_EXTRA 0x0040 // Accept frames that are too long
345 #define PP_TxCFG 0x0601 // Transmit configuration
346 #define PP_TxCFG_CRS 0x4000 // Enable interrupt on loss of carrier
347 #define PP_TxCFG_SQE 0x8000 // Enable interrupt on Signal Quality Error
348 #define PP_TxCFG_TxOK 0x0001 // Enable interrupt on successful xmits
349 #define PP_TxCFG_Late 0x0002 // Enable interrupt on "out of window"
350 #define PP_TxCFG_Jabber 0x0004 // Enable interrupt on jabber detect
351 #define PP_TxCFG_Collision 0x0008 // Enable interrupt if collision
352 #define PP_TxCFG_16Collisions 0x0080 // Enable interrupt if > 16 collisions
354 #define PP_TxCmd 0x0801 // Transmit command status
355 #define PP_TxCmd_TxStart_5 0x0000 // Start after 5 bytes in buffer
356 #define PP_TxCmd_TxStart_381 0x4000 // Start after 381 bytes in buffer
357 #define PP_TxCmd_TxStart_1021 0x8000 // Start after 1021 bytes in buffer
358 #define PP_TxCmd_TxStart_Full 0xC000 // Start after all bytes loaded
359 #define PP_TxCmd_Force 0x0001 // Discard any pending packets
360 #define PP_TxCmd_OneCollision 0x0002 // Abort after a single collision
361 #define PP_TxCmd_NoCRC 0x0010 // Do not add CRC
362 #define PP_TxCmd_NoPad 0x0020 // Do not pad short packets
364 #define PP_BufCFG 0x0A01 // Buffer configuration
365 #define PP_BufCFG_SWI 0x4000 // Force interrupt via software
366 #define PP_BufCFG_RxDMA 0x8000 // Enable interrupt on Rx DMA
367 #define PP_BufCFG_TxRDY 0x0001 // Enable interrupt when ready for Tx
368 #define PP_BufCFG_TxUE 0x0002 // Enable interrupt in Tx underrun
369 #define PP_BufCFG_RxMiss 0x0004 // Enable interrupt on missed Rx packets
370 #define PP_BufCFG_Rx128 0x0008 // Enable Rx interrupt after 128 bytes
371 #define PP_BufCFG_TxCol 0x0010 // Enable int on Tx collision ctr overflow
372 #define PP_BufCFG_Miss 0x0020 // Enable int on Rx miss ctr overflow
373 #define PP_BufCFG_RxDest 0x0080 // Enable int on Rx dest addr match
375 #define PP_LineCTL 0x1201 // Line control
376 #define PP_LineCTL_Rx 0x4000 // Enable receiver
377 #define PP_LineCTL_Tx 0x8000 // Enable transmitter
379 #define PP_RER 0x2401 // Receive event
380 #define PP_RER_IAHash 0x4000 // Frame hash match
381 #define PP_RER_Dribble 0x8000 // Frame had 1-7 extra bits after last byte
382 #define PP_RER_RxOK 0x0001 // Frame received with no errors
383 #define PP_RER_Hashed 0x0002 // Frame address hashed OK
384 #define PP_RER_IA 0x0004 // Frame address matched IA
385 #define PP_RER_Broadcast 0x0008 // Broadcast frame
386 #define PP_RER_CRC 0x0010 // Frame had CRC error
387 #define PP_RER_RUNT 0x0020 // Runt frame
388 #define PP_RER_EXTRA 0x0040 // Frame was too long
390 #define PP_TER 0x2801 // Transmit event
391 #define PP_TER_CRS 0x4000 // Carrier lost
392 #define PP_TER_SQE 0x8000 // Signal Quality Error
393 #define PP_TER_TxOK 0x0001 // Packet sent without error
394 #define PP_TER_Late 0x0002 // Out of window
395 #define PP_TER_Jabber 0x0004 // Stuck transmit?
396 #define PP_TER_NumCollisions 0x0078 // Number of collisions
397 #define PP_TER_16Collisions 0x0080 // > 16 collisions
399 #define PP_SelfCtl 0x1401 // Chip control
400 #define PP_SelfCtl_Reset 0x4000 // Self-clearing reset
402 #define PP_BusCtl 0x1601 // Bus control
403 #define PP_BusCtl_ResetRxDMA 0x4000 // Reset receiver DMA engine
404 #define PP_BusCtl_DMAextend 0x0001
405 #define PP_BusCtl_UseSA 0x0002
406 #define PP_BusCtl_MemoryE 0x0004 // Enable "memory mode"
407 #define PP_BusCtl_DMAburst 0x0008
408 #define PP_BusCtl_IOCH_RDYE 0x0010
409 #define PP_BusCtl_RxDMAsize 0x0020
410 #define PP_BusCtl_EnableIRQ 0x0080 // Enable interrupts
412 #define PP_LineStat 0x3401 // Line status
413 #define PP_LineStat_LinkOK 0x8000 // Line is connected and working
414 #define PP_LineStat_AUI 0x0001 // Connected via AUI
415 #define PP_LineStat_10BT 0x0002 // Connected via twisted pair
416 #define PP_LineStat_Polarity 0x0010 // Line polarity OK (10BT only)
417 #define PP_LineStat_CRS 0x0040 // Frame being received
419 #define PP_SelfStat 0x3601 // Chip status
420 #define PP_SelfStat_InitD 0x8000 // Chip initialization complete
421 #define PP_SelfStat_SIBSY 0x0001 // EEPROM is busy
422 #define PP_SelfStat_EEPROM 0x0002 // EEPROM present
423 #define PP_SelfStat_EEPROM_OK 0x0004 // EEPROM checks out
424 #define PP_SelfStat_ELPresent 0x0008 // External address latch logic available
425 #define PP_SelfStat_EEsize 0x0010 // Size of EEPROM
427 #define PP_BusStat 0x3801 // Bus status
428 #define PP_BusStat_TxBid 0x8000 // Tx error
429 #define PP_BusStat_TxRDY 0x0001 // Ready for Tx data
431 #define PP_LAF 0x5001 // Logical address filter (6 bytes)
432 #define PP_IA 0x5801 // Individual address (MAC)
436 // ------------------------------------------------------------------------
437 // "page pointer" access functions
438 static __inline__ cyg_uint16
439 get_reg(cyg_addrword_t base, int regno)
442 HAL_WRITE_UINT16(base+CS8900A_PPTR, regno);
443 HAL_READ_UINT16(base+CS8900A_PDATA, val);
445 diag_printf("get_reg(%p, %d) => 0x%04x\n", base, regno, val);
450 static __inline__ void
451 put_reg(cyg_addrword_t base, int regno, cyg_uint16 val)
454 diag_printf("put_reg(%p, %d, 0x%04x)\n", base, regno, val);
456 HAL_WRITE_UINT16(base+CS8900A_PPTR, regno);
457 HAL_WRITE_UINT16(base+CS8900A_PDATA, val);
460 #endif // _CYGONCE_ETH_CL_CS8900_H_