1 //==========================================================================
5 // Davicom DM9000 ethernet driver
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2003, 2004 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //#####DESCRIPTIONBEGIN####
43 // Contributors: msalter
46 // Description: hardware driver for Davicom DM9000 NIC
49 //####DESCRIPTIONEND####
51 //==========================================================================
53 #include <pkgconf/system.h>
54 #include <pkgconf/io_eth_drivers.h>
55 #include <pkgconf/devs_eth_davicom_dm9000.h>
56 #include <cyg/infra/cyg_type.h>
57 #include <cyg/infra/cyg_ass.h>
58 #include <cyg/hal/hal_arch.h>
59 #include <cyg/hal/hal_cache.h>
60 #include <cyg/hal/hal_intr.h>
61 #include <cyg/hal/hal_endian.h>
62 #include <cyg/infra/diag.h>
63 #include <cyg/hal/hal_if.h>
64 #include <cyg/hal/drv_api.h>
65 #include <cyg/io/eth/netdev.h>
66 #include <cyg/io/eth/eth_drv.h>
68 #include <dm9000_info.h>
71 #include <pkgconf/redboot.h>
73 #include <flash_config.h>
76 #include CYGDAT_DEVS_ETH_DAVICOM_DM9000_INL
78 #define DM9000_PKT_MAX 1536
81 // Control and Status register offsets
103 #define DM_TRPAL 0x22
104 #define DM_TRPAH 0x23
105 #define DM_RWPAL 0x24
106 #define DM_RWPAH 0x25
111 #define DM_CHIPR 0x2c
113 #define DM_MRCMDX 0xf0
114 #define DM_MRCMD 0xf2
115 #define DM_MDRAL 0xf4
116 #define DM_MDRAH 0xf5
117 #define DM_MWCMDX 0xf6
118 #define DM_MWCMD 0xf8
119 #define DM_MDWAL 0xfa
120 #define DM_MDWAH 0xfb
121 #define DM_TXPLL 0xfc
122 #define DM_TXPLH 0xfd
126 // NCR (Network Control Register)
127 #define NCR_EXT_PHY (1 << 7) // 1 ==> external PHY, 0 ==> internal
128 #define NCR_WAKEEN (1 << 6) // enable wakeup events
129 #define NCR_FCOL (1 << 4) // force collision mode (test)
130 #define NCR_FDX (1 << 3) // full duplex (read-only for internal phy)
131 #define NCR_LBK_NOR (0 << 1) // loopback off
132 #define NCR_LBK_MAC (1 << 1) // MAC loopback
133 #define NCR_LBK_PHY (2 << 1) // PHY loopback
134 #define NCR_RST (1 << 0) // Reset (auto-clears after 10us)
136 // NSR (Network Status Register)
137 #define NSR_SPEED (1 << 7) // 0 = 100Mbps, 1 = 10Mbps
138 #define NSR_LINKST (1 << 6) // link status (1 = okay)
139 #define NSR_WAKEST (1 << 5) // wake status (clear by read)
140 #define NSR_TX2END (1 << 3) // TX packet 2 complete
141 #define NSR_TX1END (1 << 2) // TX packet 1 complete
142 #define NSR_RXOV (1 << 1) // RX overflow
144 // TCR (TX Control Register)
145 #define TCR_TJDIS (1 << 6) // TX jabber disable
146 #define TCR_EXCECM (1 << 5) // 0 = abort after 15 collisions
147 #define TCR_PAD_DIS2 (1 << 4)
148 #define TCR_CRC_DIS2 (1 << 3)
149 #define TCR_PAD_DIS1 (1 << 2)
150 #define TCR_CRC_DIS1 (1 << 1)
151 #define TCR_TXREQ (1 << 0)
153 // TSR (TX Status Register)
154 #define TSR_TJTO (1 << 7)
155 #define TSR_LC (1 << 6)
156 #define TSR_NC (1 << 5)
157 #define TSR_LCOL (1 << 4)
158 #define TSR_COL (1 << 3)
159 #define TSR_EC (1 << 2)
161 // RCR (RX Control Register)
162 #define RCR_WTDIS (1 << 6)
163 #define RCR_DIS_LONG (1 << 5)
164 #define RCR_DIS_CRC (1 << 4)
165 #define RCR_ALL (1 << 3)
166 #define RCR_RUNT (1 << 2)
167 #define RCR_PRMSC (1 << 1)
168 #define RCR_RXEN (1 << 0)
170 // RSR (RX Status Register)
171 #define RSR_RF (1 << 7)
172 #define RSR_MF (1 << 6)
173 #define RSR_LCS (1 << 5)
174 #define RSR_RWTO (1 << 4)
175 #define RSR_PLE (1 << 3)
176 #define RSR_AE (1 << 2)
177 #define RSR_CE (1 << 1)
178 #define RSR_FOE (1 << 0)
180 // FCR (Flow Control Register)
181 #define FCR_TXPO (1 << 7)
182 #define FCR_TXPF (1 << 6)
183 #define FCR_TXPEN (1 << 5)
184 #define FCR_BKPA (1 << 4)
185 #define FCR_BKPM (1 << 3)
186 #define FCR_RXPS (1 << 2)
187 #define FCR_RXPCS (1 << 1)
188 #define FCR_FLCE (1 << 0)
190 // EPCR (EEPROM & PHY Control Register)
191 #define EPCR_REEP (1 << 5)
192 #define EPCR_WEP (1 << 4)
193 #define EPCR_EPOS (1 << 3)
194 #define EPCR_ERPRR (1 << 2)
195 #define EPCR_ERPRW (1 << 1)
196 #define EPCR_ERRE (1 << 0)
198 // WCR (Wakeup Control Register)
199 #define WCR_LINKEN (1 << 5)
200 #define WCR_SAMPLEEN (1 << 4)
201 #define WCR_MAGICEN (1 << 3)
202 #define WCR_LINKST (1 << 2)
203 #define WCR_SAMPLEST (1 << 1)
204 #define WCR_MAGIGST (1 << 0)
206 // SMCR (Special Mode Control Register)
207 #define SMCR_SM_EN (1 << 7)
208 #define SMCR_FLC (1 << 2)
209 #define SMCR_FB1 (1 << 1)
210 #define SMCR_FB0 (1 << 0)
212 // ISR (Interrupt Status Register)
213 #define ISR_IOMODE_16 (0 << 6)
214 #define ISR_IOMODE_32 (1 << 6)
215 #define ISR_IOMODE_8 (2 << 6)
216 #define ISR_ROOS (1 << 3)
217 #define ISR_ROS (1 << 2)
218 #define ISR_PTS (1 << 1)
219 #define ISR_PRS (1 << 0)
221 // IMR (Interrupt Mask Register)
222 #define IMR_PAR (1 << 7)
223 #define IMR_ROOM (1 << 3)
224 #define IMR_ROM (1 << 2)
225 #define IMR_PTM (1 << 1)
226 #define IMR_PRM (1 << 0)
229 // Read one datum from 8-bit bus
230 static int read_data_8(struct dm9000 *p, cyg_uint8 *dest)
232 HAL_READ_UINT8(p->io_data, *dest);
236 // Read one datum from 16-bit bus
237 static int read_data_16(struct dm9000 *p, cyg_uint8 *dest)
241 HAL_READ_UINT16(p->io_data, val);
242 memcpy(dest, &val, 2);
246 // Read one datum from 32-bit bus
247 static int read_data_32(struct dm9000 *p, cyg_uint8 *dest)
251 HAL_READ_UINT32(p->io_data, val);
252 memcpy(dest, &val, 4);
257 // Write one datum to 8-bit bus
258 static int write_data_8(struct dm9000 *p, cyg_uint8 *src)
260 HAL_WRITE_UINT8(p->io_data, *src);
264 // Write one datum to 16-bit bus
265 static int write_data_16(struct dm9000 *p, cyg_uint8 *src)
269 memcpy(&val, src, 2);
270 HAL_WRITE_UINT16(p->io_data, val);
274 // Write one datum to 32-bit bus
275 static int write_data_32(struct dm9000 *p, cyg_uint8 *src)
279 memcpy(&val, src, 4);
280 HAL_WRITE_UINT32(p->io_data, val);
286 // Return one byte from DM9000 register
287 static cyg_uint8 getreg(struct dm9000 *p, cyg_uint8 reg)
290 HAL_WRITE_UINT8(p->io_addr, reg);
291 HAL_READ_UINT8(p->io_data, val);
295 // Write one byte to DM9000 register
296 static void putreg(struct dm9000 *p, cyg_uint8 reg, cyg_uint8 val)
298 HAL_WRITE_UINT8(p->io_addr, reg);
299 HAL_WRITE_UINT8(p->io_data, val);
302 // Read a word from EEPROM
303 static cyg_uint16 eeprom_read(struct dm9000 *p, int offset)
305 putreg(p, DM_EPAR, offset);
306 putreg(p, DM_EPCR, EPCR_ERPRR);
307 while (getreg(p, DM_EPCR) & EPCR_ERRE)
309 CYGACC_CALL_IF_DELAY_US(200);
310 putreg(p, DM_EPCR, 0);
311 return getreg(p, DM_EPDRL) | (getreg(p, DM_EPDRH) << 8);
314 // Write a word to EEPROM
315 static void eeprom_write(struct dm9000 *p, int offset, cyg_uint16 val)
317 putreg(p, DM_EPAR, offset);
318 putreg(p, DM_EPDRH, val >> 8);
319 putreg(p, DM_EPDRL, val);
320 putreg(p, DM_EPCR, EPCR_WEP | EPCR_ERPRW);
321 while (getreg(p, DM_EPCR) & EPCR_ERRE)
323 CYGACC_CALL_IF_DELAY_US(200);
324 putreg(p, DM_EPCR, 0);
327 // Reload info from EEPROM
328 static void eeprom_reload(struct dm9000 *p)
330 putreg(p, DM_EPCR, EPCR_REEP);
331 while (getreg(p, DM_EPCR) & EPCR_ERRE)
333 CYGACC_CALL_IF_DELAY_US(200);
334 putreg(p, DM_EPCR, 0);
338 // Read a word from PHY
339 static cyg_uint16 phy_read(struct dm9000 *p, int offset)
341 putreg(p, DM_EPAR, 0x40 + offset);
342 putreg(p, DM_EPCR, EPCR_EPOS | EPCR_ERPRR);
343 CYGACC_CALL_IF_DELAY_US(200);
344 putreg(p, DM_EPCR, 0);
345 return getreg(p, DM_EPDRL) | (getreg(p, DM_EPDRH) << 8);
348 // Write a word to PHY
349 static void phy_write(struct dm9000 *p, int offset, cyg_uint16 val)
351 putreg(p, DM_EPAR, 0x40 + offset);
352 putreg(p, DM_EPDRL, val);
353 putreg(p, DM_EPDRH, val >> 8);
354 putreg(p, DM_EPCR, EPCR_EPOS | EPCR_ERPRW);
355 CYGACC_CALL_IF_DELAY_US(500);
356 putreg(p, DM_EPCR, 0);
360 static void init_phy(struct dm9000 *p)
362 phy_write(p, 4, 0x1e1); // Advertise 10/100 half/full duplex w/CSMA
363 phy_write(p, 0, 0x1200); // enable autoneg
366 putreg(p, DM_GPCR, 1);
367 putreg(p, DM_GPR, 0);
371 static inline void dm9000_reset(struct dm9000 *p)
373 putreg(p, DM_NCR, NCR_RST);
374 CYGACC_CALL_IF_DELAY_US(100);
377 static int initialize_nic(struct dm9000 *priv)
383 switch (getreg(priv, DM_ISR) >> 6) {
385 priv->read_data = read_data_16;
386 priv->write_data = write_data_16;
390 priv->read_data = read_data_32;
391 priv->write_data = write_data_32;
395 priv->read_data = read_data_8;
396 priv->write_data = write_data_8;
400 diag_printf("Unknown DM9000 bus i/f.\n");
406 putreg(priv, DM_TCR, 0);
407 putreg(priv, DM_BPTR, 0x3f);
408 putreg(priv, DM_FCTR, 0x38);
409 putreg(priv, DM_FCR, 0xff);
410 putreg(priv, DM_SMCR, 0);
411 putreg(priv, DM_NSR, NSR_WAKEST | NSR_TX1END | NSR_TX2END);
412 putreg(priv, DM_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
415 for (i = 0; i < 6; i++)
416 putreg(priv, DM_PAR + i, priv->mac_address[i]);
418 // clear multicast table except for broadcast address
419 for (i = 0; i < 6; i++)
420 putreg(priv, DM_MAR + i, 0x00);
421 putreg(priv, DM_MAR + 6, 0x00);
422 putreg(priv, DM_MAR + 7, 0x80);
428 // ------------------------------------------------------------------------
430 // API Function : dm9000_init
432 // ------------------------------------------------------------------------
434 dm9000_init(struct cyg_netdevtab_entry * ndp)
436 struct eth_drv_sc *sc;
440 unsigned short u16tab[64];
442 sc = (struct eth_drv_sc *)ndp->device_instance;
443 priv = (struct dm9000 *)sc->driver_private;
447 #ifdef CYG_HAL_DM9000_PRESENT
448 if (!CYG_HAL_DM9000_PRESENT())
452 id = getreg(priv, DM_VIDL);
453 id |= getreg(priv, DM_VIDH) << 8;
454 id |= getreg(priv, DM_PIDL) << 16;
455 id |= getreg(priv, DM_PIDH) << 24;
457 if (id != 0x90000A46)
460 for (i = 0; i < 64; i++)
461 u16tab[i] = eeprom_read(priv, i);
469 eeprom_write(priv, 6, u16tab[6]);
470 eeprom_write(priv, 3, u16tab[3]);
476 for (i = 0; i < 64; i++)
477 u16tab[i] = eeprom_read(priv, i);
478 } while ((u16tab[0] | u16tab[1] | u16tab[2]) == 0);
480 priv->mac_address[0] = u16tab[0];
481 priv->mac_address[1] = u16tab[0] >> 8;
482 priv->mac_address[2] = u16tab[1];
483 priv->mac_address[3] = u16tab[1] >> 8;
484 priv->mac_address[4] = u16tab[2];
485 priv->mac_address[5] = u16tab[2] >> 8;
487 if (!initialize_nic(priv))
490 // Initialize upper level driver
491 (sc->funs->eth_drv->init)(sc, &(priv->mac_address[0]) );
495 // ------------------------------------------------------------------------
497 // API Function : dm9000_start
499 // ------------------------------------------------------------------------
501 dm9000_start( struct eth_drv_sc *sc, unsigned char *enaddr, int flags )
503 struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
506 putreg(priv, DM_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
509 putreg(priv, DM_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
514 // ------------------------------------------------------------------------
516 // API Function : dm9000_stop
518 // ------------------------------------------------------------------------
520 dm9000_stop( struct eth_drv_sc *sc )
522 struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
525 putreg(priv, DM_RCR, 0);
528 putreg(priv, DM_IMR, IMR_PAR);
534 // ------------------------------------------------------------------------
536 // API Function : dm9000_recv
538 // ------------------------------------------------------------------------
540 dm9000_recv( struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len )
542 struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
543 struct eth_drv_sg *sg = sg_list;
546 int len, total_len, nread, n, leftover;
548 total_len = priv->rxlen;
549 nread = leftover = 0;
551 // diag_printf("dm9000_recv: total_len=%d\n", total_len);
557 // diag_printf("recv: buf=%p len=%d to_read=%d, leftover=%d\n", p, len, total_len - nread, leftover);
559 if ((nread + len) > total_len)
560 len = total_len - nread;
563 if (leftover <= len) {
564 memcpy(p, tmpbuf + (sizeof(tmpbuf) - leftover), leftover);
570 memcpy(p, tmpbuf + (sizeof(tmpbuf) - leftover), len);
578 while (len >= sizeof(tmpbuf)) {
579 n = priv->read_data(priv, p);
586 n = priv->read_data(priv, tmpbuf);
588 memcpy(p, tmpbuf, n);
593 memcpy(p, tmpbuf, len);
601 } while (nread < total_len);
605 for (sg = sg_list; sg < (sg_list + sg_len); sg++) {
607 diag_dump_buf(sg->buf, sg->len);
612 // ------------------------------------------------------------------------
614 // API Function : dm9000_can_send
616 // ------------------------------------------------------------------------
618 dm9000_can_send(struct eth_drv_sc *sc)
620 struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
622 if (!priv->active || priv->txbusy || priv->reset_pending)
629 // ------------------------------------------------------------------------
631 // API Function : dm9000_send
633 // ------------------------------------------------------------------------
635 dm9000_send(struct eth_drv_sc *sc,
636 struct eth_drv_sg *sg_list, int sg_len,
637 int total_len, unsigned long key)
639 struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
640 struct eth_drv_sg *sg = sg_list;
642 int i, len, extra, n, save_len;
646 diag_printf("dm9000_send: NCR[%02x] NSR[%02x] TPL[%02x]\n",
647 getreg(priv, DM_NCR), getreg(priv, DM_NSR),
648 getreg(priv, DM_TRPAL) | (getreg(priv, DM_TRPAH) << 8)
654 save_len = total_len;
657 HAL_WRITE_UINT8(priv->io_addr, DM_MWCMD);
659 while (total_len > 0) {
666 n = sizeof(tmpbuf) - extra;
667 memcpy(tmpbuf + extra, p, n);
670 for (i = 0; i < sizeof(tmpbuf) && total_len > 0; i += n) {
671 n = priv->write_data(priv, tmpbuf + i);
677 while (len >= sizeof(tmpbuf) && total_len > 0) {
678 n = priv->write_data(priv, p);
684 if (len > 0 && total_len > 0) {
686 memcpy(tmpbuf, p, extra);
688 if ((total_len - extra) <= 0) {
689 // go ahead and write it now
690 for (i = 0; total_len > 0; i += n, total_len -= n) {
691 n = priv->write_data(priv, tmpbuf + i);
702 putreg(priv, DM_TXPLL, save_len);
703 putreg(priv, DM_TXPLH, save_len >> 8);
705 putreg(priv, DM_TCR, TCR_TXREQ);
710 // ------------------------------------------------------------------------
712 // API Function : dm9000_poll
714 // ------------------------------------------------------------------------
716 dm9000_poll(struct eth_drv_sc *sc)
718 struct dm9000 *priv = (struct dm9000 *)sc->driver_private;
719 cyg_uint8 status, rxstat, rx1;
720 cyg_uint16 pkt_stat, pkt_len;
724 putreg(priv, DM_IMR, IMR_PAR);
726 // get and clear staus
727 status = getreg(priv, DM_ISR);
728 putreg(priv, DM_ISR, status);
731 if (1 /*status & ISR_PRS*/) {
733 rx1 = getreg(priv, DM_MRCMDX);
734 HAL_READ_UINT8(priv->io_data, rxstat);
736 // check for packet ready
741 HAL_WRITE_UINT8(priv->io_addr, DM_MRCMD);
742 for (i = 0, cp = (cyg_uint8 *)u16; i < 4; )
743 i += priv->read_data(priv, cp + i);
745 u16[0] = CYG_LE16_TO_CPU(u16[0]);
746 u16[1] = CYG_LE16_TO_CPU(u16[1]);
748 #if (CYG_BYTEORDER == CYG_MSBFIRST)
757 diag_printf("pkt_stat=%04x pkt_len=%04x\n", pkt_stat, pkt_len);
760 if (pkt_len < 0x40) {
761 diag_printf("packet too short: %d (0x%04x)\n", pkt_len, pkt_len);
764 i += priv->read_data(priv, cp);
765 } else if (pkt_len > 1536) {
766 priv->reset_pending = 1;
767 diag_printf("packet too long: %d (0x%04x)\n", pkt_len, pkt_len);
768 } else if (pkt_stat & 0xbf00) {
769 diag_printf("bad packet status: 0x%04x\n", pkt_stat);
772 i += priv->read_data(priv, cp);
775 priv->rxlen = pkt_len;
776 (sc->funs->eth_drv->recv)(sc, pkt_len);
779 } else if (rxstat > 1) {
780 // this should never happen.
781 diag_printf("unknown rxstat byte: %d\n", rxstat);
782 priv->reset_pending = 1;
787 // check transmit status
788 if (status & ISR_PTS) {
791 txstat = getreg(priv, DM_NSR);
793 if (txstat & (NSR_TX1END | NSR_TX2END)) {
794 if (txstat & NSR_TX1END)
795 txstat = getreg(priv, DM_TSRI);
797 txstat = getreg(priv, DM_TSRII);
799 if (txstat & TSR_COL) {
803 if (getreg(priv, DM_TRPAL) & 3) {
804 // NIC bug detected. Need to reset.
805 priv->reset_pending = 1;
806 diag_printf("NIC collision bug detected!\n");
809 (sc->funs->eth_drv->tx_done)(sc, priv->txkey, 0);
814 if (priv->reset_pending && !priv->txbusy) {
815 initialize_nic(priv);
818 putreg(priv, DM_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
820 priv->reset_pending = 0;
824 putreg(priv, DM_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
828 // ------------------------------------------------------------------------
830 // API Function : dm9000_deliver
832 // ------------------------------------------------------------------------
834 dm9000_deliver(struct eth_drv_sc *sc)
839 // ------------------------------------------------------------------------
841 // API Function : dm9000_int_vector
843 // ------------------------------------------------------------------------
845 dm9000_int_vector(struct eth_drv_sc *sc)
848 priv = (struct dm9000 *)sc->driver_private;
854 // ------------------------------------------------------------------------
856 // API Function : dm9000_ioctl
858 // ------------------------------------------------------------------------
860 dm9000_ioctl(struct eth_drv_sc *sc, unsigned long key,
861 void *data, int data_length)
866 // ------------------------------------------------------------------------