1 //==========================================================================
5 // Ethernet transciever (PHY) support
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2003, 2004 Gary Thomas
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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30 // License. However the source code for this file must still be made available
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
47 // Description: API support for ethernet PHY
50 //####DESCRIPTIONEND####
52 //==========================================================================
54 #include <pkgconf/system.h>
55 #include <pkgconf/io_eth_drivers.h>
56 #include <pkgconf/devs_eth_phy.h>
57 #include <cyg/infra/cyg_type.h>
59 #include <cyg/hal/hal_arch.h>
60 #include <cyg/hal/drv_api.h>
61 #include <cyg/hal/hal_if.h>
62 #include <cyg/hal/hal_tables.h>
64 #include <cyg/io/eth_phy.h>
65 #include <cyg/io/eth_phy_dev.h>
67 // Define table boundaries
68 CYG_HAL_TABLE_BEGIN( __ETH_PHY_TAB__, _eth_phy_devs );
69 CYG_HAL_TABLE_END( __ETH_PHY_TAB_END__, _eth_phy_devs );
70 extern struct _eth_phy_dev_entry __ETH_PHY_TAB__[], __ETH_PHY_TAB_END__;
73 #define MII_Start 0x40000000
74 #define MII_Read 0x20000000
75 #define MII_Write 0x10000000
76 #define MII_Cmd 0x30000000
77 #define MII_Phy(phy) (phy << 23)
78 #define MII_Reg(reg) (reg << 18)
79 #define MII_TA 0x00020000
82 // PHY unit access (via MII channel, using bit-level operations)
86 phy_cmd(eth_phy_access_t *f, cyg_uint32 cmd)
90 bool is_read = (cmd & MII_Cmd) == MII_Read;
92 // Set both bits as output
93 f->ops.bit_level_ops.set_dir(1);
96 for (i = 0; i < 32; i++) {
97 f->ops.bit_level_ops.set_clock(0);
98 f->ops.bit_level_ops.set_data(1);
99 CYGACC_CALL_IF_DELAY_US(1);
100 f->ops.bit_level_ops.set_clock(1);
101 CYGACC_CALL_IF_DELAY_US(1);
105 for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) {
106 f->ops.bit_level_ops.set_clock(0);
107 f->ops.bit_level_ops.set_data((cmd >> off) & 0x00000001);
108 CYGACC_CALL_IF_DELAY_US(1);
109 f->ops.bit_level_ops.set_clock(1);
110 CYGACC_CALL_IF_DELAY_US(1);
115 // If read, fetch data register
119 f->ops.bit_level_ops.set_clock(0);
120 f->ops.bit_level_ops.set_dir(0);
121 CYGACC_CALL_IF_DELAY_US(1);
122 f->ops.bit_level_ops.set_clock(1);
123 CYGACC_CALL_IF_DELAY_US(1);
124 f->ops.bit_level_ops.set_clock(0);
125 CYGACC_CALL_IF_DELAY_US(1);
127 for (i = 0, off = 15; i < 16; i++, off--) {
128 f->ops.bit_level_ops.set_clock(1);
130 retval |= f->ops.bit_level_ops.get_data();
131 CYGACC_CALL_IF_DELAY_US(1);
132 f->ops.bit_level_ops.set_clock(0);
133 CYGACC_CALL_IF_DELAY_US(1);
137 // Set both bits as output
138 f->ops.bit_level_ops.set_dir(1);
141 for (i = 0; i < 32; i++) {
142 f->ops.bit_level_ops.set_clock(0);
143 f->ops.bit_level_ops.set_data(1);
144 CYGACC_CALL_IF_DELAY_US(1);
145 f->ops.bit_level_ops.set_clock(1);
146 CYGACC_CALL_IF_DELAY_US(1);
153 _eth_phy_init(eth_phy_access_t *f)
156 unsigned short state;
157 unsigned long id = 0;
158 struct _eth_phy_dev_entry *dev;
160 if (f->init_done) return true;
162 // Scan to determine PHY address
164 for (addr = 0; addr < 0x20; addr++) {
165 if (_eth_phy_read(f, PHY_ID1, addr, &state)) {
167 if (_eth_phy_read(f, PHY_ID2, addr, &state)) {
170 for (dev = __ETH_PHY_TAB__; dev != &__ETH_PHY_TAB_END__; dev++) {
172 eth_phy_printf("PHY: %s\n", dev->name);
181 // Can't handle this PHY
182 eth_phy_printf("Unsupported PHY device - id: %lx\n", id);
184 f->init_done = false;
189 _eth_phy_reset(eth_phy_access_t *f)
192 eth_phy_printf("PHY reset without init on PHY: %p\n", f);
199 _eth_phy_write(eth_phy_access_t *f, int reg, int addr, unsigned short data)
202 eth_phy_printf("PHY write without init on PHY: %p\n", f);
205 if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
206 phy_cmd(f, MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data);
208 f->ops.reg_level_ops.put_reg(reg, addr, data);
213 _eth_phy_read(eth_phy_access_t *f, int reg, int addr, unsigned short *val)
218 eth_phy_printf("PHY read without init on PHY: %p\n", f);
221 if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
222 ret = phy_cmd(f, MII_Start | MII_Read | MII_Phy(addr) | MII_Reg(reg) | MII_TA);
226 return f->ops.reg_level_ops.get_reg(reg, addr, val);
231 _eth_phy_cfg(eth_phy_access_t *f, int mode)
233 int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
235 unsigned short reset_mode, phy_state;
239 eth_phy_printf("PHY config without init on PHY: %p\n", f);
243 // Reset PHY (transceiver)
247 _eth_phy_write(f, PHY_BMCR, f->phy_addr, PHY_BMCR_RESET);
248 for (i = 0; i < 5*100; i++) {
249 phy_ok = _eth_phy_read(f, PHY_BMCR, f->phy_addr, &phy_state);
250 eth_phy_printf("PHY: %x\n", phy_state);
251 if (phy_ok && !(phy_state & PHY_BMCR_RESET)) break;
252 CYGACC_CALL_IF_DELAY_US(10000); // 10ms
254 if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
255 eth_phy_printf("PPC405: Can't get PHY unit to soft reset: %x\n", phy_state);
259 reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG;
260 _eth_phy_write(f, PHY_BMCR, f->phy_addr, reset_mode);
261 while (phy_timeout-- >= 0) {
262 phy_ok = _eth_phy_read(f, PHY_BMSR, f->phy_addr, &phy_state);
263 if (phy_ok && (phy_state & PHY_BMSR_AUTO_NEG)) {
266 CYGACC_CALL_IF_DELAY_US(10000); // 10ms
269 if (phy_timeout <= 0) {
270 eth_phy_printf("** PPC405 Warning: PHY LINK UP failed: %04x\n", phy_state);
274 return _eth_phy_state(f);
278 _eth_phy_state(eth_phy_access_t *f)
283 eth_phy_printf("PHY state without init on PHY: %p\n", f);
286 if (f->dev->stat(f, &state)) {