1 #ifndef CYGONCE_DEVS_ETH_SMSC_LAN91CXX_LAN91CXX_H
2 #define CYGONCE_DEVS_ETH_SMSC_LAN91CXX_LAN91CXX_H
3 //==========================================================================
7 // SMCS LAN91C110 (LAN91CXX compatible) Ethernet chip
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2003 Nick Garnett
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //####BSDCOPYRIGHTBEGIN####
45 // -------------------------------------------
47 // Portions of this software may have been derived from OpenBSD or other sources,
48 // and are covered by the appropriate copyright disclaimers included herein.
50 // -------------------------------------------
52 //####BSDCOPYRIGHTEND####
53 //==========================================================================
54 //#####DESCRIPTIONBEGIN####
57 // Contributors: jskov, hmt, jco, nickg
59 // Purpose: Hardware description of LAN9000 series, LAN91C96/110.
62 //####DESCRIPTIONEND####
64 //==========================================================================
66 #include <cyg/hal/hal_io.h>
67 #include <cyg/hal/hal_endian.h>
69 #define LAN91CXX_TCR 0x00
70 #define LAN91CXX_EPH_STATUS 0x01
71 #define LAN91CXX_RCR 0x02
72 #define LAN91CXX_COUNTER 0x03
73 #define LAN91CXX_MIR 0x04
74 #define LAN91CXX_MCR 0x05 // Other than 91C111
75 #define LAN91CXX_RPCR 0x05 // 91C111 only
76 #define LAN91CXX_RESERVED_0 0x06
77 #define LAN91CXX_BS 0x07
78 #define LAN91CXX_CONFIG 0x08
79 #define LAN91CXX_BASE_REG 0x09
80 #define LAN91CXX_IA01 0x0a
81 #define LAN91CXX_IA23 0x0b
82 #define LAN91CXX_IA45 0x0c
83 #define LAN91CXX_GENERAL 0x0d // 91C96 - was "RESERVED_1" for others
84 #define LAN91CXX_CONTROL 0x0e
85 #define LAN91CXX_BS2 0x0f
86 #define LAN91CXX_MMU_COMMAND 0x10
87 #define LAN91CXX_PNR 0x11
88 #define LAN91CXX_FIFO_PORTS 0x12
89 #define LAN91CXX_POINTER 0x13
90 #define LAN91CXX_DATA_HIGH 0x14
91 #define LAN91CXX_DATA 0x15
92 #define LAN91CXX_INTERRUPT 0x16
93 #define LAN91CXX_BS3 0x17
94 #define LAN91CXX_MT01 0x18
95 #define LAN91CXX_MT23 0x19
96 #define LAN91CXX_MT45 0x1a
97 #define LAN91CXX_MT67 0x1b
98 #define LAN91CXX_MGMT 0x1c
99 #define LAN91CXX_REVISION 0x1d
100 #define LAN91CXX_ERCV 0x1e
101 #define LAN91CXX_BS4 0x1f
103 #define LAN91CXX_RCR_SOFT_RST 0x8000 // soft reset
104 #define LAN91CXX_RCR_FILT_CAR 0x4000 // filter carrier
105 #define LAN91CXX_RCR_ABORT_ENB 0x2000 // abort on collision
106 #define LAN91CXX_RCR_STRIP_CRC 0x0200 // strip CRC
107 #define LAN91CXX_RCR_RXEN 0x0100 // enable RX
108 #define LAN91CXX_RCR_ALMUL 0x0004 // receive all muticasts
109 #define LAN91CXX_RCR_PRMS 0x0002 // promiscuous
110 #define LAN91CXX_RCR_RX_ABORT 0x0001 // set when abort due to long frame
112 #define LAN91CXX_TCR_SWFDUP 0x8000 // Switched Full Duplex mode
113 #define LAN91CXX_TCR_ETEN_TYPE 0x4000 // ETEN type (91C96) 0 <=> like a 91C94
114 #define LAN91CXX_TCR_EPH_LOOP 0x2000 // loopback mode
115 #define LAN91CXX_TCR_STP_SQET 0x1000 // Stop transmission on SQET error
116 #define LAN91CXX_TCR_FDUPLX 0x0800 // full duplex
117 #define LAN91CXX_TCR_MON_CSN 0x0400 // monitor carrier during tx (91C96)
118 #define LAN91CXX_TCR_NOCRC 0x0100 // does not append CRC to frames
119 #define LAN91CXX_TCR_PAD_EN 0x0080 // pads frames with 00 to min length
120 #define LAN91CXX_TCR_FORCOL 0x0004 // force collision
121 #define LAN91CXX_TCR_LLOOP 0x0002 // local loopback (91C96)
122 #define LAN91CXX_TCR_TXENA 0x0001 // enable
124 #define LAN91CXX_POINTER_RCV 0x8000
125 #define LAN91CXX_POINTER_AUTO_INCR 0x4000
126 #define LAN91CXX_POINTER_READ 0x2000
127 #define LAN91CXX_POINTER_ETEN 0x1000
128 #define LAN91CXX_POINTER_NOT_EMPTY 0x0800
131 #define LAN91CXX_INTERRUPT_TX_IDLE_M 0x8000 // (91C96)
132 #define LAN91CXX_INTERRUPT_ERCV_INT_M 0x4000
133 #define LAN91CXX_INTERRUPT_EPH_INT_M 0x2000
134 #define LAN91CXX_INTERRUPT_RX_OVRN_INT_M 0x1000
135 #define LAN91CXX_INTERRUPT_ALLOC_INT_M 0x0800
136 #define LAN91CXX_INTERRUPT_TX_EMPTY_INT_M 0x0400
137 #define LAN91CXX_INTERRUPT_TX_INT_M 0x0200
138 #define LAN91CXX_INTERRUPT_RCV_INT_M 0x0100
139 #define LAN91CXX_INTERRUPT_TX_IDLE 0x0080 // (91C96)
140 #define LAN91CXX_INTERRUPT_ERCV_INT 0x0040 // also ack
141 #define LAN91CXX_INTERRUPT_EPH_INT 0x0020
142 #define LAN91CXX_INTERRUPT_RX_OVRN_INT 0x0010 // also ack
143 #define LAN91CXX_INTERRUPT_ALLOC_INT 0x0008
144 #define LAN91CXX_INTERRUPT_TX_EMPTY_INT 0x0004 // also ack
145 #define LAN91CXX_INTERRUPT_TX_INT 0x0002 // also ack
146 #define LAN91CXX_INTERRUPT_RCV_INT 0x0001
148 #if 1 // Whichever we choose, the behaviour is the same.
149 #define LAN91CXX_INTERRUPT_TX_SET 0x0002 // TX
150 #define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0000 // -none-
151 #define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 // TX alone
152 #define LAN91CXX_INTERRUPT_TX_SET_M 0x0200 // TX alone
154 #define LAN91CXX_INTERRUPT_TX_SET 0x0006 // TX_EMPTY + TX
155 #define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0004 // TX_EMPTY and not plain TX
156 #define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 // TX alone
157 #define LAN91CXX_INTERRUPT_TX_SET_M 0x0600 // TX_EMPTY + TX
160 #define LAN91CXX_CONTROL_RCV_BAD 0x4000
161 #define LAN91CXX_CONTROL_AUTO_RELEASE 0x0800
162 #define LAN91CXX_CONTROL_LE_ENABLE 0x0080
163 #define LAN91CXX_CONTROL_CR_ENABLE 0x0040
164 #define LAN91CXX_CONTROL_TE_ENABLE 0x0020
166 // These are for setting the MAC address in the 91C96 serial EEPROM
167 #define LAN91CXX_CONTROL_EEPROM_SELECT 0x0004
168 #define LAN91CXX_CONTROL_RELOAD 0x0002
169 #define LAN91CXX_CONTROL_STORE 0x0001
170 #define LAN91CXX_CONTROL_EEPROM_BUSY 0x0003
171 #define LAN91CXX_ESA_EEPROM_OFFSET 0x0020
173 #define LAN91CXX_STATUS_TX_UNRN 0x8000
174 #define LAN91CXX_STATUS_LINK_OK 0x4000
175 #define LAN91CXX_STATUS_CTR_ROL 0x1000
176 #define LAN91CXX_STATUS_EXC_DEF 0x0800
177 #define LAN91CXX_STATUS_LOST_CARR 0x0400
178 #define LAN91CXX_STATUS_LATCOL 0x0200
179 #define LAN91CXX_STATUS_WAKEUP 0x0100
180 #define LAN91CXX_STATUS_TX_DEFR 0x0080
181 #define LAN91CXX_STATUS_LTX_BRD 0x0040
182 #define LAN91CXX_STATUS_SQET 0x0020
183 #define LAN91CXX_STATUS_16COL 0x0010
184 #define LAN91CXX_STATUS_LTX_MULT 0x0008
185 #define LAN91CXX_STATUS_MUL_COL 0x0004
186 #define LAN91CXX_STATUS_SNGL_COL 0x0002
187 #define LAN91CXX_STATUS_TX_SUC 0x0001
189 #define LAN91CXX_MMU_noop 0x0000
190 #define LAN91CXX_MMU_alloc_for_tx 0x0020
191 #define LAN91CXX_MMU_reset_mmu 0x0040
192 #define LAN91CXX_MMU_rem_rx_frame 0x0060
193 #define LAN91CXX_MMU_rem_tx_frame 0x0070 // (91C96) only when TX stopped
194 #define LAN91CXX_MMU_remrel_rx_frame 0x0080
195 #define LAN91CXX_MMU_rel_packet 0x00a0
196 #define LAN91CXX_MMU_enq_packet 0x00c0
197 #define LAN91CXX_MMU_reset_tx_fifo 0x00e0
199 #define LAN91CXX_CONTROLBYTE_CRC 0x1000
200 #define LAN91CXX_CONTROLBYTE_ODD 0x2000
201 #define LAN91CXX_CONTROLBYTE_RX 0x4000
203 #define LAN91CXX_RX_STATUS_ALIGNERR 0x8000
204 #define LAN91CXX_RX_STATUS_BCAST 0x4000
205 #define LAN91CXX_RX_STATUS_BADCRC 0x2000
206 #define LAN91CXX_RX_STATUS_ODDFRM 0x1000
207 #define LAN91CXX_RX_STATUS_TOOLONG 0x0800
208 #define LAN91CXX_RX_STATUS_TOOSHORT 0x0400
209 #define LAN91CXX_RX_STATUS_HASHVALMASK 0x007e // MASK
210 #define LAN91CXX_RX_STATUS_MCAST 0x0001
211 #define LAN91CXX_RX_STATUS_BAD \
212 (LAN91CXX_RX_STATUS_ALIGNERR | \
213 LAN91CXX_RX_STATUS_BADCRC | \
214 LAN91CXX_RX_STATUS_TOOLONG | \
215 LAN91CXX_RX_STATUS_TOOSHORT)
217 // Attribute memory registers in PCMCIA mode
218 #define LAN91CXX_ECOR 0x8000
219 #define LAN91CXX_ECOR_RESET (1<<7)
220 #define LAN91CXX_ECOR_LEVIRQ (1<<6)
221 #define LAN91CXX_ECOR_ATTWR (1<<2)
222 #define LAN91CXX_ECOR_ENABLE (1<<0)
224 #define LAN91CXX_ECSR 0x8002
225 #define LAN91CXX_ECSR_IOIS8 (1<<5)
226 #define LAN91CXX_ECSR_PWRDWN (1<<2)
227 #define LAN91CXX_ECSR_INTR (1<<1)
229 // These are for manipulating the MII interface
230 #define LAN91CXX_MGMT_MDO 0x0001
231 #define LAN91CXX_MGMT_MDI 0x0002
232 #define LAN91CXX_MGMT_MCLK 0x0004
233 #define LAN91CXX_MGMT_MDOE 0x0008
235 // Internal PHY registers (91c111)
236 #define LAN91CXX_PHY_CTRL 0
237 #define LAN91CXX_PHY_STAT 1
238 #define LAN91CXX_PHY_ID1 2
239 #define LAN91CXX_PHY_ID2 3
240 #define LAN91CXX_PHY_AUTO_AD 4
241 #define LAN91CXX_PHY_AUTO_CAP 5
242 #define LAN91CXX_PHY_CONFIG1 16
243 #define LAN91CXX_PHY_CONFIG2 17
244 #define LAN91CXX_PHY_STATUS_OUT 18
245 #define LAN91CXX_PHY_MASK 19
248 #define LAN91CXX_PHY_CTRL_COLTST (1 << 7)
249 #define LAN91CXX_PHY_CTRL_DPLX (1 << 8)
250 #define LAN91CXX_PHY_CTRL_ANEG_RST (1 << 9)
251 #define LAN91CXX_PHY_CTRL_MII_DIS (1 << 10)
252 #define LAN91CXX_PHY_CTRL_PDN (1 << 11)
253 #define LAN91CXX_PHY_CTRL_ANEG_EN (1 << 12)
254 #define LAN91CXX_PHY_CTRL_SPEED (1 << 13)
255 #define LAN91CXX_PHY_CTRL_LPBK (1 << 14)
256 #define LAN91CXX_PHY_CTRL_RST (1 << 15)
258 #define LAN91CXX_RPCR_LEDA_LINK (0 << 2)
259 #define LAN91CXX_RPCR_LEDA_TXRX (4 << 2)
260 #define LAN91CXX_RPCR_LEDA_RX (6 << 2)
261 #define LAN91CXX_RPCR_LEDA_TX (7 << 2)
262 #define LAN91CXX_RPCR_LEDB_LINK (0 << 5)
263 #define LAN91CXX_RPCR_LEDB_TXRX (4 << 5)
264 #define LAN91CXX_RPCR_LEDB_RX (6 << 5)
265 #define LAN91CXX_RPCR_LEDB_TX (7 << 5)
266 #define LAN91CXX_RPCR_ANEG (1 << 11)
267 #define LAN91CXX_RPCR_DPLX (1 << 12)
268 #define LAN91CXX_RPCR_SPEED (1 << 13)
271 // ------------------------------------------------------------------------
273 #ifdef KEEP_STATISTICS
274 struct smsc_lan91cxx_stats {
275 unsigned int tx_good ;
276 unsigned int tx_max_collisions ;
277 unsigned int tx_late_collisions ;
278 unsigned int tx_underrun ;
279 unsigned int tx_carrier_loss ;
280 unsigned int tx_deferred ;
281 unsigned int tx_sqetesterrors ;
282 unsigned int tx_single_collisions;
283 unsigned int tx_mult_collisions ;
284 unsigned int tx_total_collisions ;
285 unsigned int rx_good ;
286 unsigned int rx_crc_errors ;
287 unsigned int rx_align_errors ;
288 unsigned int rx_resource_errors ;
289 unsigned int rx_overrun_errors ;
290 unsigned int rx_collisions ;
291 unsigned int rx_short_frames ;
292 unsigned int rx_too_long_frames ;
293 unsigned int rx_symbol_errors ;
294 unsigned int interrupts ;
295 unsigned int rx_count ;
296 unsigned int rx_deliver ;
297 unsigned int rx_resource ;
298 unsigned int rx_restart ;
299 unsigned int tx_count ;
300 unsigned int tx_complete ;
301 unsigned int tx_dropped ;
305 struct lan91cxx_priv_data;
306 typedef cyg_bool (*provide_esa_t)(struct lan91cxx_priv_data* cpd);
308 typedef struct lan91cxx_priv_data {
309 int txbusy; // A packet has been sent
310 unsigned long txkey; // Used to ack when packet sent
311 unsigned short* base; // Base I/O address of controller
312 // (as it comes out of reset)
313 #if CYGINT_DEVS_ETH_SMSC_LAN91CXX_PCMCIA_MODE
314 unsigned char* attbase; // Base attribute address of controller
315 // only used in PCMCIA mode
317 int interrupt; // Interrupt vector used by controller
318 unsigned char enaddr[6]; // Controller ESA
319 // Function to configure the ESA - may fetch ESA from EPROM or
320 // RedBoot config option. Use of the 'config_enaddr()' function
321 // is depreciated in favor of the 'provide_esa()' function and
322 // 'hardwired_esa' boolean
323 void (*config_enaddr)(struct lan91cxx_priv_data* cpd);
324 // New function to fetch the ESA from flash via RedBoot
325 // (see devs_eth_innovator.inl)
326 provide_esa_t provide_esa;
331 int addrsh; // Address bits to shift
332 int c111_reva; // true if this is a revA LAN91C111
333 #ifdef KEEP_STATISTICS
334 struct smsc_lan91cxx_stats stats;
336 } lan91cxx_priv_data;
338 // ------------------------------------------------------------------------
340 #include CYGDAT_DEVS_ETH_SMSC_LAN91CXX_INL
342 #ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
343 typedef cyg_uint32 rxd_t;
345 typedef cyg_uint16 rxd_t;
348 #ifndef SMSC_PLATFORM_DEFINED_GET_REG
349 static __inline__ unsigned short
350 get_reg(struct eth_drv_sc *sc, int regno)
352 struct lan91cxx_priv_data *cpd =
353 (struct lan91cxx_priv_data *)sc->driver_private;
356 HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS << cpd->addrsh), CYG_CPU_TO_LE16(regno>>3));
357 HAL_READ_UINT16(cpd->base+((regno&0x7) << cpd->addrsh), val);
358 val = CYG_LE16_TO_CPU(val);
361 diag_printf("read reg %d val 0x%04x\n", regno, val);
365 #endif // SMSC_PLATFORM_DEFINED_GET_REG
367 #ifndef SMSC_PLATFORM_DEFINED_PUT_REG
368 static __inline__ void
369 put_reg(struct eth_drv_sc *sc, int regno, unsigned short val)
371 struct lan91cxx_priv_data *cpd =
372 (struct lan91cxx_priv_data *)sc->driver_private;
374 HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS << cpd->addrsh), CYG_CPU_TO_LE16(regno>>3));
375 HAL_WRITE_UINT16(cpd->base+((regno&0x7) << cpd->addrsh), CYG_CPU_TO_LE16(val));
378 diag_printf("write reg %d val 0x%04x\n", regno, val);
381 #endif // SMSC_PLATFORM_DEFINED_PUT_REG
383 #ifndef SMSC_PLATFORM_DEFINED_PUT_DATA
384 // ------------------------------------------------------------------------
385 // Assumes bank2 has been selected
386 static __inline__ void
387 put_data(struct eth_drv_sc *sc, unsigned short val)
389 struct lan91cxx_priv_data *cpd =
390 (struct lan91cxx_priv_data *)sc->driver_private;
392 HAL_WRITE_UINT16(cpd->base+((LAN91CXX_DATA & 0x7) << cpd->addrsh), val);
395 diag_printf("write data 0x%04x\n", val);
398 #endif // SMSC_PLATFORM_DEFINED_PUT_DATA
400 #ifndef SMSC_PLATFORM_DEFINED_GET_DATA
401 // Assumes bank2 has been selected
402 static __inline__ rxd_t
403 get_data(struct eth_drv_sc *sc)
406 struct lan91cxx_priv_data *cpd =
407 (struct lan91cxx_priv_data *)sc->driver_private;
409 #ifdef CYGSEM_DEVS_ETH_SMSC_LAN91CXX_USE_32BIT
410 HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7) << cpd->addrsh), val);
412 HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7) << cpd->addrsh), val);
416 diag_printf("read data 0x%x\n", val);
420 #endif // SMSC_PLATFORM_DEFINED_GET_DATA
422 // ------------------------------------------------------------------------
423 // Read the bank register (this one is bank-independent)
424 #ifndef SMSC_PLATFORM_DEFINED_GET_BANKSEL
425 static __inline__ unsigned short
426 get_banksel(struct eth_drv_sc *sc)
428 struct lan91cxx_priv_data *cpd =
429 (struct lan91cxx_priv_data *)sc->driver_private;
432 HAL_READ_UINT16(cpd->base+(LAN91CXX_BS << cpd->addrsh), val);
433 val = CYG_LE16_TO_CPU(val);
435 diag_printf("read bank val 0x%04x\n", val);
442 // ------------------------------------------------------------------------
443 // Write on PCMCIA attribute memory
444 #if CYGINT_DEVS_ETH_SMSC_LAN91CXX_PCMCIA_MODE
445 static __inline__ void
446 put_att(struct eth_drv_sc *sc, int offs, unsigned char val)
448 struct lan91cxx_priv_data *cpd =
449 (struct lan91cxx_priv_data *)sc->driver_private;
451 HAL_WRITE_UINT8(cpd->attbase + (offs << cpd->addrsh), CYG_CPU_TO_LE16(val));
454 diag_printf("write attr %d val 0x%02x\n", offs, val);
458 // Read from PCMCIA attribute memory
459 static __inline__ unsigned char
460 get_att(struct eth_drv_sc *sc, int offs)
462 struct lan91cxx_priv_data *cpd =
463 (struct lan91cxx_priv_data *)sc->driver_private;
466 HAL_READ_UINT8(cpd->attbase + (offs << cpd->addrsh), val);
467 val = CYG_LE16_TO_CPU(val);
469 diag_printf("read attr %d val 0x%02x\n", offs, val);
473 #endif // #if CYGINT_DEVS_ETH_SMSC_LAN91CXX_PCMCIA_MODE
475 // ------------------------------------------------------------------------
476 #endif // CYGONCE_DEVS_ETH_SMSC_LAN91CXX_LAN91CXX_H
477 // EOF smsc_lan91cxx.h