4 #include <cyg/infra/cyg_type.h>
10 cyg_uint32 sdhc_status;
11 cyg_uint32 sdhc_clk_rate;
12 cyg_uint32 sdhc_dat_cont;
13 cyg_uint32 sdhc_response_to;
14 cyg_uint32 sdhc_read_to;
15 cyg_uint32 sdhc_blk_len;
17 cyg_uint32 sdhc_rev_no;
18 cyg_uint32 sdhc_int_cntr;
21 cyg_uint32 sdhc_reserved;
22 cyg_uint32 sdhc_res_fifo;
23 cyg_uint32 sdhc_buffer_access;
26 /* Defines for card types */
38 typedef struct _card_specific_data
46 /* Defines for card types */
47 typedef struct _card_id
62 typedef enum frequency_mode
68 typedef struct command
71 cyg_uint32 data_control;
83 #define CARD_STATE 0x1E00
84 #define CARD_STATE_SHIFT 9
86 /*Defines of CSD data*/
87 #define CSD_STRUCT_MSK 0x00C00000
88 #define CSD_STRUCT_SHIFT 22
91 /* Define the states of the card*/
107 typedef struct _response
116 typedef enum card_mode
132 RESPONSE_48_CRC = 0x1,
134 RESPONSE_48_WITHOUT_CRC = 0x3
137 enum status_bus_width
144 #define SDHC_INT 0xc015
146 #define OCR_VALUE 0x80ff8000
147 #define OCR_VALUE_MASK 0x00ff8000
148 #define CARD_BUSY 0x80000000
149 #define SD_R1_APP_CMD_MSK 0x20
151 #define BLOCK_LEN 0x200
155 /* Status regsiter Masks */
156 #define SDHC_STATUS_END_CMD_RESP_MSK 0x2000
157 #define SDHC_STATUS_WRITE_OP_DONE_MSK 0x1000
158 #define SDHC_STATUS_READ_OP_DONE_MSK 0x800
159 #define SDHC_STATUS_WR_CRC_ERR_CODE_MSK 0x600
160 #define SDHC_STATUS_CARD_BUS_CLK_RUN_MSK 0x100
161 #define SDHC_STATUS_RESP_CRC_ERR_MSK 0x20
162 #define SDHC_STATUS_BUF_READ_RDY_MSK 0x80
163 #define SDHC_STATUS_BUF_WRITE_RDY_MSK 0x40
164 #define SDHC_STATUS_READ_CRC_ERR_MSK 0x8
165 #define SDHC_STATUS_WRITE_CRC_ERR_MSK 0x4
166 #define SDHC_STATUS_TIME_OUT_RESP_MSK 0x2
167 #define SDHC_STATUS_TIME_OUT_READ 0x1
169 #define SDHC_STATUS_CLEAR ((cyg_uint32)(0xC0007E2F))
173 /* Command (data control) masks */
174 #define SDHC_CMD_FROMAT_OF_RESP 0x00000007
175 #define SDHC_CMD_DATA_ENABLE 0x00000008
176 #define SDHC_CMD_WRITE_READ 0x00000010
177 #define SDHC_CMD_INIT 0x00000080
178 #define SDHC_CMD_BUS_WIDTH 0x00000300
179 #define SDHC_CMD_START_READWAIT 0x00000400
180 #define SDHC_CMD_STOP_READWAIT 0x00000800
181 #define SDHC_CMD_DATA_CTRL_CMD_RESP_LONG_OFF 0x00001000
183 /* Command (data control) shift */
184 #define SDHC_CMD_FROMAT_OF_RESP_SHIFT 0x0
185 #define SDHC_CMD_DATA_ENABLE_SHIFT 0x3
186 #define SDHC_CMD_BUS_WIDTH_SHIFT 0x8
187 #define SDHC_CMD_WRITE_READ_SHIFT 0x4
188 #define SDHC_CMD_INIT_SHIFT 0x7
190 //#define SDHC_CMD_FROMAT_OF_RESP_NONE 0x0
191 //#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_48 0x1
192 //#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_136 0x2
193 //#define SDHC_CMD_DATA_CTRL_FROMAT_OF_RESP_48_N0_CRC 0x3
194 //#define SDHC_CMD_DATA_CTRL_BUS_WIDTH_1_BIT 0x0
195 //#define SDHC_CMD_DATA_CTRL_BUS_WIDTH_4_BIT 0x2
197 /* Define each command */
228 extern cyg_uint32 CCC; /* Card Command Class */
230 extern cyg_uint32 mxcmci_init (cyg_uint32 bus_width, cyg_uint32 base_address);
231 extern cyg_uint32 mmc_data_write (cyg_uint32 *src_ptr,cyg_uint32 length,cyg_uint32 offset);
232 extern cyg_uint32 mmc_data_erase (cyg_uint32 offset, cyg_uint32 size);
233 extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32);
234 extern cyg_uint32 card_flash_query(void* data);
235 extern cyg_uint32 card_get_capacity_size (void);
243 perm_write_protect:1,
252 cyg_uint32 wp_grp_size:7,
261 cyg_uint32 c_size_up:10,
265 write_blk_misalign:1,
269 cyg_uint32 tran_speed:8,
274 } __attribute__ ((packed));
283 perm_write_protect:1,
303 write_blk_misalign:1,
307 cyg_uint32 tran_speed:8,
312 } __attribute__ ((packed));