1 #ifndef _MXCMCI_HOST_H_
2 #define _MXCMCI_HOST_H_
4 // ==========================================================================
6 // Module Name: mxcmci_host.h
8 // General Description: Limited Bootloader eSDHC Driver.
11 // ==========================================================================
12 //####ECOSGPLCOPYRIGHTBEGIN####
13 // -------------------------------------------
14 // This file is part of eCos, the Embedded Configurable Operating System.
15 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
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38 // this file might be covered by the GNU General Public License.
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41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 //==========================================================================
45 //#####DESCRIPTIONBEGIN####
47 // Author(s): Lewis Liu <weizhi.liu@freescale.com>
48 // Contributors: Lewis Liu <weizhi.liu@freescale.com>
49 // Date: 2008-05-13 Initial version
54 //####DESCRIPTIONEND####
55 //====================================================================================================
57 #include <cyg/infra/cyg_type.h>
60 #define ESDHC_SOFTWARE_RESET 0x01000000 /* RSTA bit of ESDHC system control register*/
61 #define ESDHC_CMD_INHIBIT 0x00000003 /* Command inhibit bits*/
62 #define ESDHC_SOFTWARE_INIT 0x08000000 /* INITA bit of ESDHC system control register */
63 #define ESDHC_LITTLE_ENDIAN_MODE 0x00000020 /* Little Endian mode */
64 #define ESDHC_HW_BIG_ENDIAN_MODE 0x00000010 /* Half Word Big Endian mode */
65 #define ESDHC_BIG_ENDIAN_MODE 0x00000000 /* Big Endian mode */
66 #define ESDHC_ONE_BIT_SUPPORT 0x00000000 /* 1 Bit Mode support */
67 #define ESDHC_FOUR_BIT_SUPPORT 0x00000002 /* 4 Bit Mode support */
68 #define ESDHC_EIGHT_BIT_SUPPORT 0x00000004 /* 8 Bit Mode support */
69 #define ESDHC_CLOCK_ENABLE 0x00000007 /* Clock Enable */
70 #define ESDHC_ENABLE 0x00000008 /* Enable SD */
72 #define ESDHC_FREQ_MASK 0xffff0007
73 #define ESDHC_IDENT_FREQ 0x0000800e /* SDCLKFS 0x08 ; DVS 0xe */
74 #define ESDHC_OPERT_FREQ 0x00000200 /* SDCLKFS 0x02 ; DVS 0x0 */
75 #define ESDHC_INTERRUPT_ENABLE 0x007f0123 /* Enable Interrupts */
76 #define ESDHC_CONFIG_BLOCK 0x00010200 /* 512 byte block size*/
77 #define ESDHC_CLEAR_INTERRUPT 0xffffffff
79 #define ESDHC_CONFIG_BLOCK_512 0x00000200 /* 512 byte block size*/
80 #define ESDHC_CONFIG_BLOCK_64 0x00000040 /* 64 byte block size*/
81 #define ESDHC_BLOCK_SHIFT 16
83 #define ESDHC_CLEAR_INTERRUPT 0xffffffff
84 #define ESDHC_OPER_TIMEOUT 96 /* 3 msec time out */
85 #define ESDHC_READ_TIMEOUT 3264 /* 102 msec read time out */
86 #define ESDHC_ACMD41_TIMEOUT 48000 /* 1.5 sec =1500 msec delay for ACMD41 cmd */
88 #define ESDHCI_SPACE_AVAILABLE 0x00000400
89 #define ESDHCI_DATA_AVAILABLE 0x00000800
91 /*==================================================================================================
93 ==================================================================================================*/
94 #define DATA_TRANSFER_SHIFT 4
95 #define RESPONSE_FORMAT_SHIFT 16
96 #define DATA_PRESENT_SHIFT 21
97 #define CRC_CHECK_SHIFT 19
98 #define CMD_INDEX_CHECK_SHIFT 20
99 #define CMD_INDEX_SHIFT 24
100 #define BLOCK_COUNT_ENABLE_SHIFT 1
101 #define MULTI_SINGLE_BLOCK_SELECT_SHIFT 5
103 #define SWITCH_BLK_LEN 64
104 #define FIFO_SIZE 128
105 #define WRITE_READ_WATER_MARK_LEVEL 0x00200020
110 /*==================================================================================================
112 ==================================================================================================*/
113 #define ESDHC_STATUS_END_CMD_RESP_MSK 0x1
114 #define ESDHC_STATUS_END_CMD_RESP_TIME_MSK 0x00010001
115 #define ESDHC_STATUS_TIME_OUT_RESP_MSK 0x10000
116 #define ESDHC_STATUS_RESP_CRC_ERR_MSK 0x20000
117 #define ESDHC_STATUS_RESP_INDEX_ERR_MSK 0x80000
118 #define ESDHC_STATUS_BUF_READ_RDY_MSK 0x20
119 #define ESDHC_STATUS_BUF_WRITE_RDY_MSK 0x10
120 #define ESDHC_STATUS_TRANSFER_COMPLETE_MSK 0x2
121 #define ESDHC_STATUS_TIME_OUT_READ 0x100000
122 #define ESDHC_STATUS_READ_CRC_ERR_MSK 0x200000
124 #define ESDHC_RESET_CMD_MSK 0x02000000
125 #define ESDHC_RESET_DAT_MSK 0x04000000
126 #define ESDHC_RESET_ALL_MSK 0x01000000
139 RESPONSE_48_CHECK_BUSY
145 DATA_PRESENT_NONE = 0,
147 }data_present_select;
153 }crc_check_enable,cmdindex_check_enable,block_count_enable;
159 }multi_single_block_select;
165 xfer_type_t data_transfer;
166 response_format_t response_format;
167 data_present_select data_present;
168 crc_check_enable crc_check;
169 cmdindex_check_enable cmdindex_check;
170 block_count_enable block_count_enable_check;
171 multi_single_block_select multi_single_block;
176 response_format_t format;
186 HALF_WORD_BIG_ENDIAN,
192 OPERATING_FREQ = 20000, /* in kHz */
193 IDENTIFICATION_FREQ = 400 /* in kHz */
197 enum esdhc_data_status
203 enum esdhc_int_cntr_val
205 ESDHC_INT_CNTR_END_CD_RESP = 0x4,
206 ESDHC_INT_CNTR_BUF_WR_RDY = 0x8
209 enum esdhc_reset_status
211 ESDHC_WRONG_RESET = 0,
212 ESDHC_CORRECT_RESET = 1
217 volatile cyg_uint32 dma_system_address;
218 volatile cyg_uint32 block_attributes;
219 volatile cyg_uint32 command_argument;
220 volatile cyg_uint32 command_transfer_type;
221 volatile cyg_uint32 command_response0;
222 volatile cyg_uint32 command_response1;
223 volatile cyg_uint32 command_response2;
224 volatile cyg_uint32 command_response3;
225 volatile cyg_uint32 data_buffer_access;
226 volatile cyg_uint32 present_state;
227 volatile cyg_uint32 protocol_control;
228 volatile cyg_uint32 system_control;
229 volatile cyg_uint32 interrupt_status;
230 volatile cyg_uint32 interrupt_status_enable;
231 volatile cyg_uint32 interrupt_signal_enable;
232 volatile cyg_uint32 autocmd12_status;
233 volatile cyg_uint32 host_controller_capabilities;
234 volatile cyg_uint32 watermark_level;
235 cyg_uint32 reserved1[2];
236 volatile cyg_uint32 force_event;
237 volatile cyg_uint32 adma_error_status_register;
238 volatile cyg_uint32 adma_system_address;
239 cyg_uint32 reserved[40];
240 volatile cyg_uint32 host_controller_version;
241 }host_register, *host_register_ptr;
244 extern host_register_ptr esdhc_base_pointer;
245 //extern cyg_uint32 available_mask;
247 extern void host_reset(cyg_uint32 data_transfer_width, cyg_uint32 endian_mode);
248 extern void host_cfg_clock(sdhc_freq_t);
249 extern void host_read_response(command_response_t *);
250 extern cyg_uint32 host_send_cmd(command_t *cmd);
251 extern cyg_uint32 host_data_read(cyg_uint32 *,cyg_uint32);
252 extern cyg_uint32 host_data_write(cyg_uint32 *,cyg_uint32);
253 extern void host_cfg_block(cyg_uint32 blk_len, cyg_uint32 nob);
254 extern void host_init(cyg_uint32 base_address);
255 extern void esdhc_softreset(cyg_uint32 mask);
256 /*================================================================================================*/
257 #endif /* _MXCMCI_HOST_H_ */