1 #ifndef CYGONCE_DEVS_SPI_ARM_AT91_H
2 #define CYGONCE_DEVS_SPI_ARM_AT91_H
3 //==========================================================================
7 // Atmel AT91 (ARM) SPI driver defines
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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29 // or inline functions from this file, or you compile this file and link it
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32 // License. However the source code for this file must still be made available
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Savin Zlobec <savin@elatec.si>
48 //####DESCRIPTIONEND####
50 //==========================================================================
52 #include <pkgconf/hal.h>
53 #include <pkgconf/io_spi.h>
55 #include <cyg/infra/cyg_type.h>
56 #include <cyg/hal/drv_api.h>
57 #include <cyg/io/spi.h>
59 //-----------------------------------------------------------------------------
62 typedef struct cyg_spi_at91_bus_s
64 // ---- Upper layer data ----
66 cyg_spi_bus spi_bus; // Upper layer SPI bus data
68 // ---- Lower layer data ----
70 cyg_interrupt spi_interrupt; // SPI interrupt object
71 cyg_handle_t spi_interrupt_handle; // SPI interrupt handle
72 cyg_drv_mutex_t transfer_mx; // Transfer mutex
73 cyg_drv_cond_t transfer_cond; // Transfer condition
74 cyg_bool transfer_end; // Transfer end flag
75 cyg_bool cs_up; // Chip Select up flag
78 //-----------------------------------------------------------------------------
81 typedef struct cyg_spi_at91_device_s
83 // ---- Upper layer data ----
85 cyg_spi_device spi_device; // Upper layer SPI device data
87 // ---- Lower layer data (configurable) ----
89 cyg_uint8 dev_num; // Device number
90 cyg_uint8 cl_pol; // Clock polarity (0 or 1)
91 cyg_uint8 cl_pha; // Clock phase (0 or 1)
92 cyg_uint32 cl_brate; // Clock baud rate
93 cyg_uint16 cs_up_udly; // Delay in us between CS up and transfer start
94 cyg_uint16 cs_dw_udly; // Delay in us between transfer end and CS down
95 cyg_uint16 tr_bt_udly; // Delay in us between two transfers
97 // ---- Lower layer data (internal) ----
99 cyg_bool init; // Is device initialized
100 cyg_uint8 cl_scbr; // Value of SCBR (SPI clock) reg field
101 cyg_uint8 cl_div32; // Divide SPI master clock by 32
102 } cyg_spi_at91_device_t;
104 //-----------------------------------------------------------------------------
105 // AT91 SPI exported bus
107 externC cyg_spi_at91_bus_t cyg_spi_at91_bus;
109 //-----------------------------------------------------------------------------
111 #endif // CYGONCE_DEVS_SPI_ARM_AT91_H
113 //-----------------------------------------------------------------------------