packages/devs/usb/imx/v2_0/include/usbs_imx.h

   1 //==========================================================================
   2 //
   3 //      include/usbs_imx.h
   4 //
   5 //      The interface exported by the i.MX37 or i.MX51 USB OTG device driver
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is a part of Diagnosis Package based on eCos for Freescale i.MX
  11 // Family microprocessor.
  12 // Copyright (C) 2008 Freescale Semiconductor, Inc.
  13 //
  14 // eCos is free software; you can redistribute it and/or modify it under
  15 // the terms of the GNU General Public License as published by the Free
  16 // Software Foundation; either version 2 or (at your option) any later version.
  17 //
  18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  21 // for more details.
  22 //
  23 // You should have received a copy of the GNU General Public License along
  24 // with eCos; if not, write to the Free Software Foundation, Inc.,
  25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  26 //
  27 // As a special exception, if other files instantiate templates or use macros
  28 // or inline functions from this file, or you compile this file and link it
  29 // with other works to produce a work based on this file, this file does not
  30 // by itself cause the resulting work to be covered by the GNU General Public
  31 // License. However the source code for this file must still be made available
  32 // in accordance with section (3) of the GNU General Public License.
  33 //
  34 // This exception does not invalidate any other reasons why a work based on
  35 // this file might be covered by the GNU General Public License.
  36 //
  37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  38 // at http://sources.redhat.com/ecos/ecos-license/
  39 // -------------------------------------------
  40 //####ECOSGPLCOPYRIGHTEND####
  41 //==========================================================================
  42 //#####DESCRIPTIONBEGIN####
  43 //
  44 // Author(s):    fisherz
  45 // Contributors: fisherz
  46 // Date:         2008-07-22
  47 // Purpose:
  48 //
  49 //####DESCRIPTIONEND####
  50 //==========================================================================
  51 #ifndef CYGONCE_USBS_IMX_H
  52 #define CYGONCE_USBS_IMX_H
  53
  54 #include <cyg/io/usb/usbs.h>
  55
  56 #ifdef __cplusplus
  57 extern "C" {
  58 #endif
  59
  60 //#define USBS_DEBUG    0
  61
  62 /*
  63  * This function is an exported API for application to initialize
  64  * MX37 or MX51 USB OTG in device mode from hardware to driver.
  65  */
  66 void usbs_imx_otg_device_init(void);
  67 void usbs_imx_otg_device_deinit(void);
  68 #if defined(CYGBLD_IMX_USB_DOWNLOAD_SUPPORT)
  69 void usbs_imx_otg_download(unsigned char * buffer, unsigned int length);
  70 #endif
  71 /*
  72  * The i.MX37 and 51 family comes with on-chip USB OTG support. This
  73  * provides three endpoints. Endpoint 0 can only be used for control
  74  * messages. Endpoints 1 and 2 can only be used for bulk transfers,
  75  * host->slave for endpoint 1 and slave->host for endpoint 2.
  76  */
  77 extern usbs_control_endpoint    usbs_imx_otg_ep0;
  78 extern usbs_rx_endpoint         usbs_imx_otg_ep1;
  79 extern usbs_tx_endpoint         usbs_imx_otg_ep2;
  80
  81
  82 /************************************************************************/
  83 #define BUFFER_SIZE     0x800
  84
  85 #if defined(CYGHWR_USB_DEVS_MX37_OTG)
  86 #define USB_BASE_ADDRESS 0xC3FD4000
  87 #define MX37_IRQ_USB_SERVICE_REQUEST    18      //i.MX37 USB OTG Interrupt
  88 #define MX37_IRQ_USB_PRIORITY                   99      //i.MX37 USB Interrupt Priority
  89 #define IMX_IRQ_USB_DEV_SERVICE_REQUEST MX37_IRQ_USB_SERVICE_REQUEST
  90 #define IMX_IRQ_USB_DEV_PRIORITY                MX37_IRQ_USB_PRIORITY
  91
  92 #define CCM_BASE_ADDR 0xE3F8C000
  93 #define CCM_CSCMR1_OFFSET       0x34
  94 #define CCM_CSCMR1 (CCM_BASE_ADDR + CCM_CSCMR1_OFFSET)
  95 #define REGVAL_CCM_CSCMR1 (*((volatile cyg_uint32*)CCM_CSCMR1))
  96 #define USB_MX37_SET_PHY_CLK_24MHZ() (REGVAL_CCM_CSCMR1&=(~((0x1) <<26)))
  97
  98 #define USB_IMX_SET_TD_OFFSET(offset,num) offset=num
  99 #endif
 100
 101
 102 #if defined(CYGHWR_USB_DEVS_MX51_OTG)
 103 #define USB_BASE_ADDRESS 0x73F80000
 104 #define MX51_IRQ_USB_SERVICE_REQUEST    18      //i.MX51 USB OTG Interrupt
 105 #define MX51_IRQ_USB_PRIORITY                   99      //i.MX51 USB Interrupt Priority
 106 #define IMX_IRQ_USB_DEV_SERVICE_REQUEST MX51_IRQ_USB_SERVICE_REQUEST
 107 #define IMX_IRQ_USB_DEV_PRIORITY                MX51_IRQ_USB_PRIORITY
 108
 109 #define  USB_OTG_BASE_ADDR      ((cyg_uint32)USB_BASE_ADDRESS + 0x000)
 110 #define  USB_H1_BASE_ADDR       ((cyg_uint32)USB_BASE_ADDRESS + 0x200)
 111 #define  USB_H2_BASE_ADDR       ((cyg_uint32)USB_BASE_ADDRESS + 0x400)
 112 #define  USB_H3_BASE_ADDR       ((cyg_uint32)USB_BASE_ADDRESS + 0x400)
 113 #define  USB_CONTROL_REG        ((cyg_uint32)USB_BASE_ADDRESS + 0x800)
 114 #define  USB_OTG_MIRROR_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x804)
 115 #define  USB_PHY_CTRL_0_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x808)
 116 #define  USB_PHY_CTRL_1_REG ((cyg_uint32)USB_BASE_ADDRESS + 0x80c)
 117 #define  USB_CTRL_1_REG         ((cyg_uint32)USB_BASE_ADDRESS + 0x810)
 118
 119 #define CCM_BASE_ADDR 0x73FD4000
 120 #define CCM_CSCMR1_OFFSET 0x1C
 121 #define CCM_CSCDR1_OFFSET 0x24
 122 #define CCM_CSCMR1 (CCM_BASE_ADDR + CCM_CSCMR1_OFFSET)
 123 #define CCM_CSCDR1 (CCM_BASE_ADDR + CCM_CSCDR1_OFFSET)
 124 #define CCM_CSCMR1_REGVAL (*(cyg_uint32 *)(CCM_BASE_ADDR + CCM_CSCMR1_OFFSET))
 125 #define CCM_CSCDR1_REGVAL (*(cyg_uint32 *)(CCM_BASE_ADDR + CCM_CSCDR1_OFFSET))
 126 /* CSCMR1 register */
 127 #define CSCMR1_USBOH3_PHY_CLK_SEL_MASK          0x04000000
 128 #define CSCMR1_USBOH3_PHY_CLK_SEL_VALUE         0x04000000
 129 #define CSCMR1_USBOH3_CLK_SEL_MASK                      0x00c00000
 130 #define CSCMR1_USBOH3_CLK_SEL_VALUE                     0x00400000
 131 /*CSCDR1 register config*/
 132 #define CSCDR1_USBOH3_CLK_PRED_SEL_MASK         0x00000700
 133 #define CSCDR1_USBOH3_CLK_PRED_SEL_VALUE        0x00000400  /* divide by 5 */
 134 #define CSCDR1_USBOH3_CLK_PODF_SEL_MASK         0x000000C0
 135 #define CSCDR1_USBOH3_CLK_PODF_SEL_VALUE        0x00000040  /* divide by 2 */
 136 /* CDCDR register */
 137 #define CDCDR_USB_CLK_PREDF_MASK   0x00000070
 138 #define CDCDR_USB_CLK_PREDF_VALUE  0x00000010  /* divide by 2 */
 139 #define CDCDR_USB_CLK_PODF_MASK    0x0000000E
 140 #define CDCDR_USB_CLK_PODF_VALUE   0x00000002  /* divide by 2 */
 141
 142 /*Hash Defines for PHY_CTRL_REG_1*/
 143 #define  USB_PHY_CTRL_PLLDIVVALUE_MASK  0x00000003
 144 #define  USB_PHY_CTRL_PLLDIVVALUE_19_2_MHZ  0x00000000
 145 #define  USB_PHY_CTRL_PLLDIVVALUE_24_MHZ  0x00000001
 146 #define  USB_PHY_CTRL_PLLDIVVALUE_26_MHZ  0x00000002
 147 #define  USB_PHY_CTRL_PLLDIVVALUE_27_MHZ  0x00000003
 148
 149
 150 #define USB_IMX_SET_TD_OFFSET(offset,num) offset=num//do{}while(0)
 151 #endif
 152 /************************************************************************/
 153 #define IMX_USB_INTR_DEV_SLE            (1<<8)  //DCSuspend - Sleep Enable
 154 #define IMX_USB_INTR_DEV_SRE            (1<<7)  //SOF Received Enable
 155 #define IMX_USB_INTR_DEV_RESET          (1<<6)  //USB Reset Enable
 156 #define IMX_USB_INTR_DEV_SEE            (1<<4)  //System Error Enable
 157 #define IMX_USB_INTR_DEV_PCE            (1<<2)  //Port Change Detect Enable
 158 #define IMX_USB_INTR_DEV_USBINT (1<<0)  //USBINT Enable, IOS@dQH, IOC@dTD will be available
 159
 160 #define IMX_USB_STS_DCSPD                       (1<<8)  //DCSuspend Interrupt
 161 #define IMX_USB_STS_SOFRSV                      (1<<7)  //SOF Received Interrupt
 162 #define IMX_USB_STS_RESET                       (1<<6)  //USB Reset Received Interrupt
 163 #define IMX_USB_STS_SYSERR                      (1<<4)  //System Error Interrupt, not implemented in Marley, always '0'
 164 #define IMX_USB_STS_PTCHANGE            (1<<2)  //Port Change Detect Interrupt
 165 #define IMX_USB_STS_USBINT                      (1<<0)  //USB Interrupt
 166 /************************************************************************/
 167 #define BIT0    0x00000001
 168 #define BIT1    0x00000002
 169 #define BIT2    0x00000004
 170 #define BIT3    0x00000008
 171 #define BIT4    0x00000010
 172 #define BIT5    0x00000020
 173 #define BIT6    0x00000040
 174 #define BIT7    0x00000080
 175 #define BIT8    0x00000100
 176 #define BIT9    0x00000200
 177 #define BIT10   0x00000400
 178 #define BIT11   0x00000800
 179 #define BIT12   0x00001000
 180 #define BIT13   0x00002000
 181 #define BIT14   0x00004000
 182 #define BIT15   0x00008000
 183 #define BIT16   0x00010000
 184 #define BIT17   0x00020000
 185 #define BIT18   0x00040000
 186 #define BIT19   0x00080000
 187 #define BIT20   0x00100000
 188 #define BIT21   0x00200000
 189 #define BIT22   0x00400000
 190 #define BIT23   0x00800000
 191 #define BIT24   0x01000000
 192 #define BIT25   0x02000000
 193 #define BIT26   0x04000000
 194 #define BIT27   0x08000000
 195 #define BIT28   0x10000000
 196 #define BIT29   0x20000000
 197 #define BIT30   0x40000000
 198 #define BIT31   0x80000000
 199 /* Device Queue Head and Device Transfer Descriptor Related Defination */
 200 #define SIZE_OF_QHD             0x40
 201 #define SIZE_OF_DTD0    0x20
 202 #define SIZE_OF_DTD1    0x20
 203 #define dTD_SIZE_EPIN   (SIZE_OF_DTD0 + SIZE_OF_DTD1)   //0x40
 204 #define dTD_SIZE_EPOUT  (SIZE_OF_DTD0 + SIZE_OF_DTD1)   //0x40
 205
 206 #define BUFFER_USED_PER_EP ((SIZE_OF_QHD + dTD_SIZE_EPIN) +(SIZE_OF_QHD + dTD_SIZE_EPOUT)) //0x100
 207
 208 #define ZLT_ENABLE              0
 209 #define ZLT_DISABLE     1
 210
 211 #define IOS_NOTSET              0
 212 #define IOS_SET                 1
 213
 214 #define IOC_NOTSET              0
 215 #define IOC_SET                 1
 216
 217 #define TERMINATE               1
 218 #define NOT_TERMINATE   0
 219
 220 #define NO_STATUS               0
 221 #define ACTIVE                  BIT7
 222
 223 #define EPOUT_COMPLETE  BIT0
 224 #define EPIN_COMPLETE   BIT16
 225
 226 #define EPOUT_PRIME             BIT0
 227 #define EPIN_PRIME              BIT16
 228
 229 #define EPOUT_ENABLE    BIT7
 230 #define EPIN_ENABLE     BIT23
 231
 232 #define STALL_RX                0x00000001
 233 #define STALL_TX                0x00010000
 234
 235 /* Buffer size of the buffer used for bulk data transfer */
 236
 237 #define CONTROL_BUFFER_SIZE             0x40
 238 #define BULK_BUFFER_SIZE                0x200
 239 #define NUM_OF_BULK_BUFFER              0x2
 240 #define TOTAL_DATA_BUFFER_SIZE  ((BULK_BUFFER_SIZE * NUM_OF_BULK_BUFFER) + CONTROL_BUFFER_SIZE)//512*2+64=1088
 241
 242 #define BULK_TD_BUFFER_TOTAL_SIZE       0x4000
 243 #define BULK_TD_BUFFER_PAGE_SIZE        0x1000
 244 /************************************************************************/
 245 #define USB_OTG_TRANS_MASK      0xC0000000
 246 #define USB_OTG_TRANS_SERIAL    0xC0000000
 247 #define USB_OTG_TRANS_ULPI      0x80000000
 248 #define USB_OTG_TRANS_PHILIP    0x40000000
 249 #define USB_OTG_TRANS_UTMI      0x00000000
 250 #define USB_OTG_FS_ONLY         0x01000000
 251 #define USB_OTG_TRANS_WIDTH     0x10000000
 252
 253 /***********************USB OTG Register Map*****************************/
 254 // ----------------------------------------------------------------------------
 255 // This device driver for i.MX37 has three endpoints.
 256 //
 257 // Endpoint 0 can only be used for bi-directional control messages.
 258 //
 259 // Endpoint 1 can only be used for host->slave bulk OUT transfers.
 260 //
 261 // Endpoint 2 can only be used for slave-host bulk IN transfers.
 262 //
 263 // Start with definitions of the hardware. The use of a structure and
 264 // a const base pointer should allow the compiler to do base/offset
 265 // addressing and keep the hardware base address in a register. This
 266 // is better than defining each hardware register via a separate
 267 // address. Although the registers are only a byte wide, the peripheral
 268 // bus only supports word accesses.
 269 //
 270 // The USB_OTG_ID etc. macros allow for an alternative way of
 271 // accessing the hardware if a better approach is presented, without
 272 // having to rewrite all the code. Macros that correspond to registers
 273 // are actually addresses, making it easier in the code to distinguish
 274 // them from bit values: the & and * operators will just cancel out.
 275 typedef struct usbs_imx_otg_hardware{
 276   volatile cyg_uint32 id;             //0x000, Identification Register
 277   volatile cyg_uint32 hwgeneral;      //0x004, General HW Parameters
 278   volatile cyg_uint32 hwhost;         //0x008, Host HW Parameters
 279   volatile cyg_uint32 hwdevice;       //0x00c, Device HW Parameters
 280   volatile cyg_uint32 hwtxbuf;        //0x010, TX Buffer HW Parameters
 281   volatile cyg_uint32 hwrxbuf;        //0x014, RX Buffer HW Parameters
 282                     int rsv1[26];
 283   volatile cyg_uint32 gptimer0ld;     //0x080, GP Timer0 Load Register
 284   volatile cyg_uint32 gptimer0ctrl;   //0x084, GP Timer0 Control Register
 285   volatile cyg_uint32 gptimer1ld;     //0x088, GP Timer1 Load Register
 286   volatile cyg_uint32 gptimer1ctrl;   //0x08c, GP Timer1 control register
 287   volatile cyg_uint32 sbuscfg;        //0x090, System Bus Interface Control
 288                     int rsv2[27];
 289   volatile unsigned char caplength;     //0x100, Capability Length Register
 290                     char rsv3;
 291   volatile cyg_uint16 hciversion;   //0x102, Host Interface Version Number
 292   volatile cyg_uint32 hcsparams;      //0x104, Host Control Structural Parameters
 293   volatile cyg_uint32 hccparams;      //0x108, Host Control Capability Parameters
 294                     int rsv4[5];
 295   volatile cyg_uint16 dciversion;   //0x120, Device Interface Version Number
 296                     short rsv5;
 297   volatile cyg_uint32 dccparams;      //0x124, Device Control Capability Parameters
 298                     int rsv6[6];
 299   volatile cyg_uint32 usbcmd;         //0x140, USB Command
 300   volatile cyg_uint32 usbsts;         //0x144, USB Status
 301   volatile cyg_uint32 usbintr;        //0x148, USB Interrupt Enable
 302   volatile cyg_uint32 frindex;        //0x14c, USB Frame Index
 303                     int rsv7;
 304   volatile cyg_uint32 devaddr;        //0x154, USB Device Address
 305   volatile cyg_uint32 endptlistaddr;  //0x158, Address of Endpoint list in memory
 306   volatile cyg_uint32 ttctrl;         //0x15c, TT status and control
 307   volatile cyg_uint32 burstsize;      //0x160, Programmable Burst Size
 308   volatile cyg_uint32 txfilltuning;   //0x164, Host Transmit Pre-Buffer Packet Tuning
 309   volatile cyg_uint32 txttfilltuning; //0x168,Host TT Transmit Pre-Buffer packet Tuning
 310                     int rsv8;
 311   volatile cyg_uint32 ulpiviewpoint;  //0x170, ULPI Viewport
 312                     int rsv9;
 313   volatile cyg_uint32 endptnak;       //0x178, Endpoint NAK
 314   volatile cyg_uint32 endptnaken;     //0x17c, Endpoint NAK Enable
 315   volatile cyg_uint32 configflag;     //0x180, Configured Flag Register
 316   volatile cyg_uint32 portsc1;      //0x184~0x1a0, Port Status/Control 1~8
 317         volatile cyg_uint32 portsc2;
 318         volatile cyg_uint32 portsc3;
 319         volatile cyg_uint32 portsc4;
 320         volatile cyg_uint32 portsc5;
 321         volatile cyg_uint32 portsc6;
 322         volatile cyg_uint32 portsc7;
 323         volatile cyg_uint32 portsc8;
 324   volatile cyg_uint32 otgsc;          //0x1a4, OTG Status and Control
 325   volatile cyg_uint32 usbmode;        //0x1a8, USB Device Mode
 326   volatile cyg_uint32 endptsetupstat; //0x1ac,Endpoint Setup Status
 327   volatile cyg_uint32 endptprime;     //0x1b0, Endpoint Initialization
 328   volatile cyg_uint32 endptflush;     //0x1b4, Endpoint De-Initialization
 329   volatile cyg_uint32 endptstatus;    //0x1b8, Endpoint Status
 330   volatile cyg_uint32 endptcomplete;  //0x1bc, Endpoint Complete
 331   volatile cyg_uint32 endptctrl[16];  //0x1c0~0x1fc, Endpoint Control 0~15
 332 }usbs_imx_otg_hardware;
 333 /*************************usb structures typedefs*************************/
 334 //-----------------------------------------------
 335 //USB buffer data structure
 336 typedef struct {
 337     cyg_uint32 buffer_address;
 338     cyg_uint32 buffer_size;
 339 }usb_plat_config_data_t;
 340
 341 //setup data for Queue Header
 342 typedef struct dqh_setup_t{
 343         cyg_uint32 dqh_word0;
 344         cyg_uint32 dqh_word1;
 345         cyg_uint32 dqh_word2;
 346         cyg_uint32 dqh_word3;
 347         cyg_uint32 dqh_word4;
 348         cyg_uint32 dqh_word5;
 349         cyg_uint32 dqh_word6;
 350         cyg_uint32 dqh_word7;
 351         cyg_uint32 dqh_word8;
 352         cyg_uint32 dqh_word9;
 353         cyg_uint32 dqh_word10;
 354         cyg_uint32 dqh_word11;
 355 } dqh_setup_t;
 356 //setup data for Transfer Descriptor
 357 typedef struct dtd_setup_t {
 358         cyg_uint32 dtd_word0;
 359         cyg_uint32 dtd_word1;
 360         cyg_uint32 dtd_word2;
 361         cyg_uint32 dtd_word3;
 362         cyg_uint32 dtd_word4;
 363         cyg_uint32 dtd_word5;
 364         cyg_uint32 dtd_word6;
 365         cyg_uint32 dtd_word7;
 366 } dtd_setup_t;
 367
 368 //structure for Queue Header
 369 typedef struct dqh_t {
 370         cyg_uint32 dqh_base;
 371         cyg_uint32 next_link_ptr;
 372         cyg_uint32 buffer_ptr0;
 373         cyg_uint32 buffer_ptr1;
 374         cyg_uint32 buffer_ptr2;
 375         cyg_uint32 buffer_ptr3;
 376         cyg_uint32 buffer_ptr4;
 377         cyg_uint16 total_bytes;
 378   cyg_uint16 mps;
 379   cyg_uint16 current_offset;
 380   cyg_uint8 zlt;
 381   cyg_uint8 ios;
 382   cyg_uint8 terminate;
 383   cyg_uint8 ioc;
 384   cyg_uint8 status;
 385 }dqh_t;
 386
 387 //structure for Transfer Descriptor
 388 typedef struct dtd_t {
 389         cyg_uint32 dtd_base;
 390         cyg_uint32 next_link_ptr;
 391         cyg_uint32 buffer_ptr0;
 392         cyg_uint32 buffer_ptr1;
 393         cyg_uint32 buffer_ptr2;
 394         cyg_uint32 buffer_ptr3;
 395         cyg_uint32 buffer_ptr4;
 396         cyg_uint16 total_bytes;
 397         cyg_uint16 current_offset;
 398         cyg_uint8 terminate;
 399         cyg_uint8 ioc;
 400         cyg_uint8 status;
 401 }dtd_t;
 402
 403 //structure for Transfer Descriptor layout
 404 typedef volatile struct TransferDescriptor {
 405         unsigned terminal                       :1      ;
 406         unsigned rsv1                           :4      ;
 407         unsigned nxt_pt                         :27     ;
 408
 409         unsigned status                         :8      ;
 410         unsigned rsv2                           :2      ;
 411         unsigned multo                          :2      ;
 412         unsigned rsv3                           :3      ;
 413         unsigned ioc                            :1      ;
 414         unsigned totalbytes                     :15     ;
 415         unsigned rsv4                           :1      ;
 416
 417         unsigned offset                         :12     ;
 418         unsigned bufferptr0                     :20     ;
 419
 420         unsigned frame_num                      :11     ;
 421         unsigned rsv5                           :1      ;
 422         unsigned bufferptr1                     :20     ;
 423
 424         unsigned rsv6                           :12     ;
 425         unsigned bufferptr2                     :20     ;
 426
 427         unsigned rsv7                           :12     ;
 428         unsigned bufferptr3                     :20     ;
 429
 430         unsigned rsv8                           :12     ;
 431         unsigned bufferptr4                     :20     ;
 432 }__attribute__((packed)) TransferDescriptor;
 433
 434 //structure for Queue Header layout
 435 typedef volatile struct QueueHeader {
 436         unsigned rsv1                           :15             ;
 437         unsigned ios                            :1              ;
 438         unsigned mps                            :11             ;
 439         unsigned rsv2                           :2              ;
 440         unsigned zlt                            :1              ;
 441         unsigned mult                           :2              ;
 442
 443         unsigned rsv3                           :5              ;
 444         unsigned current_dtd            :27             ;
 445
 446         struct TransferDescriptor       dtd             ;
 447
 448         unsigned rsv4                           :32             ;
 449
 450         unsigned setupbuf0                      :8              ;
 451         unsigned setupbuf1                      :8              ;
 452         unsigned setupbuf2                      :8              ;
 453         unsigned setupbuf3                      :8              ;
 454
 455         unsigned setupbuf4                      :8              ;
 456         unsigned setupbuf5                      :8              ;
 457         unsigned setupbuf6                      :8              ;
 458         unsigned setupbuf7                      :8              ;
 459 }__attribute__((packed)) QueueHeader;
 460
 461 //bulk buffer status
 462 enum {
 463         BUFFER_FREED,
 464         BUFFER_RELEASED,
 465         BUFFER_ALLOCATED
 466 };
 467
 468 //structure of bulk buffer
 469 typedef struct {
 470         unsigned char * buffer;
 471         cyg_uint32    stat;
 472 }bulk_buffer_t;
 473
 474 //bulk buffer status
 475 enum {
 476         MASS_STORAGE_CBW_TYPE = 1,
 477         MASS_STORAGE_DATA_TYPE
 478 };
 479
 480 //structure of USB buffer map
 481 typedef struct {
 482     cyg_uint32 ep_dqh_base_addrs;       /* Base Address of Queue Header */
 483     cyg_uint32 ep_dtd_base_addrs;       /* Base Address of Transfer Descriptor */
 484     cyg_uint32 ep0_buffer_addrs;        /* Buffer Addres for EP0 IN  */
 485     cyg_uint32 buffer1_address;         /* Buffer1 address for bulk transfer */
 486     cyg_uint32 buffer1_status;          /* Status of Buffer1 */
 487     cyg_uint32 buffer2_address;         /* Buffer2 address for bulk transfer */
 488     cyg_uint32 buffer2_status;          /* Status of Buffer2 */
 489 }buffer_map_t;
 490
 491 //Data Structure used for configuring the Endpoints.
 492 typedef struct {
 493     cyg_uint8  end_pt_no;                                       /* Endpoint number */
 494     cyg_uint8  direction;                                       /* Direction of endpoint */
 495     cyg_uint8  transfer_type;                   /* type of transfer supporting on the endpoint */
 496     cyg_uint16  max_pkt_size;                   /* maximum packet size in bytes */
 497 }usb_end_pt_info_t;
 498
 499 //Buffer descriptor used for data transfer on USB
 500 typedef struct {
 501     void * buffer ;                                                             /* Address of the buffer to/from data is to be transmitted */
 502     cyg_uint32 size ;                   /*  size of the buffer to  be transmitted/recieved */
 503     cyg_uint32 bytes_transfered;        /* actual number of bytes transfered */
 504 }usb_buffer_descriptor_t;
 505
 506 /*************************important constant in usb transaction*************************/
 507 /* Maximum packet size defination */
 508 #define MPS_8           8
 509 #define MPS_64          64
 510
 511 #define SETUP_DATA_LENGTH                       0x8
 512 #define ENDPT_NUMBER_MASK                       0x0F
 513 #define ENDPT_DIR_MASK                          0x80
 514 #define ENDPT_DIR_SHIFT                         0x7
 515 #define ENDPT_TRNS_TYPE_MASK            0x03
 516
 517 #define USB_MAX_DEVICE_ADDR                     127
 518 #define USB_DEV_VALUE_OF_UNCONFIG       0x0
 519
 520 #define USB_DEV_CONFIG_DESC_CONFIG_VALUE        0x01
 521 /* Default device address */
 522 #define USB_DEFAULT_ADDR                        0x00
 523
 524 /* DESCRIPTOR Type */
 525 #define DEVICE_DESC                                     0x1
 526 #define CONF_DESC                                       0x2
 527 #define STRING_DESC                                     0x3
 528 #define INTERFACE_DESC                          0x4
 529 #define ENDPOINT_DESC                           0x5
 530 #define DEVICE_QUALIFIER                        0x6
 531 #define OTHER_SPEED_CONF_DESC           0x7
 532
 533 /* String SUB DESCRIPTOR type */
 534 #define STR_DES0                                        0x0
 535 #define STR_DES1                                        0x1
 536 #define STR_DES2                                        0x2
 537 #define STR_DES3                                        0x3
 538 #define STR_DES4                                        0x4
 539 #define STR_DES5                                        0x5
 540
 541 /* Descriptor Index */
 542 #define FILL_DEVICE_DESC                        0x1
 543 #define FILL_DEVICE_QF_DESC                     0x2
 544 #define FILL_CONF_DESC                          0x3
 545 #define FILL_OT_CONF_DESC                       0x4
 546 #define FILL_STR_DES0                           0x5
 547 #define FILL_STR_DES1                           0x6
 548 #define FILL_STR_DES2                           0x7
 549 #define FILL_STR_DES3                           0x8
 550 #define FILL_SN_DESC                            0x9     //mandatory descriptor for mass storage device
 551
 552 #define LEN_OF_CONFIG_VALUE                     0x1
 553
 554 #define NUM_OF_ENDPT_OFFSET             0x4
 555 #define CONFIG_NUMBER_OFFSET            0x5
 556 #define STRING_DESC_LEN_OFFSET          0x0
 557 #define DEVICE_DESC_LEN_OFFSET          0x0
 558 #define CONF_DESC_LEN_OFFSET            0x0
 559 #define INF_DESC_LEN_OFFSET                     0x0
 560 #define EP_DESC_LEN_OFFSET                      0x0
 561
 562 /*************************usb enums typedefs*************************/
 563 typedef enum {
 564         USB_DEFAULT_STATE,
 565         USB_ADDRESSED_STATE,
 566         USB_CONFIGURED_STATE,
 567         USB_SUSPENDED_STATE
 568 } USB_DEVICE_STATE_T;
 569
 570 /* USB Device State which are handled by DCD */
 571 typedef enum
 572 {
 573     USB_DEV_DUMMY_STATE,
 574     USB_DEV_DEFAULT_STATE,
 575     USB_DEV_ADDRESSED_STATE,
 576     USB_DEV_CONFIGURED_STATE
 577 }usb_state_t;
 578
 579 /* Status of all transaction on USB */
 580 typedef enum
 581 {
 582     USB_SUCCESS,
 583     USB_FAILURE,
 584     USB_INVALID = -1 /* Always Keep this entry in last */
 585 }usb_status_t;
 586
 587 /* enum for endpoint numbers */
 588 enum
 589 {
 590     EP0,
 591     EP1,
 592     EP2,
 593     EP3,
 594     EP4,
 595     EP5
 596 };
 597
 598 enum
 599 {
 600     OUT,
 601     IN
 602 };
 603 /* enum for data transfer type on endpoints */
 604 enum
 605 {
 606     CONTROL,
 607     ISOCHRONOUS,
 608     BULK,
 609     INTERRUPT
 610 };
 611
 612 /* Constants defined to represent the elements within the setup packet. */
 613 enum
 614 {
 615     BMREQUESTTYPE,
 616     BREQUEST,
 617     WVALUE_LOWBYTE,
 618     WVALUE_HIGHBYTE,
 619     WINDEX_LOWBYTE,
 620     WINDEX_HIGHBYTE,
 621     WLENGTH_LOWBYTE,
 622     WLENGTH_HIGHBYTE
 623 };
 624
 625 /* Enum constants for function to identify the USB Standard Request defined
 626  * in USB Specification.
 627  */
 628 enum
 629 {
 630    USB_GET_STATUS,
 631    USB_CLEAR_FEATURE,
 632    USB_RESERVED_REQ_ONE,
 633    USB_SET_FEATURE,
 634    USB_RESERVED_REQ_TWO,
 635    USB_SET_ADDRESS,
 636    USB_GET_DESCRIPTOR,
 637    USB_SET_DESCRIPTOR,
 638    USB_GET_CONFIGURATION,
 639    USB_SET_CONFIGURATION,
 640    USB_GET_INTERFACE,
 641    USB_SET_INTERFACE,
 642    USB_SYNCH_FRAME
 643 };
 644
 645 /* Mass Storage Class-specific request
 646  */
 647 enum{
 648         USB_MSC_GET_MAX_LUN=0xFE,
 649         USB_MSC_BOT_RESET
 650 };
 651 #define USB_REQTYPE_RESET       0x21
 652 #define USB_REQTYE_GETMAXLUN    0xA1
 653
 654 /* Status of the buffer used for bulk transfer */
 655 enum {
 656     BUFFER_FREE,
 657     BUFFER_IN_USE
 658 };
 659
 660 /***********************usb_descriptor_definitions*************************/
 661 #define VID     0x15A2
 662 #define PID     0x002C
 663
 664 /* Constants defined to represent device descriptor elements. */
 665 #define USB_DEV_DESC_LEN                                 0x12
 666 #define USB_DEV_DESC_TYPE                                0x01
 667 #define USB_DEV_DESC_SPEC_LB                             0x00
 668 #define USB_DEV_DESC_SPEC_HB                             0x02
 669 #define USB_DEV_DESC_DEV_CLASS                           0x00  /*ROM Code definition*///0x02    /* Fisher: CDC bDeviceClass */
 670 #define USB_DEV_DESC_DEV_SUBCLASS                                                0x00   //0x02  /* Fisher: Abstract Control Model*/
 671 #define USB_DEV_DESC_DEV_PROTOCOL                        0x00
 672 #define USB_DEV_DESC_EP0_MAXPACKETSIZE                   0x40
 673 #define USB_DEV_DESC_VENDORID_LB                         (VID & 0x00FF)
 674 #define USB_DEV_DESC_VENDORID_HB                         ((VID & 0xFF00) >> 0x8)
 675 #define USB_DEV_DESC_PRODUCTID_LB                        (PID & 0x00FF)
 676 #define USB_DEV_DESC_PRODUCTID_HB                        ((PID & 0xFF00) >> 0x8)
 677 #define USB_DEV_DESC_DEV_RELEASE_NUM_LB                  0x01
 678 #define USB_DEV_DESC_DEV_RELEASE_NUM_HB                  0x00
 679 #define USB_DEV_DESC_DEV_STRING_IND_MANUFACTURE          0x01
 680 #define USB_DEV_DESC_DEV_STRING_IND_PRODUCT              0x02
 681 #if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
 682 #define USB_DEV_DESC_DEV_STRING_IND_SERIAL_NUM           0x00
 683 #else
 684 #define USB_DEV_DESC_DEV_STRING_IND_SERIAL_NUM           0x05 /*for mass storage device, it must >0*/
 685 #endif
 686 #define USB_DEV_DESC_DEV_NUM_CONFIGURATIONS              0x01
 687
 688
 689
 690 /* Constants defindes to represent elements of configuration descriptor. */
 691
 692 #define USB_DEV_CONFIG_DESC_LEN                          0x09 /* Length of configuration descriptor. */
 693 #define USB_DEV_CONFIG_DESC_TYPE                         0x02 /* Descriptor type. */
 694 #define USB_DEV_CONFIG_DESC_TTL_LEN_LB                   0x20 /* Total length of configuration information. */
 695 #define USB_DEV_CONFIG_DESC_TTL_LEN_HB                   0x00 /* Total length of configuration information. */
 696 #define USB_DEV_CONFIG_DESC_NUM_0F_INF                   0x01 /* Number of interfaces in this configuration. */
 697 #define USB_DEV_CONFIG_DESC_CONFIG_VALUE                 0x01 /* Configuration value. */
 698 #if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
 699 #define USB_DEV_CONFIG_DESC_STRING_INDEX                 0x04 /* String index for this configuration. */
 700 #else
 701 #define USB_DEV_CONFIG_DESC_STRING_INDEX                 0x00 /* String index for this configuration. */
 702 #endif
 703 #define USB_DEV_CONFIG_DESC_ATTRIBUTES                   0xC0/*  Self powered and supported remote wakeup. */
 704                                                                                                                                 /* 0x80 Self powered and supported remote wakeup. */
 705
 706 #define USB_DEV_CONFIG_DESC_MAX_POWER                    0x32 /* 100ma,Max power consumed by phone. */
 707
 708 #define USB_DEV_INF_DESC_LEN                             0x09 /* Interface descriptor length. */
 709 #define USB_DEV_INF_DESC_TYPE                            0x04 /* The descriptor type, 4 interface descriptor. */
 710 #define USB_DEV_INF_DESC_INF_INDEX                       0x00 /* Interface index. */
 711 #define USB_DEV_INF_DESC_ALT_SETTING                     0x00 /* The alternate setting is 0. */
 712 #define USB_DEV_INF_DESC_NUM_OF_EP                       0x02 /* Control endpoint and data endpoint 1 and 2. */
 713 #define USB_DEV_INF_DESC_INF_CLASS_VENDOR                0xFF /* Interface class: Vendor Specific. */
 714 #define USB_DEV_INF_DESC_INF_CLASS_MSC                   0x08 /* Interface class: Mass Storage. */
 715 #define USB_DEV_INF_DESC_INF_SUBCLASS_S_BLANK                                            0x40 /* (Subclass) Motorola Flash Download. */
 716 #define USB_DEV_INF_DESC_INF_SUBCLASS_NS_BLANK           0x42
 717 #define USB_DEV_INF_DESC_INF_SUBCLASS_MSC_SCSI           0x06   /* SCSI transparent command set for mass storage*/
 718 #define USB_DEV_INF_DESC_INF_PROTOCOL                    0x01 /* (Interface protocol) Vendor Specific, ROM bootloader interface. */
 719 #define USB_DEV_INF_DESC_INF_PROTOCOL_MSC_BOT                                            0x50   /* Mass Storage Bulk Only Transport*/
 720 #if defined(CYGHWR_IMX_USB_DOWNLOAD_SUPPORT)
 721 #define USB_DEV_INF_DESC_STRING_INDEX                    0x05  /* Index of interface string descriptor. */
 722 #else
 723 #define USB_DEV_INF_DESC_STRING_INDEX                    0x04  /* Index of interface string descriptor. */
 724 #endif
 725
 726 /* Constants defined to represent the endpoint descriptor elements. */
 727 #define USB_MAX_PACKET_SIZE                     0x0200
 728 #define USB_MAX_PACKET_SIZE_LO          (USB_MAX_PACKET_SIZE&0xFF)
 729 #define USB_MAX_PACKET_SIZE_HI          ((USB_MAX_PACKET_SIZE>>8)&0xFF)
 730
 731 /* Endpoint 1 descriptor. */
 732 #define USB_EP1_DESC_SIZE                                0x07 /* Size of descriptor in bytes. */
 733 #define USB_EP1_DESC_TYPE                                0x05 /* Descriptor type. */
 734 #define USB_EP1_DESC_EP_ADDR                             0x01 /* (Endpoint address) Endpoint 1, OUT. */
 735 #define USB_EP1_DESC_ATTRIBUTES                          0x02 /* (Attributes) Bulk Endpoint. */
 736 #define USB_EP1_DESC_MAX_PACKET_SIZE_FS_LB               0x40 /* Max Packet Size. */
 737 #define USB_EP1_DESC_MAX_PACKET_SIZE_FS_HB               0x00 /* Max Packet Size. */
 738 #define USB_EP1_DESC_MAX_PACKET_SIZE_HS_LB               USB_MAX_PACKET_SIZE_LO /* Max Packet Size. */
 739 #define USB_EP1_DESC_MAX_PACKET_SIZE_HS_HB               USB_MAX_PACKET_SIZE_HI /* Max Packet Size. */
 740 #define USB_EP1_DESC_INTERVAL                            0x00 /* Interval, ignored. */
 741 #define USB_EP1_DESC_INTERVAL_HS                         0x01 /* at most 1NAK. */
 742 /* Endpoint 2 descriptor. */
 743 #define USB_EP2_DESC_SIZE                                0x07 /* Size of descriptor in bytes. */
 744 #define USB_EP2_DESC_TYPE                                0x05 /* Descriptor type. */
 745 #define USB_EP2_DESC_EP_ADDR                             0x82 /* (Endpoint address) Endpoint 2, IN. */
 746 #define USB_EP2_DESC_ATTRIBUTES                          0x02 /* (Attributes) Bulk Endpoint. */
 747 #define USB_EP2_DESC_MAX_PACKET_SIZE_FS_LB               0x40 /* Max Packet Size. */
 748 #define USB_EP2_DESC_MAX_PACKET_SIZE_FS_HB               0x00 /* Max Packet Size. */
 749 #define USB_EP2_DESC_MAX_PACKET_SIZE_HS_LB               USB_MAX_PACKET_SIZE_LO/* Max Packet Size. */
 750 #define USB_EP2_DESC_MAX_PACKET_SIZE_HS_HB               USB_MAX_PACKET_SIZE_HI /* Max Packet Size. */
 751
 752 #define USB_EP2_DESC_INTERVAL                            0x00 /* Interval, ignored. */
 753 #define USB_EP2_DESC_INTERVAL_HS                                                 0x01 /* at most 1NAK. */
 754 /* String Descriptor 0 */
 755 #define USB_STR0_DESC_SIZE                               0x04 /* Size of descriptor in bytes. */
 756 #define USB_STR0_DESC_TYPE                               0x03 /* Descriptor type. */
 757 #define USB_LANGUAGE_ID_LB                                                               0x09 /* Language id of english */
 758 #define USB_LANGUAGE_ID_HB                                                               0x04 /* Language id of english */
 759
 760 /* String Descriptor 1 */
 761 #define USB_STR1_DESC_SIZE                                0x3A /* Size of descriptor in bytes. */
 762 #define USB_STR1_DESC_TYPE                                0x03 /* Descriptor type. */
 763
 764 /* String Descriptor 2 */
 765 #define USB_STR2_DESC_SIZE_NS                             0x20 /* Size of descriptor in bytes for Non Secure Download*/
 766 #define USB_STR2_DESC_SIZE_SE                             0x20 /* Size of descriptor in bytes for Secure Engg. download*/
 767 #define USB_STR2_DESC_SIZE_S                              0x20 /* Size of descriptor in bytes for Secure production download*/
 768 #define USB_STR2_DESC_TYPE                                0x03 /* Descriptor type. */
 769
 770 /* String Descriptor 3 */
 771 #define USB_STR3_DESC_SIZE                                0x20 /* Size of descriptor in bytes. */
 772 #define USB_STR3_DESC_TYPE                                0x03 /* Descriptor type. */
 773
 774 /* Serial number string descriptor */
 775 #define USB_SN_DESC_LEN                                                                 0x1A /* Size of descriptor length*/
 776 #define USB_SN_DESC_TYPE                                                                0x03 /* type of descriptor*/
 777 /*************************usb descriptor typedefs********************/
 778 typedef struct {
 779         usb_configuration_descriptor usb_config_desc;
 780     usb_interface_descriptor  usb_interface_desc;
 781     usb_endpoint_descriptor  usb_endpoint_desc[USB_DEV_INF_DESC_NUM_OF_EP];
 782 }__attribute__((packed)) usb_conf_desc;
 783 /* USB device serial number for mass storage requiremen*/
 784 typedef struct {
 785         cyg_uint8  length;
 786         cyg_uint8  descriptor_type;
 787         cyg_uint8  string[24];
 788 }__attribute__((packed)) usb_str4_desc;
 789 /* USB string Descriptor structure 0 according to USB2.0 Specification */
 790 typedef struct {
 791     cyg_uint8  length;
 792     cyg_uint8  descriptor_type;
 793     cyg_uint8  language_id0_l;
 794     cyg_uint8  language_id0_h;
 795 }__attribute__((packed)) usb_str0_desc;
 796
 797 /* USB string Descriptor structure 1 according to USB2.0 Specification */
 798 typedef struct {
 799     cyg_uint8  length;
 800     cyg_uint8  descriptor_type;
 801     cyg_uint8  string[56];
 802 }__attribute__((packed)) usb_str1_desc;
 803
 804 /* USB string Descriptor structure 2 according to USB2.0 Specification */
 805 typedef struct {
 806     cyg_uint8  length;
 807     cyg_uint8  descriptor_type;
 808     cyg_uint8  string[34];
 809 }__attribute__((packed)) usb_str2_desc;
 810
 811 /* USB string Descriptor structure 3 according to USB2.0 Specification */
 812 typedef struct {
 813     cyg_uint8  length;
 814     cyg_uint8  descriptor_type;
 815     cyg_uint8  string[30];
 816 }__attribute__((packed)) usb_str3_desc;
 817
 818 #define usb_dev_desc usb_device_descriptor      //rename the structure
 819
 820 /* ALL USB Descriptors for both FS and HS */
 821 typedef struct {
 822     usb_dev_desc*  device_desc;
 823     usb_conf_desc* config_desc;
 824         usb_str4_desc*   sn_desc;
 825     usb_str0_desc* str_desc0;
 826     usb_str1_desc* str_desc1;
 827     usb_str2_desc* str_desc2;
 828     usb_str3_desc* str_desc3;
 829
 830 }usb_descriptor;
 831
 832 #ifdef __cplusplus
 833 } /* extern "C" { */
 834 #endif
 835
 836
 837 #endif /* CYGONCE_USBS_IMX_H */